AOZ5049QI
High-Current, High-Performance
DrMOS Power Module
General Description
Features
The AOZ5049QI is a high efficiency synchronous buck
power stage module consisting of two asymmetrical
MOSFETs and an integrated driver. The MOSFETs are
individually optimized for operation in the synchronous
buck configuration. The High Side (HS) MOSFET is
optimized to achieve low capacitance and gate charge
for fast switching with low duty cycle operation. The Low
Side (LS) MOSFET has ultra low on-resistance to
minimize conduction loss. The compact 3.5mm x 5mm
QFN package is optimally chosen and designed to
minimize parasitic inductance for minimal EMI signature.
4.5V to 25V power supply range
The AOZ5049QI is intended for use with TTL and tri-state
compatibility by using both the PWM and /or FCCM inputs
for accurate control of the power MOSFETs.
A number of features provided make the AOZ5049QI a
highly versatile power module. The bootstrap supply
diode is integrated in the driver. The LS MOSFET can be
driven into diode emulation mode to provide
asynchronous operation when required. The pinout is
optimized for low inductance routing of the converter,
keeping the parasitics and their effects to a minimum.
4.5V to 5.5V driver supply range
Up to 35A output current
Integrated bootstrap Schottky diode
Up to 2MHz switching operation
Tri-state FCCM/PWM input compatible
Under-voltage lockout protection
Single pin control for shutdown/diode emulation/CCM
operation
Small 3.5mm x 5mm QFN-24L package
Applications
Servers
Notebook computers
VRMs for motherboards
Point-of-load DC/DC converters
Memory and graphic cards
Video gaming consoles
Typical Application Circuit
4.5V to 25V
VIN
AOZ5049QI
Cboot
FCCM
Controller
Cvin
BOOT
Drive Logic
and
Delay
VSWH
L
VOUT
PWM
Cout
PGND
PGND
VCC
PGND
PGND
Cvcc
+5
Rev. 3.0 June 2016
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Page 1 of 14
AOZ5049QI
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ5049QI
-40°C to +85°C
3.5mm x 5mm QFN-24L
RoHS
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
VCC
NC
VIN
PGND
GL
GL
PGND
PGND
23
22
21
20
19
18
17
11
12
PGND
VIN
PGND
5
10
VSWH
PGND
PGND
4
9
GH
VIN
PGND
3
8
BOOT
VIN
2
7
FCCM
VIN
1
6
PWM
24
Pin Configuration
16
VSWH
15
VSWH
14
VSWH
13
VSWH
3.5mm x 5mm QFN-24
(Top View)
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Page 2 of 14
AOZ5049QI
Pin Description
Pin Number
Pin Name
Pin Function
1
PWM
PWM input signal from the controller IC. This input is compatible with 5V and Tri-State logic
level Low Side.
2
FCCM
Continuous conduction mode of operation is allowed when FCCM = High.
Discontinuous mode is allowed and diode emulation mode is active when FCCM = Low.
High impedance on the input of FCCM will shutdown both HS and LS MOSFETs.
3
BOOT
HS MOSFET Gate Driver supply rail (5V wrt VSWH). Connect a 100nF ceramic
capacitor between BOOT and the VSWH (Pin 5).
4
GH
5
VSWH
6, 7, 8
VIN
Power stage high voltage input pin.
9, 10, 11, 12,
17, 18
PGND
Power Ground pin for power stage.
13, 14, 15, 16
VSWH
Switching node connected to the source of HS MOSFET and the drain of LS MOSFET. These
pins are being used for Zero Cross Detect, Bootstrap UVLO and Anti-Overlap Control.
19, 20
GL
21
PGND
22
VIN
Power stage high voltage input pin.
23
NC
No Connect. Optional connection to Pin 24 rendering no effect in performance and operation.
24
VCC
HS MOSFET Gate pin.
Switching node connected to the source of HS MOSFET and the drain of LS MOSFET. This
pin is dedicated for bootstrap capacitor connection to the BOOT pin. It is optional to connect to
Pin 13 externally on PCB.
LS MOSFET Gate pin.
Power Ground pin for LS MOSFET Gate Driver.
Serves as Input Bias and LS MOSFET Gate Driver Rail. Connect a 2.2µF MLCC directly
across to this pin and PGND (Pin 21).
Functional Block Diagram
VCC
BOOT
VIN
VCC
DCM/CCM
Enable
Tri-State
SD Logic
FCCM
REF/BIAS
UVLO
GH
Control
Logic
HS
Tri-State
Clamps
VCC
Sequencing
and
Propagation
Delay Bank
Control
Logic
HS
Output
Check
LS
PWM/
Tri-State
Logic
HS Gate
Driver
Driver
Logic
LS Min ON
PWM
Level
Translator
VSWH
BST
UVLO
ZCD
PWM
Tri-State
Irev
LS Check
Voff
VCC
LS Gate
Driver
GL
PGND
PGND
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Page 3 of 14
AOZ5049QI
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum ratings may damage the
device.
Parameter
Rating
Parameter
Low Voltage Supply (VCC)
-0.3V to 7V
High Voltage Supply (VIN)
-0.3V to 30V
Control Inputs (PWM, FCCM)
-0.3V to (VCC+0.3V)
Bootstrap Voltage DC
(BOOT-PGND)
-0.3V to 33V
Bootstrap Voltage DC
(BOOT-VSWH)
-0.3V to 7V
BOOT Voltage Transient (1)
(BOOT-VSWH)
-0.3V to 9V
Switch Node Voltage DC (VSWH)
-0.3V to 30V
Switch Node Voltage Transient(1)
(VSWH)
-0.3V to 38V
High Side Gate Voltage DC (GH)
(VSWH-0.3V) to BOOT
High Side Gate Voltage
Transient(2) (GH)
Rating
High Voltage Supply (VIN)
4.5V to 25V
Low Voltage Supply
{VCC, (BOOT-VSWH)}
4.5V to 5.5V
Control Inputs (PWM, FCCM)
Operating Frequency
0V to (VCC-0.3V)
200kHz to 2MHz
(VSWH-5V) to BOOT
Low Side Gate Voltage DC (GL)
(PGND-0.3V) to
(VCC+0.3V)
Low Side Gate Voltage
Transient(2) (GL)
(PGND-2.5V) to
(VCC+0.3V)
Storage Temperature (TS)
-65°C to +150°C
Max Junction Temperature (TJ)
ESD Rating
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
(3)
125°C
2kV
Notes:
1. Peak voltages can be applied for 10ns per switching cycle.
2. Peak voltages can be applied for 20ns per switching cycle.
3. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5k in series with 100pF.
Rev. 3.0 June 2016
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AOZ5049QI
Electrical Characteristics(4)
TA = 25°C, VIN = 12V, VCC = 5V unless otherwise specified.
Symbol
Parameter
VIN
Power Stage Power Supply
VCC
Driver Power Supply
RJC
RJA
Thermal Resistance
Conditions
VCC = 5V
Min.
Typ.
Max.
Units
4.5
25
V
4.5
5.5
V
PCB Temp = 100°C
3
°C / W
AOS Demo Board
10
°C / W
VCC Rising
3.4
VCC Falling
500
mV
3
A
INPUT SUPPLY AND UVLO
VCC
VCC_HYST
IVCC_SD
Under-Voltage Lockout
Shutdown Bias Supply Current
Control Circuit Bias Current
IVCC
Switching Current (IBIAS +
IDRV)
FCCM = Floating (Shutdown)
VPWM = Internally Pulled Low
3.9
V
FCCM = 5V (CCM), VPWM = Floating
80
A
FCCM = 0V (DCM), VPWM = Floating
120
A
FCCM = 5V, VPWM = 800kHz
27
mA
FCCM = 5V, VPWM = 1MHz
34
mA
FCCM = 5V, VPWM = 1.5MHz
48
mA
PWM INPUT
VPWMH
PWM Input High Threshold
VPWM Rising, VCC = 5V
VPWML
PWM Input Low Threshold
VPWM Falling, VCC = 5V
IPWM
PWM Pin Input Current
VTRI
PWM Input Tri-State
Threshold Window
4.1
V
0.7
V
Source, PWM = 5V
+250
A
Sink, PWM = 0V
-250
A
PWM = High Impedance
1.1
FCCM Rising, VCC = 5V
Shutdown CCM
3.8
3.9
V
FCCM INPUT
VFCCMH
FCCM Enable Threshold
VFCCML
IFCCM
VTRI
VTRI_HYST
tPTS
FCCM Pin Input Current
V
FCCM Falling, VCC = 5V
Shutdown DCM
1.2
V
Source, FCCM = 5V
+50
A
Sink, FCCM = 0V
-50
A
FCCM Input Tri-State
Threshold Window
FCCM = High Impedance
FCCM Input Threshold
Hysteresis
Shutdown CCM Shutdown
DCM Shutdown DCM
PS4 Exit Latency
VCC = 5V
1.4
3.4
300
V
mV
15
s
GATE DRIVER TIMING
tPDLU
PWM Falling to GH Turn-Off
PWM 10%, GH 90%
18
ns
tPDLL
PWM Raising to GL Turn-Off
PWM 90%, GL 90%
25
ns
tPDHU
GL Falling to GH Rising
Deadtime
GL 10%, GH 10%
20
ns
tPDHL
GH/VSWH Falling to GL Rising
Deadtime
tTSSHD
VSWH @ 1V, GL 10%
20
ns
Tri-State Shutdown Delay
TS to GH Falling, TS to GL Falling
175
ns
tPTS
Tri-State Propagation Delay
TS Exit
35
ns
tLGMIN
Low-Side Minimum On-Time
FCCM = 0V
350
ns
Notes:
4. All voltages are specified with respect to the corresponding PGND pin
5. Characterisation value. Not tested in production.
Rev. 3.0 June 2016
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Page 5 of 14
AOZ5049QI
Timing Diagram
PWM
tPDLL
GL
tPDHL
10%
tPDLU
GH
tPDHU
VSWH
1V
Figure 1. PWM Logic Input Timing Diagram
PWM
tTSSHD
tTSSHD
tTSSHD
tTSSHD
GL
tPTS
tPTS
tPTS
tPTS
GH
Figure 2. PWM Tri-State Input Logic Timing Diagram
CCM
2.5V
FCCM
DCM
PWM
(Float)
2.5V
Considering All Positive
(Forward Current)
In PS4 Mode
2.5μs
Shutdown
Delay
2.5μs PS4
Exit Delay
0V
tTPS = 50ns
GL
tTPS = 50ns
GL OFF
GH
GH OFF
Figure 3. FCCM Logic During High Impedance at PWM Input
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Page 6 of 14
AOZ5049QI
Typical Performance Characteristics
TA = 25°C, VIN = 19V, VCC = 5V, L = 220nH, unless otherwise specified.
Figure 4. 800kHz Efficiency vs. Load Current
Figure 5. 800kHz Power Loss vs. Load Current
89
7.0
6.5
6.0
5.5
5.0
Power Loss (W)
Efficiency (%)
88
87
86
4.5
4.0
3.5
3.0
2.5
2.0
85
1.5
Vin = 19V
Vout = 1V
1.0
0.5
84
5
10
15
20
25
30
35
5
10
15
Load Current (A)
20
25
30
35
Load Current (A)
Figure 6. PWM Threshold vs. Temperature
Figure 7. FCCM Input Threshold vs. Temperature
4.25
3.75
4.00
TS to High Threshold (Rising)
3.75
TS to PWM High
3.25
PWM High to TS
3.25
FCCM Threshold (V)
PWM Threshold (V)
3.50
3.00
2.75
2.50
2.25
2.00
1.75
PWM Low to TS
1.50
High Threshold to TS (Falling)
2.75
2.25
Low Threshold to TS (Rising)
1.75
TS to PWM Low
1.25
TS to Low Threshold (Falling)
1.00
1.25
0.75
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
Temperature (°C)
Figure 8. UVLO (VCC) Threshold vs. Temperature
60
80
100
120
140
Figure 9. Supply Current (IVCC) vs. Temperature
3.63
65
3.60
60
3.58
55
2MHz
Supply Current (mA)
UVLO Threshold (V)
40
Temperature (°C)
3.56
3.54
3.52
3.50
50
45
1.5MHz
40
35
30
1MHz
3.46
25
800kHz
3.44
20
3.42
15
3.48
600kHz
-40
-20
0
20
40
60
80
100
120
140
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Rev. 3.0 June 2016
-40
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Page 7 of 14
AOZ5049QI
Typical Performance Characteristics (Continued)
Figure 10. Hold Off Propagation Delay vs. Temperature
220
Tri-State Hold Off Delay (ns)
210
200
190
180
tTSSHD
170
PWM High to TS
160
150
140
tTSSHD
PWM Low to TS
130
120
110
100
-40
-20
0
20
40
60
80
100
120
140
160
Temperature (°C)
Application Information
AOZ5049QI is a fully integrated power module designed
to work over an input voltage range of 4.5V to 25V with a
separate 5V supply for gate drive and internal control
circuits. A number of features make AOZ5049QI a highly
versatile power module. The MOSFETs are individually
optimized on either HS or LS switches in a low duty cycle
synchronous buck converter. A high current driver is also
included in the package which minimizes the gate drive
loop and results in extremely fast switching. The modules
are fully compatible with Intel DrMOS specification
IMVP8 in form fit and function.
Powering the Module and the Gate Drives
An external supply VCC of 5V is required for driving the
MOSFETs. The MOSFETs are designed with low gate
thresholds so that lower drive voltage can be used to
reduce the switching and drive losses without
compromising the conduction losses. The integrated gate
driver is capable of supplying large peak current into the
LS MOSFET to achieve extremely fast switching. A
ceramic bypass capacitor of 1F or higher is
recommended from VCC to PGND. For effective filtering
it is strongly recommended to have a direct connection
from this capacitor to PGND (pin 21).
The boost supply for driving the HS MOSFET is
generated by connecting a small capacitor between
BOOT pin and the switching node VSWH. It is
recommended that this capacitor Cboot be connected as
close as possible to the device across pins 2 and 5.
Rev. 3.0 June 2016
Boost diode is integrated into the package. A resistor in
series with Cboot can be optionally used by designers to
slow down the turn on speed of the HS MOSFET.
Typically values between 1Ω to 5 Ω is a compromise
between the need to keep both the switching time and
VSWH node spikes as low as possible.
Undervoltage Lockout
In a UVLO event, both GH and GL outputs are actively
held low until adequate gate supply becomes available.
The under-voltage lockout is set at 3.4V with a 500mV
hysteresis. The AOZ5049QI must be powered up and
enabled before the PWM input is applied.
Since the PWM control signals are provided typically
from an external controller or a digital processor, extra
care must be taken during start up. It should be ensured
that PWM signal goes through a proper soft start
sequence to minimize inrush current in the converter
during start up. Powering the module with a full duty
cycle PWM signal may lead to a number of undesirable
consequences as explained below. In general it should
be noted that AOZ5049QI is a combination of two
MOSFETs with an IMVP8 compliant driver, all of which
are optimized for switching at the highest efficiency.
Other than UVLO and thermal protection, it does not
have any monitoring or protection functions built in. The
PWM controller should be designed in to perform these
functions under all possible operating and transient
conditions.
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AOZ5049QI
Input Voltage VIN
AOZ5049QI is rated to operate over a wide input range of
4.5V to 25V. As with any other synchronous buck
converter, large pulse currents at high frequency and
extremely high di/dt rates will be drawn by the module
during normal operation. It is strongly recommended to
bypass the input supply very closely to package leads
with X7R or X5R quality ceramic capacitors.
The HS MOSFET in AOZ5049QI is optimized for fast
switching with low duty ratios. It has ultra low gate
charges which have been achieved as a trade off with
higher RDS(ON) value. When the module is operated at
low VIN the duty ratio will be higher and conduction
losses in the HS MOSSFET will also be correspondingly
higher. This will be compensated to some extent by
reduced switching losses. The total power loss in the
module may appear to be low even though in reality the
HS MOSFET losses may be disproportionately high.
Since the two MOSFETs have their own exposed pads
and PCB copper areas for heat dissipation, the HS
MOSFET may be much hotter than the LS MOSFET. It is
recommended that worst case junction temperature be
measured and ensured to be within safe limits when the
module is operated with high duty ratios.
reference and generate both the high and low side
complementary gate drive outputs with the minimal antioverlap delays necessary to avoid cross conduction.
When the pin is taken low the HS MOSFET drive is not
affected but diode emulation mode is activated for the LS
MOSFET. See Table 2 for all possible logic inputs and
corresponding output drive conditions. A high impedance
state at the FCCM pin shuts down the AOZ5049QI. The
FCCM Threshold Table (Table 3) lists the thresholds for
high and low level transitions as well as tri-state threshold
window. The FCCM/PWM Timing Diagram in Figure 3
illustrates the sequential timing involved when the PWM
pin is left at a high impedance state by the master
controller. During a shutdown event (FCCM entering tristate), the PWM will be actively pulled low by an internal
sink circuit of the DrMOS. Nevertheless, the ultimate goal
is to ensure that the GH and GL are held at a low state.
Table 2. Control Logic Truth Table
FCCM
PWM
GH
GL
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
L
Tri-State
L
L
H
Tri-State
L
L
Tri-State
X
L
L
PWM Input
AOZ5049QI is offered to be interfaced with 5V (TTL)
PWM logic. Refer to Figure 1 for the timing and
propagation delays between the PWM input and the
MOSFET gate drives.
The PWM is also a tri-state compatible input. When the
input is high impedance or unconnected both the gate
drives will be off and the gates are held active low. The
PWM Threshold Table below, lists the thresholds for high
and low level transitions as well as tri-state operation
window. As shown in Figure 2, there is a hold off delay
between the corresponding PWM tri-state signal and the
output gate drive being pulled low. This delay is typically
175ns and intended to prevent spurious triggering
caused by tri-state mode entrance.
Table 1. PWM Input and Tri-State Thresholds
Thresholds
VPWMH
VPWML
VTRIH
VTRIL
AOZ5049QI
4.1 V
0.7 V
1.1 V
3.9 V
Note: See Figure 2 for propagation delays and tri-state window.
Diode Mode Emulation of Low Side MOSFET (FCCM)
AOZ5049QI can be operated in the diode emulation or
skip mode using the FCCM pin. This is useful if the
converter has to operate in asynchronous mode during
start up, light load or under pre bias conditions. If FCCM
is taken high, the controller will use the PWM signal as
Rev. 3.0 June 2016
Table 3. FCCM Input and Tri-State Thresholds
Thresholds
VPWMH
VPWML
VTRIH
VTRIL
AOZ5049QI
3.8 V
1.2 V
1.4 V
3.4 V
Note: Diode emulation mode is activated when FCCM pin is held low.
Gate Drives
AOZ5049QI has an internal high current high speed
driver that generates the floating gate drive for the HS
MOSFET and a complementary drive for the LS
MOSFET. Propagation delays between transitions of the
PWM waveform and corresponding gate drives are kept
to the minimum. An internal shoot through protection
scheme ensures that neither MOSFET turns on while the
other one is still conducting, thereby preventing shoot
through condition of the input current. When the PWM
signal makes a transition from H to L or L to H, the
corresponding gate drive GH or GL begins to turn off.
The adaptive timing circuit monitors the falling edge of
the gate voltage and when the level goes below 1V, the
complementary gate driver is turned on. The dead time
between the two switches is minimized, at the same time
preventing cross conduction across the input bus. The
adaptive circuit also monitors the switching node VSWH
and ensures that transition from one MOSFET to another
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AOZ5049QI
always takes place without cross conduction, even under
transient and abnormal conditions of operation.
The gate pins GH and GL are brought out on pins 4 and
19, respectively. However these connections are not
made directly to MOSFET gate pads and their voltage
measurement may not reflect the actual gate voltage
applied inside the package. The gate connections are
primarily for functional tests during manufacturing and no
connections should be made to them in the application.
PCB Layout Guidelines
AOZ5049QI is a high current module rated for operation
up to 2MHz. This requires extremely fast switching
speeds to keep the switching losses and device
temperatures within limits. Having a robust gate driver
integrated in the package eliminates driver-to-MOSFET
gate pad parasitics of the package or PCB.
While excellent switching speeds are achieved,
correspondingly high levels of dV/dt and di/dt will be
observed throughout the power train which requires
careful attention to PCB layout to minimize voltage
spikes and other transients. As with any synchronous
buck converter layout, the critical requirement is to
minimize the area of the primary switching current loop,
formed by the HS MOSFET, LS MOSFET and the input
bypass capacitor CIN. The PCB design is somewhat
simplified because of the optimized pin out in
AOZ5049QI. The bulk of VIN and PGND pins are located
adjacent to each other and the input bypass capacitors
should be placed as close as possible to these pins. The
area of the secondary switching loop, formed by LS
MOSFET, output inductor and output capacitor COUT is
the next critical parameter, this requires second layer or
“Inner 1” should always be an uninterrupted GND plane
with sufficient GND vias placed as close as possible to
by-pass capacitors GND pads.
As shown in Figure 11, the top most layer of the PCB
should comprise of uninterrupted copper flooding for the
primary AC current loop which runs along the VIN
copper plane originating from the bypass capacitors
C33, C34 and C35 which are mounted to a large PGND
copper plane, also on the top most layer of the PCB.
These copper planes also serve as heat dissipating
elements as heat simply flows down to the VIN exposed
pad and onto the top layer VIN copper plane which fans
out to a wider area moving away from the 3.5x5 QFN
package. Adding vias will only help transfer heat to
cooler regions of the PCB board through the other 3
layers (if 4 layer PCB is used) beneath but serve no
purpose to AC activity as all the AC current sees the
lowest impedance on the top layer only.
Due to the optimized bonding technique used on the
AOZ5049QI internal package, the VIN input capacitors
are optimally placed for AC current activities on both the
primary and complimentary current loops. The return
path of the current during the complimentary period
flows through a non interrupted PGND copper plane that
is symmetrically proportional to the VIN copper plane.
Due to the PGND exposed pad, heat is optimally
dissipated simply by flowing down through the vertically
structured lower MOSFET, through the exposed PGND
pad and down to the PCB top layer PGND copper plane
that also fans outward, moving away from the package.
As the primary and secondary (complimentary) AC
current loops move through VIN to VSWH and through
PGND to VSWH, large positive and negative voltage
spikes appear at the VSWH terminal which are caused
by the large internal di/dts produced through the in
package parastics. To minimize the effects of this
interference, the VSWH terminal at which the main
inductor L1 is mounted to, is sized just so the inductor
can physically fit. The goal is to employ the least amount
of copper area for this VSWH terminal just enough so
the inductor can be securely mounted.
To minimize the effects of switching noise coupling to
the rest of the sensitive areas of the PCB, the area
directly underneath the designated VSWH copper plane
on the top layer is voided and the shape of this void is
replicated descending down through the rest of the
layers as shown on Figure 12 which is the bottom layer
of the PCB as an example.
R5
VSWH
VIN
PGND
Figure 11. Top Layer of PCB Layout (VIN, VSWH and PGND
Copper Planes)
Rev. 3.0 June 2016
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Page 10 of 14
AOZ5049QI
Adding Vias Through Exposed Pads
Landing Pattern
The AOZ5049QI can be operated at a switching
frequency of up to 2MHz. This implies that the inherent
capacitive parameters of the HS and LS MOSFETs need
to be charged and discharge on each and every cycle.
Due to the back and forth conduction of these AC
currents flowing in and out of the input capacitors, the
exposed pads (VIN and PGND) would tend to heat up,
hence requiring thermal venting. Positioning vias through
the landing pattern of the VIN and PGND thermal pads
will help quickly facilitate the thermal build up and spread
the heat much more quickly towards the surrounding
copper layers descending from the top layer.
GL
PGND
VIN
NC
VCC
Figure 12. Bottom Layer PCB Layout (VSWH Copper Plane
Voided on Descending Layers)
The exposed pads dimensional footprint of the 3.5x5
QFN package is shown on Figure 13. For optimal thermal
relief, it is recommended to fill the PGND and VIN
exposed landing pattern with 10mil diameter vias. 10mil
via diameter is a commonly used as it is optimally cost
effective based on the tooling bit used in manufacturing.
Each via is associated with a 20mil diameter keep out.
Maintain a 5mil clearance (127µm) around the inside
edge of each exposed pad in an event of solder overflow,
potentially shorting with the adjacent expose thermal
pad.
GL
VSWH
PGND
1
Area Clearance from
Edge of Thermal Pads
PWM
FCCM
VSWH
2181µm
BOOT
3500µm
2960µm
508µm (20mil)
Diameter Kept
Out
GH
VIA
127µm (5mil)
Clearance from
exposed pad
edge
PGND
VIN
VIN
VIN
VSWH
1530µm
254µm (10mil)
Diameter Drill bit
for VIA hole
1874µm
5000µm
Figure 13. Exposed Pad Land Pattern and Recommended Via Placements
Rev. 3.0 June 2016
www.aosmd.com
Page 11 of 14
AOZ5049QI
Package Dimensions, QFN3.5x5_24L EP2_S
L4
L5
A
D
L2
D1
d
E1
f
E
e
E2
L
b
Pin #1 Dot
By Marking
C 0.25
L1
TOP VIEW
L3
SIDE VIEW
BOTTOM VIEW
A2
A1
SIDE VIEW
Ø0
.
Ø0 60
.35
1.850
1.325
0.725
0.331
0.177
0.078
1.225
RECOMMENDED LAND PATTERN
2.175
2.600
1.924
1.699
0.000
0.375
0.10
0.450
1.47
0.175
0.88
0.375
0.95
1.069
0.25
1.85
1.30
1.125
1.11
0.000
1.125
1.388
1.550
1.85
0.50
2.125
0.375
0.675
1.855
2.050
2.600
Dimensions in millimeters
Symbols
A
A1
A2
E
E1
E2
D1
D
L
L1
L2
L3
L4
L5
b
d
f
e
Min.
1.00
0.00
4.90
1.63
1.15
1.65
3.40
0.35
0.22
0.30
0.58
1.02
0.58
0.20
0.33
0.70
Typ.
1.10
0.2 REF
5.00
1.73
1.25
1.75
3.50
0.40
0.27
0.35
0.63
1.12
0.63
0.25
0.38
0.75
0.50 BSC
Max.
1.20
0.05
5.10
1.83
1.35
1.85
3.60
0.45
0.32
0.40
0.68
1.22
0.68
0.30
0.43
0.80
Dimensions in inches
Symbols
A
A1
A2
E
E1
E2
D1
D
L
L1
L2
L3
L4
L5
b
d
f
e
Min.
0.039
0.000
Typ.
0.043
0.008 REF
0.193 0.197
0.064 0.068
0.045 0.049
0.065 0.069
0.134 0.138
0.014 0.016
0.009 0.011
0.012 0.014
0.023 0.025
0.040 0.044
0.023 0.025
0.008 0.010
0.013 0.015
0.028 0.030
0.02 BSC
Max.
0.047
0.002
0.201
0.072
0.053
0.073
0.142
0.018
0.013
0.016
0.027
0.048
0.027
0.012
0.017
0.031
Unit: mm
Note:
Controlling dimension are in millimeters. Converted inch dimensions are not necessarily exact.
Rev. 3.0 June 2016
www.aosmd.com
Page 12 of 14
AOZ5049QI
Tape and Reel Dimensions, QFN3.5x5
Carrier Tape
P0
P2
D1
P1
A
R
T
0.
30
M
E1
AX
.
E2
D0
E
B0
A
A0
K0
Feeding Direction
UNIT: mm
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
QFN3.5x5
(12mm)
3.89
±0.10
5.31
±0.10
1.30
±0.10
1.50
MIN.
1.50
+0.1
-0.0
12.0
±0.30
1.75
±0.10
5.50
±0.05
8.00
±0.10
4.00
±0.10
2.00
±0.05
0.30
±0.05
Reel
W1
S
G
N
M
K
V
R
H
W
UNIT: mm
Tape Size
Reel Size
M
12mm
Ø330
Ø330
±2.00
N
W
W1
H
S
12.40
Ø101.6
12.40
Ø13.20 1.70-2.60
±2.00 +2.00/-0.00 +3.00/-0.20 ±0.30
K
G
R
V
---
---
---
---
Leader/Trailer and Orientation
Unit Per
Reel:
3000pcs
Trailer Tape
300mm min.
Rev. 3.0 June 2016
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min.
Page 13 of 14
AOZ5049QI
Part Marking
AOZ5049QI
(3.5mm x 5mm QFN)
Z5049QI
Part Number Code
FA YW LT
Assembly Lot Code
Fab Code & Assembly Location
Year Code & Week Code
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 3.0 June 2016
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
www.aosmd.com
Page 14 of 14