AOZ1092D EZBuck™ 3A Simple Buck Regulator General Description Features The AOZ1092D is a high efficiency, simple to use, 3A buck regulator. The AOZ1092D works from a 4.5V to 16V input voltage range, and provides up to 3A of continuous output current with an output voltage adjustable down to 0.8V. ● 4.5V to 16V operating input voltage range ● 50mΩ internal PFET switch for high efficiency: up to 95% Schottky diode is included Internal soft start Output voltage adjustable to 0.8V 3A continuous output current Fixed 500kHz PWM operation Cycle-by-cycle current limit Short-circuit protection Output over voltage protection Thermal shutdown Small size 4x5 DFN-8 packages The AOZ1092D comes in 4x5 DFN-8 packages and is rated over a -40°C to +85°C ambient temperature range. ● ● ● ● ● ● ● ● ● ● Applications ● Point of load DC/DC conversion ● PCIe graphics cards ● Set top boxes ● DVD drives and HDD ● LCD panels ● Cable modems ● Telecom/networking/datacom equipment Typical Application VIN C1 22µF Ceramic VIN EN L1 4.7µH U1 AOZ1092D COMP RC CC C5 AGND VOUT 3.3V LX R1 C2, C3 22µF Ceramic FB GND R2 Figure 1. 3.3V/3A Non-Synchronous Buck Regulator Rev. 1.3 February 2009 www.aosmd.com Page 1 of 16 AOZ1092D Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ1092DI -40°C to +85°C DFN-8 4x5 RoHS All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards. Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. Pin Configuration VIN 1 8 LX 7 LX 6 EN 5 COMP LX PGND 2 AGND 3 GND FB 4 4x5 DFN (Top View) Pin Description Pin Number Pin Name 1 VIN 2 PGND Power ground. Electrically needs to be connected to AGND. 3 AGND Reference connection for controller section. Also used as thermal connection for controller section. Electrically needs to be connected to PGND. 4 FB 5 COMP 6 EN The enable pin is active HIGH. Connect EN pin to VIN if not used. Do not leave the EN pin floating. 7, 8 LX PWM output connection to inductor. Thermal connection for output stage. Rev. 1.3 February 2009 Pin Function Supply voltage input. When VIN rises above the UVLO threshold the device starts up. The FB pin is used to determine the output voltage via a resistor divider between the output and GND. External loop compensation pin. www.aosmd.com Page 2 of 16 AOZ1092D Block Diagram VIN UVLO & POR EN Internal +5V 5V LDO Regulator OTP + ISen – Reference & Bias Softstart Q1 ILimit + + 0.8V EAmp FB – – PWM Comp PWM Control Logic + Level Shifter + FET Driver LX D1 COMP + 0.2V 0.96V Frequency Foldback Comparator 500kHz/63kHz Oscillator – + Over Voltage Protection Comparator – AGND PGND Absolute Maximum Ratings Recommend Operating Ratings Exceeding the Absolute Maximum Ratings may damage the device. The device is not guaranteed to operate beyond the Maximum Operating Ratings. Parameter Supply Voltage (VIN) Rating Parameter 18V Supply Voltage (VIN) LX to AGND -0.7V to VIN+0.3V Output Voltage Range EN to AGND -0.3V to VIN+0.3V Ambient Temperature (TA) FB to AGND -0.3V to 6V COMP to AGND -0.3V to 6V PGND to AGND -0.3V to 0.3V Junction Temperature (TJ) +150°C Storage Temperature (TS) -65°C to +150°C Rev. 1.3 February 2009 Package Thermal Resistance DFN 4x5 (ΘJA) www.aosmd.com Rating 4.5V to 16V 0.8V to VIN -40°C to +85°C 53°C/W Page 3 of 16 AOZ1092D Electrical Characteristics TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.(3) Symbol VIN VUVLO Parameter Conditions Supply Voltage Min. Typ. 4.5 Input Under-Voltage Lockout Threshold VIN Rising 4.00 VIN Falling 3.70 Max. Units 16 V V Supply Current (Quiescent) IOUT = 0, VFB = 1.2V, VEN > 1.2V 2 3 mA IOFF Shutdown Supply Current VEN = 0V 1 10 µA VFB Feedback Voltage 0.8 0.818 V IIN IFB 0.782 Load Regulation 0.5 % Line Regulation 0.5 % Feedback Voltage Input Current 200 nA ENABLE VEN EN Input Threshold Off Threshold On Threshold VHYS 0.6 2.0 EN Input Hysteresis 100 V mV MODULATOR Frequency 400 DMAX Maximum Duty Cycle 100 DMIN Minimum Duty Cycle GVEA Error Amplifier Voltage Gain 500 V/ V GEA Error Amplifier Transconductance 200 µA / V fO 500 600 kHz % 6 % PROTECTION ILIM Current Limit 4 VPR Output Over-Voltage Protection Threshold 5 Off Threshold 960 On Threshold 840 A mV TJ Over-Temperature Shutdown Limit 150 °C tSS Soft Start Interval 2.2 ms OUTPUT STAGE High-Side Switch On-Resistance VIN = 12V 40 50 VIN = 5V 65 85 mΩ Note: 3. Specifications in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design. Rev. 1.3 February 2009 www.aosmd.com Page 4 of 16 AOZ1092D Typical Performance Characteristics Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified. Light Load (DCM) Operation Full Load (CCM) Operation Vin ripple 50mV/div Vin ripple 0.1V/div Vo ripple 50mV/div Vo ripple 50mV/div IL 2A/div IL 2A/div VLX 10V/div VLX 10V/div 1μs/div 1μs/div Startup to Full Load Full Load to Turn Off Vin 5V/div Vin 5V/div Vo 2V/div Vo 1V/div lin 1A/div lin 1A/div 400μs/div 1ms/div 50% to 100% Load Transient No Load to Turn Off Vin 5V/div Vo Ripple 0.1V/div Vo 1V/div lo 2A/div 1s/div 100μs/div Rev. 1.3 February 2009 lin 1A/div www.aosmd.com Page 5 of 16 AOZ1092D Typical Performance Characteristics (Continued) Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified. Short Circuit Protection Short Circuit Recovery Vo 2V/div Vo 2V/div IL 2A/div IL 2A/div 100μs/div 1ms/div Efficiency Efficiency (VIN = 12V) vs. Load Current 100 8.0V OUTPUT Efficieny (%) 95 5.0V OUTPUT 90 3.3V OUTPUT 85 80 75 0 0.5 1.0 1.5 2.0 2.5 3.0 Load Current (A) Thermal Derating Curves Thermal derating curves for 4x5 DFN-8 package part under typical line and output voltage condition based on EVAL board. Circuit of Figure 1. 25°C ambient temperature and natural convection (air speed <50LFM) unless otherwise specified. Derating Curve at 5V/6V Input Derating Curve at 12 Input 3.5 3.5 5.0V OUTPUT 1.8V OUTPUT 2.5 8.0V OUTPUT 3.0 3.3V OUTPUT 2.0 1.5 Output Current (IO) Output Current (IO) 3.0 1.8V OUTPUT 2.5 3.3V OUTPUT 5.0V OUTPUT 2.0 1.5 1.0 1.0 25 35 Rev. 1.3 February 2009 45 55 65 75 Ambient Temperature (TA) 85 www.aosmd.com 25 35 45 55 65 75 Ambient Temperature (TA) 85 Page 6 of 16 AOZ1092D Detailed Description The AOZ1092D is a current-mode step down regulator with integrated high side PMOS switch and low side Schottky diode. It operates from a 4.5V to 16V input voltage range and supplies up to 3A of load current. The duty cycle can be adjusted from 6% to 100% allowing a wide range of output voltage. Features include enable control, Power-On Reset, input under voltage lockout, fixed internal soft-start and thermal shut down. seen in a circuit which is using an NMOS switch. It allows 100% turn-on of the upper switch to achieve linear regulation mode of operation. The minimum voltage drop from VIN to VO is the load current times DC resistance of MOSFET plus DC resistance of buck inductor. It can be calculated by equation below: The AOZ1092D is available in 4x5 DFN-8 package. where; V O_MAX = V IN – I O × ( R DS ( ON ) + R inductor ) VO_MAX is the maximum output voltage, Enable and Soft Start VIN is the input voltage from 4.5V to 16V, The AOZ1092D has internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. A soft start process begins when the input voltage rises to 4.0V and voltage on EN pin is HIGH. In soft start process, the output voltage is ramped to regulation voltage in typically 2.2ms. The 2.2ms soft start time is set internally. IO is the output current from 0A to 3A, The EN pin of the AOZ1092D is active high. Connect the EN pin to VIN if enable function is not used. Pull it to ground will disable the AOZ1092D. Do not leave it open. The voltage on EN pin must be above 2.0 V to enable the AOZ1092D. When voltage on EN pin falls below 0.6V, the AOZ1092D is disabled. The AOZ1092D switching frequency is fixed and set by an internal oscillator. The practical switching frequency could range from 400kHz to 600kHz due to device variation. Steady-State Operation Output voltage can be set by feeding back the output to the FB pin with a resistor divider network. In the application circuit shown in Figure 1. The resistor divider network includes R1 and R2. Usually, a design is started by picking a fixed R2 value and calculating the required R1 with equation below. Under steady-state conditions, the converter operates in fixed frequency and Continuous-Conduction Mode (CCM). The AOZ1092D integrates an internal P-MOSFET as the high-side switch. Inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power MOSFET. Output voltage is divided down by the external voltage divider at the FB pin. The difference of the FB pin voltage and reference is amplified by the internal transconductance error amplifier. The error voltage, which shows on the COMP pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at PWM comparator input. If the current signal is less than the error voltage, the internal high-side switch is on. The inductor current flows from the input through the inductor to the output. When the current signal exceeds the error voltage, the high-side switch is off. The inductor current is freewheeling through the internal Schottky diode to output. The AOZ1092D uses a P-Channel MOSFET as the high side switch. It saves the bootstrap capacitor normally Rev. 1.3 February 2009 RDS(ON) is the on resistance of internal MOSFET, the value is between 40mΩ and 70mΩ depending on input voltage and junction temperature, and Rinductor is the inductor DC resistance. Switching Frequency Output Voltage Programming R 1⎞ ⎛ V O = 0.8 × ⎜ 1 + -------⎟ R 2⎠ ⎝ Some standard value of R1, R2 and most commonly used output voltage values are listed in Table 1. VO (V) R1 (kΩ) R2 (kΩ) 0.8 1.2 1.5 1.8 2.5 3.3 5.0 1.0 4.99 10 12.7 21.5 31.1 52.3 open 10 11.5 10.2 10 10 10 The combination of R1 and R2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. www.aosmd.com Page 7 of 16 AOZ1092D Since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop on upper PMOS and inductor. Protection Features Thermal Protection An internal temperature sensor monitors the junction temperature. It shuts down the internal control circuit and high side PMOS if the junction temperature exceeds 150ºC. The AOZ1092D has multiple protection features to prevent system circuit damage under abnormal conditions. Application Information Over Current Protection (OCP) Input Capacitor The sensed inductor current signal is also used for over current protection. Since AOZ1092D employs peak current mode control, the COMP pin voltage is proportional to the peak inductor current. The COMP pin voltage is limited to be between 0.4V and 2.5V internally. The peak inductor current is automatically limited cycle by cycle. The input capacitor must be connected to the VIN pin and PGND pin of the AOZ1092D to maintain steady input voltage and filter out the pulsing input current. The voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. The basic AOZ1092D application circuit is shown in Figure 1. Component selection is explained below. The cycle by cycle current limit threshold is set between 4A and 5A. When the load current reaches the current limit threshold, the cycle by cycle current limit circuit turns off the high side switch immediately to terminate the current duty cycle. The inductor current stop rising. The cycle by cycle current limit protection directly limits inductor peak current. The average inductor current is also limited due to the limitation on peak inductor current. When cycle by cycle current limit circuit is triggered, the output voltage drops as the duty cycle decreasing. The AOZ1092D has internal short circuit protection to protect itself from catastrophic failure under output short circuit conditions. The FB pin voltage is proportional to the output voltage. Whenever FB pin voltage is below 0.2V, the short circuit protection circuit is triggered. As a result, the converter is shut down and hiccups at a frequency equals to 1/8 of normal switching frequency. The converter will start up via a soft start once the short circuit condition disappears. In short circuit protection mode, the inductor average current is greatly reduced because of the low hiccup frequency. Power-On Reset (POR) A power-on reset circuit monitors the input voltage. When the input voltage exceeds 4V, the converter starts operation. When input voltage falls below 3.7V, the converter will be shut down. Output Over Voltage Protection (OVP) The AOZ1092D monitors the feedback voltage: when the feedback voltage is higher than 960mV, it immediate turns-off the PMOS to protect the output voltage overshoot at fault condition. When feedback voltage is lower than 840mV, the PMOS is allowed to turn on in the next cycle. Rev. 1.3 February 2009 The input ripple voltage can be approximated by equation below: VO ⎞ VO IO ⎛ ΔV IN = ----------------- × ⎜ 1 – ---------⎟ × --------f × C IN ⎝ V IN⎠ V IN Since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. For a buck circuit, the RMS value of input capacitor current can be calculated by: VO ⎛ VO ⎞ - ⎜ 1 – --------⎟ I CIN_RMS = I O × -------V IN ⎝ V IN⎠ if let m equal the conversion ratio: VO -------- = m V IN The relationship between the input capacitor RMS current and voltage conversion ratio is calculated and shown in Figure 2 below. It can be seen that when VO is half of VIN, CIN is under the worst current stress. The worst current stress on CIN is 0.5 x IO. 0.5 0.4 ICIN_RMS(m) 0.3 IO 0.2 www.aosmd.com 0.1 0 0 0.5 m 1 Figure 2. ICIN vs. Voltage Conversion Ratio Page 8 of 16 AOZ1092D For reliable operation and best performance, the input capacitors must have current rating higher than ICIN_RMS at worst operating conditions. Ceramic capacitors are preferred for input capacitors because of their low ESR and high ripple current rating. Depending on the application circuits, other low ESR tantalum capacitor or aluminum electrolytic capacitor may also be used. When selecting ceramic capacitors, X5R or X7R type dielectric ceramic capacitors are preferred for their better temperature and voltage characteristics. Note that the ripple current rating from capacitor manufactures are based on certain amount of life time. Further de-rating may be necessary for practical design requirement. Inductor Table 2. VOUT 5.0V Manufacturer Shielded, 6.8µH MSS1278-682MLD Coilcraft Shielded, 6.8µH MSS1260-682MLD 3.3V Un-shielded, 4.7µH DO3316P-472MLD Coilcraft Shielded, 4.7µH DO1260-472NXD 1.8V The inductor is used to supply constant current to output when it is driven by a switching voltage. For given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: VO ⎛ VO ⎞ -⎟ ΔI L = ----------- × ⎜ 1 – -------f×L ⎝ V IN⎠ L1 Shielded, 3.3µH ET553-3R3 ELYTONE Shielded, 2.2µH ET553-2R2 ELYTONE Un-shielded, 3.3µH DO3316P-222MLD Coilcraft Shielded, 2.2µH MSS1260-222NXD Output Capacitor The output capacitor is selected based on the DC output voltage rating, output ripple voltage specification and ripple current rating. The peak inductor current is: ΔI L I Lpeak = I O + -------2 High inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. Low ripple current reduces inductor core losses. It also reduces RMS current through inductor and switches, which results in less conduction loss. When selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. The inductor takes the highest current in a buck circuit. The conduction loss on inductor needs to be checked for thermal and efficiency requirements. Surface mount inductors in different shape and styles are available from Coilcraft, Elytone and Murata. Shielded inductors are small and radiate less EMI noise. But they cost more than unshielded inductors. The choice depends on EMI requirement, price and size. Table 2 lists some inductors for typical output voltage design. The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. De-rating needs to be considered for long term reliability. Output ripple voltage specification is another important factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It can be calculated by the equation below: 1 ΔV O = ΔI L × ⎛ ESR CO + -------------------------⎞ ⎝ 8×f×C ⎠ O where, CO is output capacitor value, and ESRCO is the equivalent series resistance of the output capacitor. When low ESR ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simplified to: 1 ΔV O = ΔI L × ⎛ -------------------------⎞ ⎝8 × f × C ⎠ O Rev. 1.3 February 2009 www.aosmd.com Page 9 of 16 AOZ1092D If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to: ΔV O = ΔI L × ESR CO For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum capacitor or aluminum electrolytic capacitor may also be used as output capacitors. In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calculated by: ΔI L I CO_RMS = ---------12 The compensation design is actually to shape the converter close loop transfer function to get desired gain and phase. Several different types of compensation network can be used for the AOZ1092D. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. In the AOZ1092D, FB pin and COMP pin are the inverting input and the output of internal transconductance error amplifier. A series R and C compensation network connected to COMP provides one pole and one zero. The pole is: G EA f p2 = ------------------------------------------2π × C C × G VEA where; GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. Loop Compensation The AOZ1092D employs peak current mode control for easy use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It greatly simplifies the compensation loop design. With peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. The pole is dominant pole and can be calculated by: 1 f p1 = ----------------------------------2π × C O × R L The zero is a ESR zero due to output capacitor and its ESR. It is can be calculated by: 1 f Z1 = -----------------------------------------------2π × C O × ESR CO GVEA is the error amplifier voltage gain, which is 500 V/V, and CC is cthe compensation capacitor. The zero given by the external compensation network, capacitor CC and resistor RC, is located at: 1 f Z2 = ----------------------------------2π × C C × R C To design the compensation circuit, a target crossover frequency fC for close loop must be selected. The system crossover frequency is where control loop has unity gain. The crossover frequency is also called the converter bandwidth. Generally a higher bandwidth means faster response to load transient. However, the bandwidth should not be too high because of system stability concern. When designing the compensation loop, converter stability under all line and load condition must be considered. Usually, it is recommended to set the bandwidth to be less than 1/10 of switching frequency. The AOZ1092D operates at a fixed switching frequency range from 400kHz to 600kHz. It is recommended to choose a crossover frequency less than 50kHz. f C = 50kHz where; CO is the output filter capacitor, RL is load resistor value, and ESRCO is the equivalent series resistance of output capacitor. The strategy for choosing RC and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC, to calculate RC: VO 2π × C O R C = f C × ---------- × -----------------------------V G ×G FB Rev. 1.3 February 2009 www.aosmd.com EA CS Page 10 of 16 AOZ1092D The actual junction temperature can be calculated with power dissipation in the AOZ1092D and thermal impedance from junction to ambient. where; where fC is desired crossover frequency, VFB is 0.8V, GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, and GCS is the current sense circuit transconductance, which is 6.86 A/V The compensation capacitor CC and resistor RC together make a zero. This zero is put somewhere close to the dominate pole fp1 but lower than 1/5 of selected crossover frequency. CC can is selected by: 1.5 C C = ----------------------------------2π × R C × f p1 T junction = ( P total_loss – P inductor_loss ) × Θ JA + T amb The maximum junction temperature of AOZ1092D is 150ºC, which limits the maximum load current capability. Please see the thermal de-rating curves for maximum load current of the AOZ1092D under different ambient temperature. The thermal performance of the AOZ1092D is strongly affected by the PCB layout. Extra care should be taken by users during design process to ensure that the IC will operate under the recommended environmental conditions. The above equation can be simplified to: CO × RL C C = --------------------R3 An easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com. Thermal Management and Layout Consideration In the AOZ1092D buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the VIN pin, to the LX pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. Current flows in the first loop when the high side switch is on. The second loop starts from inductor, to the output capacitors and load, to the anode of Schottky diode, to the cathode of Schottky diode. Current flows in the second loop when the low side diode is on. In PCB layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. A ground plane is strongly recommended to connect input capacitor, output capacitor, and PGND pin of the AOZ1092D. In the AOZ1092D buck regulator circuit, the major power dissipating components are the AOZ1092D and output inductor. The total power dissipation of converter circuit can be measured by input power minus output power. Several layout tips are listed below for the best electric and thermal performance. Figure 3 on the next page illustrates a PCB layout example as reference. 1. Do not use thermal relief connection to the VIN and the PGND pin. Pour a maximized copper area to the PGND pin and the VIN pin to help thermal dissipation. 2. Input capacitor should be connected to the VIN pin and the PGND pin as close as possible. 3. A ground plane is preferred. If a ground plane is not used, separate PGND from AGND and connect them only at one point to avoid the PGND pin noise coupling to the AGND pin. 4. Make the current trace from LX pins to L to Co to the PGND as short as possible. 5. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. 6. The two LX pins are connected to internal PFET drain. They are low resistance thermal conduction path and most noisy switching node. Connected a copper plane to LX pin to help thermal dissipation. This copper plane should not be too larger otherwise switching noise may be coupled to other part of circuit. 7. Keep sensitive signal trace far away form the LX pins. P total_loss = V IN × I IN – V O × I O The power dissipation of inductor can be approximately calculated by output current and DCR of the inductor. P inductor_loss = IO2 × R inductor × 1.1 Rev. 1.3 February 2009 www.aosmd.com Page 11 of 16 AOZ1092D Thermal PAD: LX Vin Vo L Cin Vin LX PG LX Cout AG EN FB CP GND Thermal PAD: AGND Via to ground plane Figure 3. AOZ1092D PCB Layout Rev. 1.3 February 2009 www.aosmd.com Page 12 of 16 AOZ1092D Package Dimensions, DFN 4x5 D A Pin #1 IDA D/2 B e 1 L E/2 R aaa C E E3 E2 Index Area (D/2 x E/2) D2 aaa C ccc C A3 D3 L1 Seating C Plane A ddd C A1 b bbb CAB Dimensions in millimeters Recommended Land Pattern 2.125 1.775 0.6 2.7 0.8 2.2 0.5 0.95 Unit: mm Symbols A Min. 0.80 A1 A3 0.00 b D Nom. 0.90 Dimensions in inches Symbols A Min. 0.031 0.02 0.05 0.20 REF A1 A3 0.000 0.001 0.002 0.008 REF 0.35 0.40 0.45 5.00 BSC b D 0.014 0.016 0.018 0.197 BSC D2 D3 E 1.975 1.625 2.125 2.225 1.775 1.875 4.00 BSC D2 D3 E 0.078 0.064 0.084 0.088 0.070 0.074 0.157 BSC E2 E3 2.500 2.050 2.750 2.300 E2 E3 0.098 0.081 e L L1 R 0.600 0.400 0.95 BSC 0.700 0.800 0.500 0.600 0.30 REF e L L1 R 0.024 0.016 aaa bbb ccc ddd – – – – aaa bbb ccc ddd – – – – 2.650 2.200 0.15 0.10 0.10 0.08 Max. 1.00 – – – – Nom. 0.035 0.104 0.087 Max. 0.039 0.108 0.091 0.037 BSC 0.028 0.031 0.020 0.024 0.012 REF 0.006 0.004 0.004 0.003 – – – – Notes: 1. Dimensions and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. 3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002. 4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5. Coplanarity applies to the terminals and all other bottom surface metallization. 6. Drawing shown are for illustration only. Rev. 1.3 February 2009 www.aosmd.com Page 13 of 16 AOZ1092D Tape Dimensions, DFN 4x5 Tape R0 20 0. .40 T D1 E1 E2 D0 E B0 Feeding Direction K0 P0 A0 Unit: mm Package A0 B0 K0 D0 D1 E E1 E2 P0 P1 P2 T DFN 5x4 (12 mm) 5.30 ±0.10 4.30 ±0.10 1.20 ±0.10 1.50 Min. Typ. 1.50 +0.10 / –0 12.00 ±0.30 1.75 ±0.10 5.50 ±0.10 8.00 ±0.10 4.00 ±0.20 2.00 ±0.10 0.30 ±0.05 Leader/Trailer and Orientation Trailer Tape (300mm Min.) Rev. 1.3 February 2009 Components Tape Orientation in Pocket www.aosmd.com Leader Tape (500mm Min.) Page 14 of 16 AOZ1092D II R1 59 Reel Dimensions, DFN 4x5 I R1 6.0±1 21 M R1 I 27 Zoom In R6 R1 P R5 5 B W1 III Zoom In 3-1.8 0.05 II /4 ø1 .0 A A N=ø100±2 3- .9 ±0 " A ø2 3-ø1 3- /8" Zoom In ø9 6± 0.2 5 1.8 6.0 1.8 6.45±0.05 8.00 6.2 ø2 2.20 1. 8.9±0.1 14 REF 0.00 0 5.0 ø13.0 R1.10 R3.10 C 1.8 12 REF 11.90 ø86 .0±0 10° 41.5 REF 43.00 44.5±0.1 44.5±0.1 .95 R3 4.0 6.10 VIEW: C 3- 8.0±0.1 ø3 " 16 ø3 / 3- 38° 40° 10.0 EF 8R 46.0±0.1 R0.5 .1 3.3 6.50 R4 R1 2.00 ø9 20 ø17.0 A 0.00 -0.05 /1 2.00 6.50 0.80 3.00 2.5 1.80 +0.05 6" 8.000.00 10.71 6° Rev. 1.3 February 2009 www.aosmd.com Page 15 of 16 AOZ1092D Package Marking Z1092DI FAYWLT Part Number Code Assembly Lot Code Fab & Assembly Location Year & Week Code This data sheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.3 February 2009 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 16 of 16