Datasheet

AOZ8304
Low Capacitance 3.3V TVS Diode Array
General Description
Features
The AOZ8304 is a transient voltage suppressor array
designed to protect high speed data lines from ESD and
lightning.
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ESD protection for high-speed data lines:
– IEC 61000-4-2, level 4 (ESD) immunity test
– ±24kV (air discharge) and ±24kV (contact discharge)
– IEC 61000-4-4 (EFT) 40A (5/50ns)
– IEC 61000-4-5 (Lightning) 25A
– Human Body Model (HBM) ±30kV
This device incorporates eight surge rated, low capacitance steering diodes and a TVS in a single package.
During transient conditions, the steering diodes direct
the transient to either the positive side of the power
supply line or to ground. They may be used to meet the
ESD immunity requirements of IEC 61000-4-2, Level 4
and IEC 61000-4-5. The TVS diodes provide effective
suppression of ESD voltages: ±24kV (air discharge) and
±24kV (contact discharge).
The AOZ8304 comes in a Halogen Free and RoHS
compliant DFN-10 2.6mm x 2.6mm package and is rated
over a -40°C to +85°C ambient temperature range. The
AOZ8304 is compatible with both lead free and SnPb
assembly techniques. The small size, low capacitance
and high ESD protection makes it ideal for protecting
high speed video and data communication interfaces.
●
Small package saves board space
●
Low insertion loss
●
Protects four I/O lines
●
Low clamping voltage
●
Low operating voltage: 3.3V
●
Green product
●
Pb-free device
Applications
●
10/100/1000 Ethernet
●
USB 2.0 power and data line protection
●
Video graphics cards
●
Monitors and flat panel displays
●
Digital Video Interface (DVI)
●
T1/E1 telecom ports
Typical Application
AOZ8304
TRD0+
TRD0-
TRD1+
TRD1-
Gigabit
Ethernet
Controller TRD2+
AOZ8304
RJ45
Connector
TRD2-
TRD3+
TRD3VCC
75Ω
75Ω
75Ω
75Ω
Figure 1. 10/100/1000 Ethernet Port Connection
Rev. 2.0 November 2010
www.aosmd.com
Page 1 of 8
AOZ8304
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ8304DIL
-40°C to +85°C
2.6mm x 2.6mm DFN-10
RoHS Compliant
Green Product
AOS Green Products (with “L” suffix) use reduced levels of Halogens, and are also RoHS compliant.
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Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
CH1
1
10
NC
NC
2
9
CH2
CH3
3
8
NC
NC
4
7
CH4
VP
5
6
NC
Pin Number
GND
Description
1, 3, 7, 9
Input/Output lines
2, 4, 6, 8, 10
No connection
5
VP
Center Tab
Ground
DFN-10
(Top View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
Rating
VP – GND
3.3V
Peak Pulse Current (IPP), tP = 8/20µs
25A
Peak Power Dissipation (8 x 20µ[email protected] 25°C)
350W
Storage Temperature (TS)
-65°C to +150°C
ESD Rating per IEC61000-4-2,
Contact(1)
ESD Rating per IEC61000-4-2, Air
ESD Rating per Human Body
±24kV
(1)
±24kV
Model(2)
±30kV
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330¾.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5k¾.
Maximum Operating Ratings
Parameter
Rating
Junction Temperature (TJ)
Rev. 2.0 November 2010
-40°C to +85°C
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Page 2 of 8
AOZ8304
Electrical Characteristics
TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C.
Parameter
Conditions
Reverse Working Voltage
Between pin 5 and GND(4)
IR
Reverse Leakage Current
VRWM = 3.3V, between pins 5 and GND
VBR
Reverse Breakdown Voltage
VBR = 1mA
VCL
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 5A, tp = 100ns, any I/O pin to
Ground(3)(6)(8)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 10A, tp = 100ns, any I/O pin to
Ground(3)(6)(8)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 25A, tp = 100ns, any I/O pin to
Ground(3)(6)(8)
Junction Capacitance
VR = 0V, f = 1MHz, any I/O pin to Ground(3)(7)
VR = 0V, f = 1MHz, between I/O pins(3)(7)
Typ.
3.5
Max.
Units
3.3
V
5
µA
5.6
V
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VRWM
Min.
.
Symbol
Cj
7.00
-4.00
V
V
9.00
-5.00
V
V
14.00
-8.00
V
V
5
pF
pF
1.25
Notes:
3. These specifications are guaranteed by design.
4. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
5. VBR is measured at the pulse test current IT.
6. Measurements performed with no external capacitor on VP (pin 5 floating).
7. Measurements performed with VP biased to 3.3 Volts.
8. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.
Rev. 2.0 November 2010
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Page 3 of 8
AOZ8304
Typical Performance Characteristics
Typical Variation of CIN vs. VR
Clamping Voltage vs. Peak Pulse Current
(f = 1MHz, T = 25°C)
(tperiod = 100ns, tr = 1ns)
14
Input Capacitance (pF)
1.2
1.0
10
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0.8
12
.
Clamping Voltage, VCL (V)
1.4
0.6
0.4
0.2
8
0
6
0
1.0
2.0
3.0
3.3
5
10
Forward Voltage vs. Forward Current
25
I/O – Gnd Insertion Loss (S21) vs. Frequency
(tperiod = 100ns, tr = 1ns)
(Vp = 3.3V)
5
0
8
-5
7
S21 (dB)
Forward Voltage (V)
20
Peak Pulse Current, IPP (A)
Input Voltage (V)
9
15
6
5
-10
-15
-20
4
-25
-30
3
5
10
15
20
1
25
10
Forward Current (A)
100
1,000
10,000
Frequency (MHz)
Analog Crosstalk (I/O–I/O) vs. Frequency
0
-10
S41 (dB)
20
-30
-40
-50
-60
-70
-80
1
10
100
1,000
10,000
Frequency (MHz)
Rev. 2.0 November 2010
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Page 4 of 8
AOZ8304
The AOZ8304 TVS is design to protect four data lines
from fast damaging transient over-voltage by clamping it
to a reference. When the transient on a protected data
line exceed the reference voltage the steering diode is
forward bias thus, conducting the harmful ESD transient
away from the sensitive circuitry under protection.
PCB Layout Guidelines
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Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8304 devices should be located as close as possible
to the noise source. The placement of the AOZ8304
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines
that enter the PCB through the I/O connector. Placing
the AOZ8304 devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8304 device. Long signal traces
will act as antennas to receive energy from fields that are
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize
interconnecting line lengths by placing devices with the
most interconnect as close together as possible. The
protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
clamping voltage. The inductance of the PCB can be
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design. The AOZ8304 low
capacitance TVS is designed to protect four high speed
data transmission lines from transient over-voltages by
clamping them to a fixed reference. The low inductance
and construction minimizes voltage overshoot during
high current surges. When the voltage on the protected
line exceeds the reference voltage the internal steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
.
Application Information
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the I/O terminals or connectors
to restrict transient coupling.
2. Fill unused portions of the PCB with ground plane.
3. Minimize the path length between the TVS and the
protected line.
4. Minimize all conductive loops including power and
ground loops.
5. The ESD transient return path to ground should be
kept as short as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4mm.
10. Keep the chassis ground trace length-to-width ratio
<5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
TPBIASx
1μF
56Ω
56Ω
IEEE 1394
Connector
TPAx+
IEEE 1394
TPAxPHY
TPBx+
TPBxGND
56Ω
5.1kΩ
56Ω
270p
AOZ8304
IEEE1394 Port Connection
Rev. 2.0 November 2010
www.aosmd.com
Page 5 of 8
AOZ8304
Package Dimensions, DFN 2.6mm x 2.6mm
D1
D
e
b
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10
E
E1
L
1
Pin #1 ID
Camfer 0.300 x 45
TOP VIEW
e1
Pin 1 ID
BOTTOM VIEW
Dimensions in millimeters
Symbols
A
A1
b
c
D
D1
E
E1
e
e1
L
A
A1
SIDE VIEW
c
Min.
Nom.
0.50
0.55
0.00
0.02
0.22
0.25
0.152 REF
2.55
2.60
2.10
2.150
2.55
2.60
1.25
1.26
0.50 BSC
2.00 REF
0.30
0.35
Max.
0.60
0.05
0.28
2.65
2.20
2.65
1.27
0.40
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters.
Rev. 2.0 November 2010
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Page 6 of 8
AOZ8304
Tape and Reel Dimensions, DFN 2.6mm x 2.6mm
Carrier Tape
P1
D0
P2
D1
K0
E1
E2
R0.3
Max.
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E
B0
A0
T
P0
R0.3 Typ.
Feeding Direction
UNIT: mm
Reel
Package
T
B0
A0
K0
D0
D1
E
E1
E2
P0
P1
P2
DFN
2.6x2.6
0.30
±0.05
2.80
±0.10
2.80
±0.10
1.10
±0.10
ø1.50
+0.1/-0.0
ø1.50
Min.
12.0
±0.3
1.75
±0.10
5.50
±0.05
4.00
±0.10
4.00
±0.10
2.00
±0.05
B
W1
S
60°
120°
K
N
M
H
Arbor Hole Detail A
Scale 2:1
2.24
B
W
2.84
Back View
Section B-B
Front View
UNIT: mm
Tape Size
12mm
Reel Size
ø180
M
ø179
±1.0
N
60
±0.5
W
13
±0.5
W1
17.0
H
ø13.0
±0.2
K
10.5
±0.25
S
2.0
±0.2
Leader / Trailer
& Orientation
Trailer Tape
300mm Min.
Rev. 2.0 November 2010
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm Min.
Page 7 of 8
AOZ8304
Part Marking
Assembly Location Code
PNOA
Part Number Code
Underscore Denotes Green Product
Option Code
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YWLT
Year & Week Code
Assembly Lot Code
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 2.0 November 2010
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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