AOZ8102 Ultra-Low Capacitance TVS Diode Array General Description Features The AOZ8102 is a transient voltage suppressor array designed to protect high speed data lines from ESD and lightning. z ESD protection for high-speed data lines: This device incorporates eight surge rated, low capacitance steering diodes and a TVS in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (±15kV air, ±8kV contact discharge). The TVS diodes provide effective suppression of ESD voltages: ±20kV (air discharge) and ±20kV (contact discharge). The AOZ8102 comes in a RoHS compliant DFN-6 1.6mm x 1.6mm package and is rated over a -40°C to +85°C ambient temperature range. The AOZ8102 is compatible with both lead free and SnPb assembly techniques. The small size, low capacitance and high ESD protection makes it ideal for protecting high speed video and data communication interfaces. z z z z z z z z – IEC 61000-4-2, level 4 (ESD) immunity test – ±20kV (air discharge) and ±20kV (contact discharge) – IEC 61000-4-5 (Lightning) 3A (8/20µs) – Human Body Model (HBM) ±20kV Small package saves board space Low insertion loss Protects four I/O lines Low capacitance from I/O to GND: 1.0pF Low clamping voltage Low operating voltage: 5.0V Pb-free device Halogen free Applications z USB 2.0 power and data line protection z Video graphics cards z Monitors and flat panel displays z Digital Video Interface (DVI) z 10/100/1000 Ethernet z Notebook computers Typical Application USB Host Controller +5V Downstream Ports VBUS RT D+ RT DVBUS GND AOZ8102 +5V VBUS RT D+ RT DGND Figure 1. 2 USB High Speed Ports Rev. 1.4 August 2011 www.aosmd.com Page 1 of 9 AOZ8102 Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ8102DI -40°C to +85°C 1.6mm x 1.6mm DFN-6 RoHS Compliant Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. Pin Configuration CH1 1 6 CH4 NC 2 5 VP CH2 3 4 CH3 DFN-6 = GND PAD (Top View) Absolute Maximum Ratings Exceeding the Absolute Maximum ratings may damage the device. Parameter Rating VP – VN 6V Peak Pulse Current, tP = 8/20µs 3A Storage Temperature (TS) -65°C to +150°C ESD Rating per IEC61000-4-2, Contact ESD Rating per IEC61000-4-2, Air ESD Rating per Human Body (1) ±20kV (1) ±20kV Model(2) ±20kV Notes: 1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330Ω. 2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5kΩ. Maximum Operating Ratings Parameter Rating Junction Temperature (TJ) Rev. 1.4 August 2011 -40°C to +85°C www.aosmd.com Page 2 of 9 AOZ8102 Electrical Characteristics TA = 25°C unless otherwise specified. Symbol Parameter IPP Reverse Peak Pulse Current VCL Clamping Voltage @ IPP VRWM IR VBR I IF Working Peak Reverse Voltage Maximum Reverse Leakage Current Breakdown Voltage IF Forward Current VF Forward Voltage PPK Peak Power Dissipation CJ Diagram VCL VBR VRWM V IR VF IT IPP Capacitance @ VR = 0 and f = 1MHz Specifications in BOLD indicate a temperature range of -40°C to +85°C. Symbol VRWM VBR Parameter Reverse Working Voltage Conditions Min. Between pin 5 and 2(4) 2(5) Reverse Breakdown Voltage IT = 1mA, between pins 5 and IR Reverse Leakage Current VRWM = 5V, between pins 5 and 2 VF Diode Forward Voltage IF = 15mA VCL Channel Clamp Voltage Positive Transients Negative Transient IPP = 1A, tp = 100ns, any I/O pin to Ground(3)(6)(8) Channel Clamp Voltage Positive Transients Negative Transient IPP = 5A, tp = 100ns, any I/O pin to Ground(3)(6)(8) Channel Clamp Voltage Positive Transients Negative Transient IPP = 12A, tp = 100ns, any I/O pin to Ground(3)(6)(8) Junction Capacitance VR = 0V, f = 1MHz, between I/O pins(3)(7) Cj VR = 0V, f = 1MHz, any I/O pin to ΔCj Channel Input Capacitance Matching Typ. Max. Units 5.5 V 6.6 0.70 Ground(3)(7) (3)(6) VR = 0V, f = 1MHz, between I/O pins V 1.0 µA 1 V 11.00 -2.50 V V 14.00 -3.50 V V 18.00 -5.00 V V 0.1 0.12 pF 1.0 1.17 pF 0.03 pF 0.85 Notes: 3. These specifications are guaranteed by design. 4. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level. 5. VBR is measured at the pulse test current IT. 6. Measurements performed with no external capacitor on VP (pin 5 floating). 7. Measurements performed with VP biased to 3.3 Volts (pin 5 @ 3.3V). 8. Measurements performed using a 100ns Transmission Line Pulse (TLP) system. Rev. 1.4 August 2011 www.aosmd.com Page 3 of 9 AOZ8102 Typical Performance Characteristics Typical Variation of CIN vs. VR (tperiod = 100ns, tr = 1ns) 20 Clamping Voltage, VCL (V) 1.2 Normalized Input Capacitance Clamping Voltage vs. Peak Pulse Current (VP = 3.3V, f = 1MHz, T = 25°C) 1.0 0.8 0.6 0.4 0.2 18 16 14 12 10 8 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 4.0 Input Voltage (V) Forward Voltage vs. Forward Current 4 6 8 Peak Pulse Current, IPP (A) Insertion Loss (dB) 4 2 0 2 4 6 8 Forward Current (A) 10 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 12 1 10 100 1000 10000 Frequency (MHz) Crosstalk (I/O-I/O) vs. Frequency ESD Response (8kV Contact per IEC61000-4-2) Vertical: 20V/div, Horizontal: 10ns/div) (Vpp = 3.3V) 0 12 (Vp = 3.3V) 6 0 10 I/O – Gnd Insertion Loss (S21) vs. Frequency (tperiod = 100ns, tr = 1ns) 8 Forward Voltage (V) 2 Insertion Loss (dB) -20 -40 -60 -80 -100 -120 1 10 100 1000 10000 Frequency (MHz) Rev. 1.4 August 2011 www.aosmd.com Page 4 of 9 AOZ8102 Application Information The AOZ8102 TVS is design to protect four data lines from fast damaging transient over-voltage by clamping it to a reference. When the transient on a protected data line exceed the reference voltage the steering diode is forward bias thus, conducting the harmful ESD transient away from the sensitive circuitry under protection. PCB Layout Guidelines Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. The location of the protection devices on the PCB is the simplest and most important design rule to follow. The AOZ8102 devices should be located as close as possible to the noise source. The placement of the AOZ8102 devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8102 devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8102 device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC’s signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS’s clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers Rev. 1.4 August 2011 with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The AOZ8102 ultra-low capacitance TVS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: 1. Place the TVS near the IO terminals or connectors to restrict transient coupling. 2. Fill unused portions of the PCB with ground plane. 3. Minimize the path length between the TVS and the protected line. 4. Minimize all conductive loops including power and ground loops. 5. The ESD transient return path to ground should be kept as short as possible. 6. Never run critical signals near board edges. 7. Use ground planes whenever possible. 8. Avoid running critical signal traces (clocks, resets, etc.) near PCB edges. 9. Separate chassis ground traces from components and signal traces by at least 4mm. 10. Keep the chassis ground trace length-to-width ratio <5:1 to minimize inductance. 11. Protect all external connections with TVS diodes. www.aosmd.com Page 5 of 9 AOZ8102 VCC Reset Clock I/O GND SIM AOZ8102 SIM Card Port Connection TPBIASx 1μ 56Ω 56Ω IEEE 1394 Connector TPAx+ IEEE 1394 PHY TPAxTPBx+ TPBx56Ω 56Ω GND 5.1kΩ 270p AOZ8102 IEEE1394 Port Connection AOZ8102 TRD0+ TRD0- Ethernet Controller TRD1+ RJ45 Connector TRD1TRD2+ TRD2TRD3+ TRD3- AOZ8102 10/100 Ethernet Port Connection Rev. 1.4 August 2011 www.aosmd.com Page 6 of 9 AOZ8102 Package Dimensions, DFN 1.6mm x 1.6mm, 6L D b e D1 E1 E L R, Pin #1 ID 1 1 Pin #1 Dot by Marking 2e Ref. TOP VIEW BOTTOM VIEW Dimensions in millimeters A A1 c SIDE VIEW RECOMMENDED LAND PATTERN 0.50 0.25 Symbols A A1 b c D D1 E E1 e L R Min. 0.50 0.00 0.22 Nom. Max. 0.55 0.60 — 0.05 0.25 0.28 0.152 REF. 1.55 1.60 1.65 0.95 1.00 1.05 1.55 1.60 1.65 0.55 0.060 0.65 0.50 BSC 0.225 0.275 0.325 — 0.20 — Dimensions in inches Symbols A A1 b c D D1 E E1 e L R Min. Nom. Max. 0.020 0.022 0.024 0.000 — 0.002 0.009 0.010 0.011 0.006 REF. 0.061 0.063 0.065 0.037 0.039 0.041 0.061 0.063 0.065 0.022 0.024 0.026 0.020 BSC 0.009 0.011 0.013 — 0.008 — 1.35 1.00 0.60 0.30 Note: 1. Controlling dimension is millimeter. Coverted inch dimensions are not necessarily exact Rev. 1.4 August 2011 www.aosmd.com Page 7 of 9 AOZ8102 Tape and Reel Dimensions, DFN 1.6mm x 1.6mm, 6L P2 Carrier Tape P1 D0 D1 E1 K0 E2 E B0 Ref. 3° A0 P0 T Feeding Direction UNIT: mm Package DFN 1.6x1.6 A0 1.80 ±0.05 B0 1.80 ±0.05 K0 0.69 ±0.05 D0 1.55 ±0.05 D1 E 0.080 8.00 ±0.05 ±0.10 E1 1.75 ±0.10 E2 3.50 ±0.05 P0 4.00 ±0.10 P1 P2 2.00 ±0.10 4.00 ±0.10 T 0.20 ±0.05 Reel W1 S K N M H UNIT: mm Tape Size Reel Size 8mm ø149 M N W1 H S K R ø179.0 ±0.50 55.0 ±0.50 8.4 +1.5/-0.0 13.0 +0.50/-0.0 1.5 Min. 10.1 Min. 2.7 ±0.20 Leader / Trailer & Orientation Trailer Tape 300mm Min. Rev. 1.4 August 2011 Components Tape Orientation in Pocket www.aosmd.com Leader Tape 500mm Min. Page 8 of 9 AOZ8102 Part Marking AOZ8102DI (1.6 x 1.6 DFN) BWL Product Number Code Assembly Lot Code Week Code Alpha & Omega Semiconductor reserves the right to make changes to this data sheet at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.4 August 2011 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 9 of 9