A Comprehensive PHEMT Core Model For Switch Applications Ce-Jun Wei, Yu Zhu, Hong Yin, Olesky Klimashov, and Dylan Bartle Skyworks Solutions Inc. 20 Sylvan Road Woburn, MA 01801 USA 20 Sylvan Road, Woburn, MA 01801, USA Abstract — A comprehensive non-linear PHEMT core model for switch applications is described. The model combines an accurate description of CV below pinch-off and a 2D CV function above pinch-off for better charge and capacitance modeling. At the same time, more accurate is the model’s IV prediction on the current in the near pinch-off region. The model has detailed leakage equations and dispersion function covering a wide range of operation, and taking gate lag into consideration. The model was verified by a variety of measured data, including IV/transfer curves, leakages, floating voltages and S-parameters/CV curves. In a switch application, comparison between modeled and measured data on harmonics, insertion loss and isolation regarding various driving power shows excellent and consistent agreement in both on-state and off-state. non-zero internal DC Vds of stacked FET for a multi-gate FET. - Accurate modeling of IV around sub-pinch-off region - Accurate modeling of gate leakages and drain-source leakages - Bias-dependent dispersion, including gate-lag We have developed a new PHEMT model for switch applications [2,4] as well as for LNA applications[3]. The model has many features including comprehensive and distributed extrinsic model. The core model meets all above challenges and the model has been incorporate into company’s design kits in ADS and GoldenGate/Cadence. It is proven to be robust. In this paper we’ll address the issues and solutions related to the intrinsic part of the PHEMT model. The extrinsic part and multi-gate device modeling were and will be continuously presented elsewhere[5]. I. INTRODUCTION II. CAPACITANCE/CHARGE MODEL Although many compact models for PHEMT’s have been published and have been incorporated into most popular automated design software applications, few of these models could be used for switch design in wireless communications. For example, PHEMT multi-mode multi-throw switches operating at off state with bias far below pinch-off have very low harmonics down to -50>-60dBm for drive power of 35dBm. The only nonlinearity comes from the gate capacitance as a function of gate bias. Therefore, accurate modeling of CV relation below pinch-off is critical. Unfortunately most popular models assume that the capacitance is either, when below pinch-off, a constant that makes the model inaccurate or, when near/below pinch-off, a 2-D function that exaggerates the harmonics owing to troublesome associated trans-capacitances. Simulation of switch circuits using these models can often predict much higher harmonics than measured by up to 20dB! Proper modeling of leakages and their partition are also crucial in multi-gate switch modeling. Again most of the existing models lack accurate description of leakages. Another issue for switch applications is that the device normally is operated at Vds=0 and at this point the model is symmetric and can be swapped between drain and source. Gummel Symmetry Test (GST) must be satisfied by the model so that the derivative at Vds=0 could be ensured to be continuous up to 3rd order or higher. Dispersion description is required not only at active and on-state region but also at pinch-off region. Gate-lag effects have an impact on the transition from off-state to on-state. Therefore comprehensive PHEMT modeling is indispensable for switch application. The requirement for core model is summarized as follows: - Accurate modeling of C(V) below pinch-off - Smooth transition from 2D CV function above pinch-off to 1D function below pinch-off. 2D CV functions are used since the RF Vds swing could be very high and there is A typical Cgs(Vgs) or Cgd(Vgd) at Vds=0 is shown in figure 1. The pinchoff voltage Vp is around -1 V. The Cgs increases quickly with Vgs when Vgs is crossing Vp. The Cgs continues to rise with Vgs after Vp but more slowly depending on Vgs. A proper description of Qg(V) has two parts, Qg1(x) and Qg2(x), dedicating to Vgs<Vp and Vgs>=Vp correspondingly, where x stands for Vgs or Vgd. The first part is always a one-dimensional function, to cover different technologies we introduced more parameters. The expression is as follows. Qg1( x) C _o C1 (v( x) Vp)2 2 C 2a (v1( x) Vtl)3 3 C1a (v1( x) Vtl) 2 2 Cea dve e (1) v ( x ) Vp dve where v( x) ( x Vp) 2 2 x Vp del 2 (2) and v1( x) x Vtl ( x Vtl)2 2 dela2 (3) C1 is the coefficient of capacitance linearly decreasing with negative Vg starting from Vp with transit voltage del. Cea is the coefficient of exponentially decreasing capacitance with decreasing distance dve. C1a is the linear coefficient and C2a is the second order factor in capacitance-voltage curve starting at Vg=Vt1 with smoothing voltage, dela. The derivative of Qg1(x) leads to below-pinchoff gate capacitance Cg1(x) .The second part of charge can be represented as follows: Qg 2( x) where C10 d1 ln(1 e x Vp d1 (1 u ( x) ) Co Vbi )1 Vbi m0 1 m0 (4) u ( x) x Vp ( x Vp) 2 2 del 2 (5) Similar to that of Qg1(x), the first-order derivative of Qg2(x) defines the above-pinchoff gate capacitance Cg2(x). The fitting curve (line) compared to measured curve (symbol) for a PHEMT device is shown in Figure 1. 8E-13 7E-13 Cgs_model Cgs_meas 6E-13 5E-13 4E-13 3E-13 Figure 2. Gate Capacitance-Cgs as function of Vgs at Vds=0 to 2 V step 0.2V for a PHEMT Device. Line: Modeled, symbol: Extracted from S-parameters: Cg1(Vgs) Cgs2 Cgs (11) Vgs Vp Vgs Vp 2E-13 1E-13 0 -5 -4 -3 -2 Vg -1 0 1 Cgd Figure 1. Gate Capacitance-Cgs as function of Vgs for Vds=0 for a PHEMT Device. Line: modeled, symbol: measured The charge-capacitance model above fits the Cgs(Vgs) and Cgd(Vgd) very well at Vds=0. For other than Vds=0, the capacitance and charge above pinch-off become a two-dimensional voltage function. That is to say, Cgs is not only a function of Vgs but also a function of Vds. For capacitance based model, we use the following equations to replace Cg2 in the Cold-FET case mentioned above. Cgd 2 Cgd1 f 1 Cgs1 f 2 Cp2(Vgs) e cvd Vds Cgs2 Cgd1 f 2 Cgs1 f 1 (6) (Vgd v _ t ) del 2 1 e Cp2(Vgd ) ecvd Vds (Vgs v _ t ) 1 e (7) del 2 Where Co x mo (1 ) Vbio Cgs1 C11 C12 Cgd1 C12 Cp2( x) (8) (9) (10) Here C11, C12 are defined identically to what those in EEHEMT charge model are defined. The model in active region (Vgs>Vp) differs from EEHEMT model is additional charge term Cp2*exp term that depends on Vds as well. The fitting can be reasonably good over a wide bias range as shown in figure 2. The fitting range covers Vds from 0V to 2 V step 0.2 V and Vgs from -1.4V to 0.6V step 0.05V or 0.1V. Since there are no unified equations to cover both the active region and the cutoff region (below Vp), the combination of two charge/capacitance models are important and poor transition can affect the switch modeling results. For capacitance based model it is simpler and straightforward. The Capacitances can be combined as follows: d2 1 e Cg1(Vgd ) Cgd 2 Vgd Vp 1 e d2 1 e (12) Vgd Vp d2 1 e d2 Owing to surface trapping effects, the large-signal RF swing may see different CV dependence. To address this issue, we introduced another parameter _Cc. In varying parts of CV characteristics, Vgs are replaced by an effective gate-source voltage Vgse which is defined as follows: (13) Vgse _ Cc Vgso (1 _ Cc) Vgs In a similar method, we also define an effective gate-drain voltage Vgde to replace Vgd in the CV characteristics. In this way, the small-signal CV remains the same , but large signal Cgs will reduced by 1-_Cc factor. In the charge model, we can use similar trasition functions for Qg1 and Qg2 as (11) and (12). Caution must be taken over capacitances in the vicinity of Vp. (11) and (12) have denominators involving voltage differences, Vgs-Vp and Vgs-Vp, and their derivatives may become huge in the transition region near Vp. To diminish this effect, we modified the gate charge definition Qg into the following form: (14) Qg Qg1(Vgs) [Qg 2(Vgs) Qg 2(Vp)] f (Vgs) Where f(vgs) is a transition function--1/(1+exp(-(Vg-Vp)/d2)). As a result, the capacitance is derived as the derivative of charge term: Qg Cg1(Vgs) Cgs2 f (Vgs) Vgs [Qg 2(Vgs) Qg 2(Vp)] f (Vgs) Cgs (15) The smoothing action results in the last term in (15). This term is an extra contribution to the previous defined Cgs. But it stays very small at all Vgs since the factor [Qg(vgs,Vds) -Qg(Vp.Vds)] is close to 0 when Vgs is close to Vp, and f’(Vgs) ≈0 at elsewhere. III. IV modeling Most advanced models can generate good fitting in IV curves. Considering the best convergence, we borrowed Symmetric Angelov IV model [4] as starting model that has good description of self-heating effects on Imax, Vp and other parameters. However, Angelov model is implicit in terms of pinchoff. It is not (17) The equation contain similar terms, p , n as in Angelov model, but we add additional terms to account for cutoff near pinchoff. Vp x dVp ( x) 0 (0.9 x) ) -5 -10 -15 -20 -25 -30 -35 freq (400.0MHz to 7.000GHz) 0 1 2 p 0.5x[1 tanh( x Vp )] dv2 (19) The αo is the slope at the linear region of the DCIV curve at vgs=0.9, and αp is the slope at below and near Vp. This parameter not only fits the slope at low vgs region but also fits the real part of S-parameters in the range near and cross Vp. The model apparently satisfies the GST condition since both Idsp, and Idsn are continuous and best conditioned functions. We should point out that the self-heating effects are incorporated with a sub-thermal circuit that defines the junction temperature rise. In the model, Imax, Vt, Vp and C10 are all functions of junction temperature Tj. The dependence of Imax on Tj results in a drop of Ids at saturation and high power region. Combined with device thermal conductance model, the model can give good fitting for various size and configuration of devices 4 5 6 7 Figure 4. Modeled(line) verse measured S-parameters(symbol) a series connected PCM SG-PHEMT as a function of Vg (from -3V to 0.2V) at Vds=0 IV Leakage model Leakage fitting is important especially for multigate FETs where the internal channel is floating. The internal gate-channel voltage is dependent on the partition of leakages between gate-channel and drain/source to internal channel. The GD or GS leakage are expressed as three components that dominated at lower, medium and high negative Vg area. 1 igs _ lk 1 igs _ lkl 1 igs _ lkm 1 igs _ lkh Ids _ lk eN I 2 M v (v g1) v (v g1)) Vds 1] I tanh(K 1 1E-2 (20) where i gs_lkl ,i gs_lkm , i gs_lkh are diode-like gate currents at lower, medium and high negative vgs regions. In this model, DS leakage near pinch-off is a 2-D function of Vds and Vgs/Vgd: [e ( N 3E-1 1E-1 e Vds) (21) Vgo Vg1 dVg With vg1 as Vgs at non-negative Vds and as Vgd at negative Vds and with v(x) defined in (2). DS leakage in the high Vds region follows a diode-like relation: Id _ high Iho (e Ndh Vd lim 1) (22) 1E-3 IDS.i, A Id_IV 3 freq, GHz n (18) Idsn is the same as Idsp but it replaces Vgs with Vgd and Vds with –Vds. Another modification is slope function, the equation α(x) describes the vgs dependence of slope parameter at linear region. It is written as follows: fp( x) 1/(1 e Model and measure dB(S21) (1 Im ax (1 tanh( p)) fp(Vgs) 2 Vds) tanh( (Vgs) Vds) 0 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 Idsp . Model and Measure S21 directly accessible to the pinchoff parameter and performance near sub-threshold region. The IV equations are a modified Angelov symmetric model [1] and they can be expressed as: (16) Ids Idsp Idsn where 1E-4 1E-5 1E-6 1E-7 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 Measured (symbol) vs modeled (line) floating Vgd Vg 0.5 Measured(symbol) vs modeled(line) gate leakage 0.0 0.0 -5.0E-8 PHEMT Device. Vd=1,2,3 and 4V. Line: modeled, symbol: measured -1.0 Ig_lk (A) Figure 3. Comparison of modeled and measured transfer curves for a Vgd_float (V) -0.5 -1.5 -1.5E-7 -2.0 -2.0E-7 -2.5 In the above equations the parameter definitions were not given and the authors assume they are self-explanatory. Figure 3 show the fitting of transfer curves in log scale, Vds=1 to 4 V step 1V. It is shown that the model fitting around Vp is excellent. Figure 4 shows modeled and measured S21 for a series connected PHEMT , the gate is connected with 7.5 KOhm resistor and biased from -3V all the way to 0.2V across Vp region. S21 is the transmission from source to drain. The parameter of αp fits the real part of S21 when Vgs cross Vp. -1.0E-7 -3.0 -6 -5 -4 -3 Vg1 -2 -1 0 -2.5E-7 -6 -5 -4 -3 -2 -1 0 Vg1 Figure 5: Modeled (line) verse measured(symbol) gate leakage and floating voltage for a PCM PHEMT Device. Where Vd lim Vd Vb (Vd Vb)2 2 del 2 (23) Here Vb is the starting point of DS breakdown. The fitted gate leakage and floating gate-to-drain voltage at drain open condition is shown in figure 5. Since the internal channel nodes of a multi-gate switch FET at off sate are floating, precise models of leakages are critical to accurate prediction for the whole device. III. DISPERSION MODEL vgt vg cfw(Vgso,Vdso) vgs _ rf cfw(Vgdo,Vdso) vgd _ rf cbk (Vgso,Vdso) vds _ rf Figure 6. Simulation bench of power drive for a series connected PCM PHEMT used in a switch configuration. Modeled vs Measured Pout & 2nd/3rd harmonics (dBm) We define a bias dependent feed-forward factor, cfw and feedback factor cbk to address the difference in RF Gm and RFGds from DCGm and DCGds respectively. There are three slow RC time constant circuits at gate-source/gate-drain branches and drain-source branch. The currents flowing through GS and GD RC branches generate feed-forward voltages on the gate and hence alter the Gm at vds>0 as the GS branch feed-forward excitation and vds<0 as the GD feed-forward excitation. On the other hand, the DS RC branch has feedback voltage added to the gate and thus alters the RF-Gds curves. The corrected input to the gate would be as follows: (24) Here, Vgso, Vgdo and Vdso are the DC components of vgs, vgd and vds. Vgs_rf, vgd_rf and vds_rf are their corresponding rf or ac components. When Vgso or Vgdo is below pinch-off, the cfw describes the gate lag. 30 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Pin (dBm) Pout 2fo 3fo . The model was validated for a SG-PHEMT in a switch configuration. The PHEMT is in a series connection configuration. Namely the RF feeds on source side and output at drain side. The gate is a meander line connected with a 7kOhm bulk resistance. When the gate bias is at Vg=0, it is at switch on-state, whereas it is at switch off-state when the Vg=-3V. Swept power from 15dBm to 30dBm at f=0.9GHz was applied the device. The configuration is shown in figure 6. Figure 7 shows the output power, 2nd and 3rd harmonics against input power when switch is on, i.e. Vg=0. Excellent coincidence between measured (symbol) and modeled (line) is achieved. Insertion loss as function of Pin can be also seen from Pout curves. Figure 8 shows the output power, 2nd harmonics and third harmonics against input power when switch is off, i.e. Vg=0. Agreement between measured (symbol) and modeled (line) is also achieved. Isolation as function of Pin can be also seen from Pout curves. IV. CONCLUSION A comprehensive PHEMT core model has been developed for switch applications. The model was validated by a variety of characteristics, including IV curves, S-parameter in linear region, CV curves below and above pinch-off, floating voltages, and leakages. At the same time, predictions of this model exhibit excellent agreement with measured data including insertion loss, isolation and harmonics at power drive condition. Figure 7. Models (line) verse measured (symbol) Pout, 2nd and 3rd harmonics verse input power at Vg=0 or on state. f=0.9 GHz. Modeled vs Measured Pout & 2nd/3rd harmonics (dBm) VI. MODELED HAMONICS AT SWITCH CONDITION 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin (dBm) Pout 2fo 3fo Figure 8. Models (line) verse measured (symbol) Pout, 2nd and 3rd harmonics verse input power at Vg=-3 V or off state. f=0.9 GHz. Reference 1. 2. 3. 4. 5. I. Angelov, L. Bengtsson, M. Garcia, "Extensions of the Chalmers Nonlinear HEMT and MESFET Model," IEEE MTT Vol. 44, No. 10, October 1996. C.-J. Wei et al, “Analysis and modeling on linearity of multi-thru TX/RX switches,” Proc. 3rd MAPE 2009, pp.5-8, Oct. 27-28,2009, Beijing. C-J. Wei, Yu Zhu et al, “Scaleable Two-Current Low-Noise Phemt Model that Predicts IP3,” 2008 APMC at Hong Kong, Dec. 2008 C.J. Wei et al," Large-Signal PHEMT Switch Model Accurately Predicts Harmonics and Two-Tone Intermodulations," MTT-Symposium, Long Beach, June 12-17, 2005 C.-J. Wei et al,” Distributed Switch FET Model that predicts Better Insertion Loss and Harmonics”, 2010 EUMW, Paris

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