1/12 ◇STRUCTURE Silicon Monolithic Integrated Circuit ◇PRODUCT 256×8 bit Electrically Erasable PROM ◇PART NUMBER BU9833GUL-W ◇PHYSICAL DIMENSION Fig.-1 ◇BLOCK DIAGRAM Fig.-2 ◇USE General purpose ◇FEATURES ・ 256 registers × 8 bits serial architecture ・Single power supply (1.7V～5.5V) ・Two wire serial interface ・Self-timed write cycle with automatic erase ・8 byte Page Write mode ・Low power consumption Write ( 5V ) : 1.2mA (Typ.) Read ( 5V ) : 0.2mA (Typ.) Standby ( 5V ) : 0.1μA(Typ.) ・DATA security Write protect feature (WP pin) Inhibit to WRITE at low VCC ・WLCSP6Pin package ------ VCSP50L1 ・High reliability fine pattern CMOS technology ・Endurance : 1,000,000 erase/write cycles ・Data retention : 40 years ・Filtered inputs in SCL・SDA for noise suppression ・Initial data FFh in all address ◇ ABSOLUTE MAXIMUM RATING (Ta=25℃) Parameter Symbol Rating Unit Supply Voltage VCC -0.3～6.5 V Power Dissipation Ｐｄ Storage Temperature Tstg -65～125 ℃ Operating Temperature Topr -40～85 ℃ Terminal Voltage － -0.3～VCC+1.0 *2 V VCSP50L1 *1 Degradation is done at 2.2mW/℃ for operation above 25℃. *2 The max value of Terminal Voltage is not over 6.5V. REV. A 220 *1 mW 2/12 ◇RECOMMENDED OPERATING CONDITION Parameter Symbol Rating Unit Supply Voltage VCC 1.7～5.5 V Input Voltage VIN 0～VCC V ◇DC OPERATING CHARACTERISTICS (Unless otherwise specified Ta=-40～85℃､VCC=1.7～5.5V) Parameter Specification Symbol Unit min. typ. max. test condition “H” Input Voltage1 VIH1 0.7VCC － VCC+1.0 V 2.5V≦Vcc≦5.5V “L” Input Voltage1 VIL1 -0.3 － 0.3VCC V 2.5V≦Vcc≦5.5V “H” Input Voltage2 VIH2 0.8VCC － VCC+1.0 V 1.8V≦Vcc＜2.5V “L” Input Voltage2 VIL2 -0.3 － 0.2VCC V 1.8V≦Vcc＜2.5V “H” Input Voltage3 VIH3 0.9VCC － VCC+1.0 V 1.7V≦Vcc＜1.8V “L” Input Voltage3 VIL3 -0.3 － 0.1VCC V 1.7V≦Vcc＜1.8V “L” Output Voltage1 VOL1 － － 0.4 V IOL=3.0mA，2.5V≦Vcc≦5.5V （SDA） “L” Output Voltage2 VOL2 － － 0.2 V IOL=0.7mA，1.7V≦Vcc＜2.5V （SDA） Input Leakage Current ILI -1 － 1 μA VIN=0V～VCC Output Leakage Current ILO -1 － 1 μA VOUT=0V～VCC (SDA) VCC=5.5V,fSCL=400ｋHz,tWR=5ms － ICC1 － 2.0 mA Operating Current ICC2 － － 0.5 mA ISB － － 2.0 μA Standby Current Byte Write Page Write VCC=5.5V,fSCL=400ｋHz Random Read Current Read Sequential Read VCC=5.5V,SDA,SCL=VCC A0,A1,A2=GND,WP=GND ○ This product is not designed for protection against radioactive rays. ◇MEMORY CELL CHARACTERISTICS (Ta=25℃、VCC＝1.7～5.5V) Specification Prameter Unit Min. Typ. Max. Write/Erase Cycle *1 1,000,000 - - Cycles Data Retention *1 40 - - Years *1 Not 100% TESTED REV. A 3/12 Product Name：BU9833GUL-W 9833 LOT NO. Fig.-1 PHYSICAL DIMENSION （VCSP50L1） （Unit : mm） ◇BLOCK DIAGRAM REV. A 4/12 VCC GND 2 Kbit EEPROM ARRAY 8bit 8bit ADDRESS DECODER SLAVE・WORD ADDRESS REGISTER 8bit START A2 DATA REGISTER WP STOP SCL CONTOROL LOGIC ACK HIGH VOLTAGE GEN. SDA VCC LEVEL DETECT Fig.-2 BLOCK DIAGRAM ◇PIN CONFIGURATION C B A C2 C1 ○ ○ B1 B2 ○ ○ A1 A2 ○ ○ 1 INDEX POST 2 Fig.-3 BU9833GUL－Ｗ（bottom view） ◇PIN NAME Land No. PIN NAME I/O FUNCTIONS C2 VＣＣ - Power Supply C1 A2 IN Slave Address Set B2 WP IN Write Protect Input B1 GND - Ground （0V） A2 SCL IN Serial Clock Input A1 SDA IN/OUT Slave and Word Address, Serial Data Input, Serial Data Output *1 *1 An open drain output requires a pull-up resister. ◇AC OPERATING CHARACTERISTICS (Unless otherwise specified Ta=-40～85℃､VCC=1.7～5.5V) REV. A 5/12 Parameter Symbol FAST-MODE STANDARD-MODE 2.5≦Vcc≦5.5V 1.7≦Vcc≦5.5V Min. Typ. Max. Min. Typ. Max. Unit Clock Frequency fSCL － － 400 － － 100 kHz Data Clock High Period tHIGH 0.6 － － 4.0 － － μs Data Clock Low Period tLOW 1.2 － － 4.7 － － μs SDA and SCL Rise Time ※1 tR － － 0.3 － － 1.0 μs SDA and SCL Fall Time ※1 tF － － 0.3 － － 0.3 μs Start Condition Hold Time tHD:STA 0.6 － － 4.0 － － μs Start Condition Setup Time tSU:STA 0.6 － － 4.7 － － μs Input Data Hold Time tHD:DAT 0 － － 0 － － ns Input Data Setup Time tSU:DAT 100 － － 250 － － ns Output Data Delay Time tPD 0.1 － 0.9 0.2 － 3.5 μs Output Data Hold Time tDH 0.1 － － 0.2 － － μs tSU:STO 0.6 － － 4.7 － － μs Bus Free Time tBUF 1.2 － － 4.7 － － μs Write Cycle Time tWR － － 5 － － 5 ms tI － － 0.1 － － 0.1 μs WP Hold Time tHD：WP 0 － － 0 － － ns WP Setup Time tSU：WP 0.1 － － 0.1 － － μs WP High Period tHIGH：WP 1.0 － － 1.0 － － μs Stop Condition Setup Time Noise Spike Width (SDA and SCL) ※1：Ｎot 100％ TESTED REV. A 6/12 ◇SYNCHRONOUS DATA TIMING tR tF tHIGH SCL tHD:STA tSU:DAT tLOW tHD:DAT SDA (IN) tBUF tPD tDH SDA (OUT) SCL tSU:STA tHD:STA tSU:STO SDA START BIT STOP BIT Fig.-4 SYNCHRONOUS DATA TIMING ○ SDA data is latched into the chip at the rising edge of SCL clock. ○ Output date toggles at the falling edge of SCL clock. ◇WRITE CYCLE TIMING SCL SDA D0 ACK tWR WRITE DATA(n) STOP CONDITION Fig.-5 WRITE CYCLE TIMING REV. A START CONDITION 7/12 ◇WP TIMING SCL DATA(n) DATA(1) SDA D1 D0 ACK ACK ｔＷＲ STOP BIT WP tSU：WP ｔＨＤ：WP Fig-6(a) WP TIMING OF THE WRITE OPERATION SCL DATA(n) DATA(1) SDA D1 D0 ACK ACK tHIGH:WP WP Fig-6(b) WP TIMING OF THE WRITE CANCEL OPERATION ○For the WRITE operation, WP must be "LOW" during the period of time from the rising edge of the clock which takes in D0 of first byte until the end of tWR. ( See Fig-6(a) ) During this period, WRITE operation is canceled by setting WP "HIGH".（ See Fig-6(b) ） ○In the case of setting WP "HIGH" during tWR, WRITE operation is stopped in the middle and the data of accessing address is not guaranteed. Please write correct data again in the case. ◇DEVICE OPERATION REV. A 8/12 ○START CONDITION (RECOGNITION OF START BIT) ・All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. ・The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. （See Fig-4 SYNCHRONOUS DATA TIMING） ○STOP CONDITION (RECOGNITION OF STOP BIT) ・All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. （See Fig-4 SYNCHRONOUS DATA TIMING） ○NOTICE ABOUT WRITE COMMAND ・In the case that stop condition is not excuted in WRITE mode, transfered data will not be written in a memory. ○DEVICE ADDRESSING ・Following a START condition, the master output the slave address to be accessed. ・The most significant four bits of the slave address are the “device type indentifier,” For this device it is fixed as “1010.” ・The next bit (device address) identify the specified device on the bus. The device address is defined by the state of A2 input pin. This IC works only when the device address inputted from SDA pin correspond to the state of A2 input pin. Using this address scheme, up to two devices may be connected to the bus. ・The last bit of the stream (R/W … READ/WRITE) determines the operation to be performed. When set to “1”, a read operation is selected ; when set to “0”, a write operation is selected. R/W set to “0” ･ ･ ･ ･ ･ ･ ･ ･ WRITE (including word address input of Random Read) R/W set to “1” ･ ･ ･ ･ ･ ･ ･ ･ READ １ ０ １ ０ A２ ０ ０ Ｒ／Ｗ ○WRITE PROTECT (WP) When WP pin set to VCC(H level), write protect is set for 256 words (all address). When WP pin set to GND(L level), enable to write 256 words (all address). Either contorol this pin or connect to GND ( or Vcc). It is inhibited from being left unconnected. ○ACKNOWLEDGE REV. A 9/12 ・Acknowledge is a software convention used to indicate successful data transfers. The transmitter device will release the bus after transmitting eight bits. (When inputting the slave address in the write or read operation, transmitter is μ-COM. When outputting the data in the read operation, it is this device.) ・During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that the eight bits of data has been received. (When inputting the slave address in the write or read operation, receiver is this device. When outputting the data in the read operation, it is μ-COM.) ・The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit). ・In the WRITE mode, the device will respond with an Acknowledge, after the receipt o feach subsequent 8-bit word (word address and write data). ・In the READ mode, the device will transmit eight bit of data, release the SDA line, and monitor the line for an Acknowledge. ・If an Acknowledge is detected, and no STOP condition is generated by the master, the device will continue to transmit the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to the standby mode. (See Fig-7 ACKNOWLEDGE RESPONSE FROM RECEIVER) START CONDITION (START BIT) SCL （Fromμ-COM） 1 8 9 SDA （μ-COM OUTPUT DATA) SDA （IC OUTPUT DATA） Acknowledge Signal (ACK Signal) Fig.-7 ACKNOWLEDGE RESPONSE FROM RECEIVER ◇BYTE WRITE REV. A 10/12 S T A R T SDA LINE W R I T E SLAVE ADDRESS 1 0 1 0 A2 0 WORD ADDRESS R / W DATA WA 0 WA 7 0 D0 D7 A C K A C K S T O P A C K WP Fig.-8 BYTE WRITE CYCLE TIMING ○By using this command, the data is programed into the indicated word address. ○When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory array. ◇ PAGE WRITE S T A R T SDA LINE SLAVE ADDRESS W R I T E WORD ADDRESS（ｎ） WA 7 1 0 1 0 A2 0 0 R A / C W K DATA(n+7) DATA(n) WA 0 D7 A C K S T O P D0 D0 A C K A C K WP Fig.-9 PAGE WRITE CYCLE TIMING ○ This device is capable of eight byte Page Write operation. ○ When two or more byte data are inputted, the three low order address bits are internally incremented by one after the receipt of each word. The five higher order bits of the address(WA7～WA3) remain constant. ○If the master transmits more than eight words, prior to generating the STOP condition, the address counter will “roll over,” and the previous transmitted data will be overwritten. REV. A 11/12 ◇CURRENT READ S T A R T SDA LINE R E A D SLAVE ADRESS DATA 1 0 1 0 A2 0 0 D7 R / W S T O P D0 A C K A C K Fig.-10 CURRENT READ CYCLE TIMING ○In case that the previous operation is Random or Current Read (which includes Sequential Read respectively), the internal address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the next word address (n+1). If the last command is Byte or Page Write, the internal address counter stays at the last address (n). Thus Current Read outputs the data of the word address (n). ○If an Acknowledge is detected, and no STOP condition is generated by the master (μ-COM), the device will continue to transmit the data. ［It can transmit all data (2kbit 256word)］ ○If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition befere returning to the standby mode. NOTE) If an Acknowledge is detected with "Low" level, not "High" level, command will become Sequential Read. So the device transmits the next data, Read is not terminated. In the case of terminating Read, input Acknowledge with "High" always, then input stop condition. ◇RANDOM READ S T A R T SDA LINE SLAVE ADDRESS W R I T E WORD ADDRESS（ｎ） WA 7 1 0 1 0 A2 0 0 R A / C W K S T A R T WA 0 SLAVE ADDRESS R E A D A C K DATA(n) D7 1 0 1 0 A2 0 0 R A / C W K S T O P D0 A C K Fig.-11 RANDOM READ CYCLE TIMING ○Random Read operation allows the master to access any memory location indicated word address. ○If an Acknowledge is detected, and no STOP condition is generated by the master (μ-COM), the device will continue to transmit the data. ［It can transmit all data (2kbit 256word)］ ○If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition befere returning to the standby mode. NOTE) If an Acknowledge is detected with "Low" level, not "High" level, command will become Sequential Read. So the device transmits the next data, Read is not terminated. In the case of terminating Read, input Acknowledge with "High" always, then input stop condition. ◇SEQENTIAL READ REV. A 12/12 S T A R T SDA LINE SLAVE ADDRESS R E A D 1 0 1 0 A2 0 0 R A / C W K DATA(n+x) DATA(n) D7 S T O P D0 D7 A C K A C K D0 A C K Fig.-12 SEQUENTIAL READ CYCLE TIMING （ Current Read ） ○If an Acknowledge is detected, and no STOP condition is generated by the master (μ-COM), the device will continue to transmit the data. ［It can transmit all data (2kbit 256word)］ ○If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition befere returning to the standby mode. ○The Sequential Read operation can be performed with both Current Read and Random Read. NOTE) If an Acknowledge is detected with "Low" level, not "High" level, command will become Sequential Read. So the device transmits the next data, Read is not terminated. In the case of terminating Read, input Acknowledge with "High" always, then input stop condition. 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