TEMIC TS80C31X2-VCAR

TS80C31X2
8-bit CMOS Microcontroller 0-60 MHz
1. Description
TEMIC TS80C31X2 is high performance CMOS and
ROMless versions of the 80C51 CMOS single chip 8bit microcontroller.
The TS80C31X2 retains all features of the TEMIC
TSC80C31 with 128 bytes of internal RAM, a 5-source,
4 priority level interrupt system, an on-chip oscilator
and two timer/counters.
In addition, the TS80C31X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
The fully static design of the TS80C31X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C31X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
●
80C31 Compatible
●
• 8031 pin and instruction compatible
• 5 Interrupt sources,
• Four 8-bit I/O ports
• 4 priority level interrupt system
• Two 16-bit timer/counters
●
Interrupt Structure with
●
Full duplex Enhanced UART
• 128 bytes scratchpad RAM
• Framing error detection
High-Speed Architecture
• Automatic address recognition
• 40 MHz @ 5V, 30MHz @ 3V
●
Power Control modes
• Idle mode
• X2 Speed Improvement capability (6 clocks/
machine cycle)
• Power-down mode
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
• Power-off Flag
●
Dual Data Pointer
●
Once mode (On-chip Emulation)
●
Asynchronous port reset
●
Power supply: 4.5-5.5V, 2.7-5.5V
●
Temperature ranges: Commercial (0 to 70oC) and
Industrial (-40 to 85oC)
●
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1
(13.9 footprint)
Rev. A - Mar. 19, 1999
1
Preliminary
TS80C31X2
TxD
RxD
3. Block Diagram
(1) (1)
XTAL1
EUART
XTAL2
ALE/ PROG
RAM
128x8
C51
CORE
PSEN
IB-bus
CPU
EA
Timer 0
Timer 1
(1)
INT
Ctrl
Parallel I/O Ports & Ext. Bus
Port 0 Port 1 Port 2 Port 3
P3
P2
P1
P0
(1) (1)
T1
T0
RESET
(1) (1)
INT1
WR
(1)
INT0
RD
(1): Alternate function of Port 3
2
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
4. SFR Mapping
The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3
• Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• Power and clock control registers: PCON
• Interrupt system registers: IE, IP, IPH
• Others: CKCON
Table 1. All SFRs with their address and their reset value
Bit
addressable
Non Bit addressable
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
F8h
F0h
FFh
B
0000 0000
F7h
E8h
E0h
EFh
ACC
0000 0000
E7h
D8h
D0h
DFh
PSW
0000 0000
D7h
C8h
CFh
C0h
C7h
B8h
IP
XXX0 0000
SADEN
0000 0000
B0h
P3
1111 1111
A8h
IE
0XX0 0000
A0h
P2
1111 1111
98h
SCON
0000 0000
90h
P1
1111 1111
88h
TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
80h
P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
0/8
1/9
2/A
3/B
BFh
IPH
XXX0 0000
SADDR
0000 0000
B7h
AFh
AUXR1
XXXX 0XX0
A7h
SBUF
XXXX XXXX
9Fh
97h
TH0
0000 0000
4/C
TH1
0000 0000
5/D
6/E
CKCON
XXXX XXX0
8Fh
PCON
00X1 0000
87h
7/F
reserved
Rev. A - Mar. 19, 1999
3
Preliminary
TS80C31X2
5. Pin Configuration
P0.0
P1.2
P1.3
P1.4
P1.5
3
4
P1.6
P1.7
RST
7
8
29
28
27
14
15
26
16
25
17
18
19
20
24
P1.4
P1.3
P1.2
P1.1
P1.0
VSS1/NIC*
2
1 44 43 42 41 40
23
22
21
7
8
39
38
P0.4/AD4
P1.6
P1.7
9
37
P0.6/AD6
RST
10
36
P0.7/AD7
P3.0/RxD
35
34
33
EA
P3.1/TxD
11
12
13
P2.4
P2.3
P3.2/INT0
P3.3/INT1
14
15
32
31
PSEN
P2.2
P3.4/T0
P3.5/T1
16
30
P2.6/A14
17
29
P2.5/A13
NIC*
P2.1
PLCC44
NIC*
ALE
P2.7/A15
18 19 20 21 22 23 24 25 26 27 28
P2.0
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VCC
VSS1/NIC*
P1.0
P1.1
P1.2
P1.3
P1.4
P0.5/AD5
P2.3/A11
P2.4/A12
PDIL40
3
P2.2/A10
11
12
13
4
P3.6/WR
VSS
EA
ALE
PSEN
P2.7
P2.6
P2.5
5
P2.1/A9
XTAL1
P0.7
P1.5
NIC*
P2.0/A8
P3.7/RD
XTAL2
32
31
30
P0.6
VSS
P3.5/T1
P3.6/WR
9
10
6
P0.5
XTAL1
P3.4/T0
P0.3
P0.4
6
XTAL2
P3.2/INT0
P3.3/INT1
36
35
34
33
5
P3.7/RD
P3.0/RxD
P3.1/TxD
P0.1
P0.2
37
P0.2/AD2
P0.3/AD3
VCC
39
38
P0.1/AD1
40
2
P0.0/AD0
1
P1.1
VCC
P1.0
44 43 42 41 40 39 38 37 36 35 34
P1.5
1
P1.6
2
P1.7
RST
3
4
P3.0/RxD
5
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
33
32
P0.4/AD4
31
P0.6/AD6
30
P0.7/AD7
29
28
EA
27
ALE
PSEN
9
26
25
10
24
P2.6/A14
11
23
P2.5/A13
PQFP44
VQFP44
6
7
8
P0.5/AD5
NIC*
P2.7/A15
P2.3/A11
P2.4/A12
P2.2/A10
P2.1/A9
NIC*
P2.0/A8
VSS
XTAL1
XTAL2
P3.7/RD
P3.6/WR
12 13 14 15 16 17 18 19 20 21 22
*NIC: No Internal Connection
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Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
Table 2. Pin Description for 40/44 pin packages
PIN NUMBER
TYPE
NAME AND FUNCTION
16
39
I
I
44
38
I
39-32
43-36
37-30
I/O
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
P2.0-P2.7
21-28
24-31
18-25
I/O
P3.0-P3.7
10-17
11,
13-19
5,
7-13
I/O
Reset
10
11
12
13
14
15
16
17
9
11
13
14
15
16
17
18
19
10
5
7
8
9
10
11
12
13
4
I
O
I
I
I
I
O
O
I
ALE
30
33
27
O (I)
PSEN
29
32
26
O
Ground: 0V reference
Optional Ground: Contact the Sales Office for ground connection.
Power Supply: This is the power supply voltage for normal, idle and powerdown operation
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during access to external program
and data memory. In this application, it uses strong internal pull-up when emitting
1s.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Port 3 also serves the special
features of the 80C51 family, as listed below.
RXD (P3.0): Serial input port
TXD (P3.1): Serial output port
INT0 (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset
using only an external capacitor to VCC.
Address Latch Enable: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used
for external timing or clocking. Note that one ALE pulse is skipped during each
access to external data memory.
Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
EA
31
35
29
I
External Access Enable: EA must be externally held low to enable the device
to fetch code from external program memory locations.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier
MNEMONIC
DIL
LCC
VQFP 1.4
VSS
Vss1
20
22
1
VCC
40
P0.0-P0.7
Rev. A - Mar. 19, 1999
5
Preliminary
TS80C31X2
6. TS80C31X2 Enhanced Features
In comparison to the original 80C31, the TS80C31X2 implements some new features, which are:
• The X2 option.
• The Dual Data Pointer.
• The 4 level interrupt priority system.
• The power-off flag.
• The ONCE mode.
• Enhanced UART
6.1 X2 Feature
The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following
advantages:
●
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
●
Save power consumption while keeping same CPU power (oscillator power saving).
●
Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
●
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.
6.1.1 Description
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.
2
XTAL1
FXTAL
XTAL1:2
state machine: 6 clock cycles.
CPU control
0
1
FOSC
X2
CKCON reg
Figure 1. Clock Generation Diagram
6
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
XTAL1
XTAL1:2
X2 bit
CPU clock
STD Mode
X2 Mode
STD Mode
Figure 2. Mode Switching Waveforms
The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles per instruction to 6 clock
cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature
(X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals
using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example
a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with
4800 baud rate will have 9600 baud rate.
Rev. A - Mar. 19, 1999
7
Preliminary
TS80C31X2
Table 3. CKCON Register
CKCON - Clock Control Register (8Fh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
X2
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
X2
Description
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2).
Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL).
Reset Value = XXXX XXX0b
Not bit addressable
8
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
6.2 Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size in a number of
ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address the external memory, and a single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3).
External Data Memory
7
0
DPS
AUXR1(A2H)
DPTR1
DPTR0
DPH(83H) DPL(82H)
Figure 3. Use of Dual Pointer
Rev. A - Mar. 19, 1999
9
Preliminary
TS80C31X2
Table 4. AUXR1: Auxiliary Register 1
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
DPS
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
DPS
Description
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
Reset Value = XXXX XXX0
Not bit addressable
Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’
pointer and the other one as a "destination" pointer.
10
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2
AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE
0003 05A2 INC AUXR1
0005 90A000 MOV DPTR,#DEST
0008
LOOP:
0008 05A2 INC AUXR1
000A E0
MOVX A,@DPTR
000B A3
INC DPTR
000C 05A2 INC AUXR1
000E F0
MOVX @DPTR,A
000F A3
INC DPTR
0010 70F6 JNZ LOOP
0012 05A2 INC AUXR1
; address of SOURCE
; switch data pointers
; address of DEST
; switch data pointers
; get a byte from SOURCE
; increment SOURCE address
; switch data pointers
; write the byte to DEST
; increment DEST address
; check for 0 terminator
; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However,
note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it.
In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence
matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1'
on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the
opposite state.
Rev. A - Mar. 19, 1999
11
Preliminary
TS80C31X2
6.3 TS80C31X2 Serial I/O Port
The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31.
It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous
Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and
reception can occur simultaneously and at different baud rates
Serial I/O port includes the following enhancements:
●
Framing error detection
●
Automatic address recognition
6.3.1 Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing
bit error detection feature, set SMOD0 bit in PCON register (See Figure 4).
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD = 1)
SM0 to UART mode control (SMOD = 0)
SMOD1 SMOD0
-
POF
GF1
GF0
PD
IDL
PCON (87h)
To UART framing error control
Figure 4. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop
bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit
is not found, the Framing Error bit (FE) in SCON register (See Table 5.) bit is set.
12
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can
clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,
RI rises on stop bit instead of the last data bit (See Figure 5. and Figure 6.).
RXD
D0
D1
D2
Start
bit
D3
D4
D5
D6
D7
Data byte
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
Figure 5. UART Timings in Mode 1
RXD
D0
Start
bit
D1
D2
D3
D4
D5
D6
Data byte
D7
D8
Ninth Stop
bit bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Figure 6. UART Timings in Modes 2 and 3
6.3.2 Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled
(SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by
allowing the serial port to examine the address of each incoming command frame. Only when the serial port
recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the
device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON
register in mode 0 has no effect).
Rev. A - Mar. 19, 1999
13
Preliminary
TS80C31X2
6.3.3 Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte
that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the
flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR
SADEN
Given
0101 0110b
1111 1100b
0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:
SADDR
SADEN
Given
1111 0001b
1111 1010b
1111 0X0Xb
Slave B:
SADDR
SADEN
Given
1111 0011b
1111 1001b
1111 0XX1b
Slave C:
SADDR
SADEN
Given
1111 0010b
1111 1101b
1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A
only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but
not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2
clear (e.g. 1111 0001b).
6.3.4 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as
don’t-care bits, e.g.:
SADDR
SADEN
Broadcast =SADDR OR SADEN
0101 0110b
1111 1100b
1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a
broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:
SADDR
1111 0001b
SADEN
1111 1010b
Broadcast 1111 1X11b,
Slave B:
SADDR
1111 0011b
SADEN
1111 1001b
Broadcast 1111 1X11B,
Slave C:
SADDR=
1111 0010b
SADEN
1111 1101b
Broadcast 1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the
master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send
and address FBh.
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Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
6.3.5 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX
XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards
compatible with the 80C51 microcontrollers that do not support automatic address recognition.
SADEN - Slave Address Mask Register (B9h)
7
6
5
4
3
2
1
0
4
3
2
1
0
Reset Value = 0000 0000b
Not bit addressable
SADDR - Slave Address Register (A9h)
7
6
5
Reset Value = 0000 0000b
Not bit addressable
Rev. A - Mar. 19, 1999
15
Preliminary
TS80C31X2
Table 5. SCON Register
SCON - Serial Control Register (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
7
Bit
Mnemonic
FE
SM0
Description
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
SM1
SM0
0
0
1
1
0
1
0
1
Mode
0
1
2
3
Description
Shift Register
8-bit UART
9-bit UART
9-bit UART
6
SM1
5
SM2
4
REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3
TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Baud Rate
FXTAL/12
Variable
FXTAL/64 or FXTAL/32
Variable
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
2
RB8
1
TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
0
RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 5. and Figure 6. in the other modes.
Reset Value = 0000 0000b
Bit addressable
16
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
Table 6. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic
7
SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
5
-
4
POF
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
3
GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.
Rev. A - Mar. 19, 1999
17
Preliminary
TS80C31X2
6.4 Interrupt System
The TS80C31X2 has a total of 5 interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts
(timers 0 and 1) and the serial port interrupt. These interrupts are shown in Figure 7.
High priority
interrupt
IPH, IP
3
INT0
IE0
0
3
TF0
0
3
INT1
IE1
0
3
Interrupt
polling
sequence, decreasing
from high to low priority
TF1
0
3
RI
TI
0
Individual Enable
Global Disable
Low priority
interrupt
Figure 7. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register (See Table 8.). This register also contains a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing
a bit in the Interrupt Priority register (See Table 9.) and in the Interrupt Priority High register (See Table 10.).
shows the bit values and priority levels associated with each combination.
18
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
Table 7. Priority Level Bit Values
IPH.x
IP.x
Interrupt Level Priority
0
0
0 (Lowest)
0
1
1
1
0
2
1
1
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 8. IE Register
IE - Interrupt Enable Register (A8h)
7
6
5
4
3
2
1
0
EA
-
-
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic
Description
7
EA
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt
enable bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
ES
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
3
ET1
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2
EX1
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
1
ET0
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0
EX0
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0XX0 0000b
Bit addressable
Table 9. IP Register
Rev. A - Mar. 19, 1999
19
Preliminary
TS80C31X2
IP - Interrupt Priority Register (B8h)
7
6
5
4
3
2
1
0
-
-
-
PS
PT1
PX1
PT0
PX0
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
PS
Serial port Priority bit
Refer to PSH for priority level.
3
PT1
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2
PX1
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1
PT0
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0
PX0
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Description
Reset Value = XXX0 0000b
Bit addressable
20
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
Table 10. IPH Register
IPH - Interrupt Priority High Register (B7h)
7
6
5
4
3
2
1
0
-
-
-
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
3
2
1
0
PSH
Description
Serial port Priority High bit
PSH
PS
0
0
0
1
1
0
1
1
Priority Level
Lowest
Highest
PT1H
Timer 1 overflow interrupt Priority High bit
PT1H
PT1
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX1H
External interrupt 1 Priority High bit
PX1H
PX1
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT0H
Timer 0 overflow interrupt Priority High bit
PT0H
PT0
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX0H
External interrupt 0 Priority High bit
PX0H
PX0
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reset Value = XXX0 0000b
Not bit addressable
Rev. A - Mar. 19, 1999
21
Preliminary
TS80C31X2
6.5 Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode.
In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port
functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had
at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to
be executed will be the one following the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give and indication if an interrupt occured during normal operation or
during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
terminated by an interrupt, the interrupt service routine can examine the flag bits.
The over way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the
hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
6.6 Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to Table 6., PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last
instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated.
VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from
power-down. To properly terminate power-down, the reset or external interrupt should not be executed before VCC
is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled
and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 8.
When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power
down exit will be completed when the first input will be released. In this case the higher priority interrupt service
routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction
that put TS80C31X2 into power-down mode.
INT0
INT1
XTAL1
Active phase
Power-down phase
Oscillator restart phase
Active phase
Figure 8. Power-Down Exit Waveform
Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect
the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt,
PD and IDL bits are cleared and idle mode is not entered.
22
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
Table 11. The state of ports during idle and power-down modes
Mode
Program
Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Power Down
External
External
1
0
1
0
Floating
Floating
Port Data
Port Data
Address
Port Data
Port Data
Port Data
Rev. A - Mar. 19, 1999
23
Preliminary
TS80C31X2
6.7 ONCE Mode (ON Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using TS80C31X2 without removing the circuit from
the board. The ONCE mode is invoked by driving certain pins of the TS80C31X2; the following sequence must
be exercised:
●
Pull ALE low while the device is in reset (RST high) and PSEN is high.
●
Hold ALE low as RST is deactivated.
While the TS80C31X2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26.
shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 12. External Pin Status during ONCE Mode
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
XTAL1/2
Weak pull-up
Weak pull-up
Float
Weak pull-up
Weak pull-up
Weak pull-up
Active
24
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
6.8 Power-Off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset.
A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to
the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (See Table 13.). POF is set by hardware when VCC rises
from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type
of reset.
Table 13. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic
7
SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
5
-
4
POF
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
3
GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 00X1 0000b
Not bit addressable
Rev. A - Mar. 19, 1999
25
Preliminary
TS80C31X2
7. Electrical Characteristics
7.1 Absolute Maximum Ratings (1)
Ambiant Temperature Under Bias:
C = commercial
I = industrial
Storage Temperature
Voltage on VCC to VSS
Voltage on Any Pin to VSS
Power Dissipation
0°C to 70°C
-40°C to 85°C
-65°C to + 150°C
-0.5 V to + 7 V
-0.5 V to VCC + 0.5 V
1 W(2)
NOTES
1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions may affect device reliability.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
26
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
7.2 DC Parameters for Standard Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
Table 14. DC Parameters in Standard Voltage
Symbol
Parameter
VIL
Input Low Voltage
VIH
Input High Voltage except XTAL1, RST
VIH1
Input High Voltage, XTAL1, RST
VOL
Output Low Voltage, ports 1, 2, 3 (6)
VOL1
VOH
Min
Typ
Max
Unit
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
0.3
0.45
1.0
V
V
V
IOL = 100 µA(4)
0.3
0.45
1.0
V
V
V
IOL = 200 µA(4)
Output Low Voltage, port 0, ALE, PSEN (6)
Output High Voltage, ports 1, 2, 3
VCC - 0.3
V
V
V
VCC - 0.7
VCC - 1.5
VOH1
Output High Voltage, port 0, ALE, PSEN
VCC - 0.3
V
V
V
VCC - 1.5
RST Pulldown Resistor
50
IOL = 1.6 mA(4)
IOL = 3.5 mA(4)
IOL = 3.2 mA(4)
IOL = 7.0 mA(4)
IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
VCC = 5 V ± 10%
VCC - 0.7
RRST
Test Conditions
IOH = -200 µA
IOH = -3.2 mA
IOH = -7.0 mA
VCC = 5 V ± 10%
90 (5)
200
kΩ
IIL
Logical 0 Input Current ports 1, 2 and 3
-50
µA
Vin = 0.45 V
ILI
Input Leakage Current
±10
µA
0.45 V < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3
-650
µA
Vin = 2.0 V
CIO
Capacitance of I/O Buffer
10
pF
Fc = 1 MHz
TA = 25°C
IPD
Power Down Current
50
µA
2.0 V < VCC < 5.5 V(3)
ICC
Power Supply Current (7)
Freq = 1 MHz
Icc op
Icc idle
Freq = 6 MHz
Icc op
Icc idle
Freq ≥ 12 MHz
Icc op = 1.25 Freq (MHz) + 5 mA
1.8
1
mA
mA
VCC = 5.5 V(1)
10
4
mA
mA
VCC = 5.5 V(2)
Icc idle = 0.36 Freq (MHz) + 2.7 mA
10 (5)
(5)
[email protected] MHz
[email protected]
[email protected]
[email protected] MHz
Rev. A - Mar. 19, 1999
mA
mA
27
Preliminary
TS80C31X2
7.3 DC Parameters for Low Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz.
Table 15. DC Parameters for Low Voltage
Symbol
Parameter
Min
Typ
Max
Unit
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
Test Conditions
VIL
Input Low Voltage
VIH
Input High Voltage except XTAL1, RST
VIH1
Input High Voltage, XTAL1, RST
VOL
Output Low Voltage, ports 1, 2, 3 (6)
0.45
V
IOL = 0.8 mA(4)
VOL1
Output Low Voltage, port 0, ALE, PSEN (6)
0.45
V
IOL = 1.6 mA(4)
VOH
Output High Voltage, ports 1, 2, 3
0.9 VCC
V
IOH = -10 µA
VOH1
Output High Voltage, port 0, ALE, PSEN
0.9 VCC
V
IOH = -40 µA
IIL
Logical 0 Input Current ports 1, 2 and 3
-50
µA
Vin = 0.45 V
ILI
Input Leakage Current
±10
µA
0.45 V < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3
-650
µA
Vin = 2.0 V
200
kΩ
10
pF
Fc = 1 MHz
TA = 25°C
RRST
RST Pulldown Resistor
50
CIO
Capacitance of I/O Buffer
IPD
Power Down Current
TBD (5)
TBD
µA
VCC = 2.0 V to 5.5 V(3)
ICC
Power Supply Current (7)
Active Mode 16MHz
Idle Mode 16MHz
TBD (5)
TBD (5)
TBD
TBD
mA
mA
VCC = 3.3 V(1)
90 (5)
VCC = 3.3 V(2)
NOTES
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 12.), VIL = VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used..
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2
N.C; Port 0 = VCC; EA = RST = VSS (see Figure 10.).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 11.).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is
due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
7. For other values, please contact your sales office.
28
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
VCC
ICC
VCC
VCC
P0
VCC
RST
EA
XTAL2
XTAL1
(NC)
CLOCK
SIGNAL
VSS
All other pins are disconnected.
Figure 9. ICC Test Condition, Active Mode
VCC
ICC
VCC
VCC
P0
RST
EA
XTAL2
XTAL1
VSS
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
Figure 10. ICC Test Condition, Idle Mode
VCC
ICC
VCC
VCC
P0
RST
(NC)
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 11. ICC Test Condition, Power-Down Mode
Rev. A - Mar. 19, 1999
29
Preliminary
TS80C31X2
VCC-0.5V
0.45V
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
0.7VCC
0.2VCC-0.1
Figure 12. Clock Signal Waveform for ICC Tests in Active and Idle Modes
7.4 AC Parameters
7.4.1 Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters,
depending on their positions, stand for the name of a signal or the logical status of that signal. The following is
a list of all the characters and what they stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
TA = 0 to +70°C; VSS = 0 V; VCC = 5 V ± 10%; -M and -V ranges.
TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; -M and -V ranges.
TA = 0 to +70°C; VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range.
TA = -40°C to +85°C; VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range.
(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF.)
Table 16., Table 19. and Table 22. give the description of each AC symbols.
Table 17., Table 20. and Table 23. give for each range the AC parameter.
Table 18., Table 21. and Table 24. give the frequency derating formula of the AC parameter. To calculate each
AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value
in the formula.
Example:
TLLIV in X2 mode for a -V part at 25 MHz:
x= 22
T= 40ns
TLLIV= 2T - x = 2 x 40 - 22 = 58ns
30
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
7.4.2 External Program Memory Characteristics
Table 16. Symbol Description
Symbol
T
Parameter
Oscillator clock period
TLHLL
ALE pulse width
TAVLL
Address Valid to ALE
TLLAX
Address Hold After ALE
TLLIV
ALE to Valid Instruction In
TLLPL
ALE to PSEN
TPLPH
PSEN Pulse Width
TPLIV
PSEN to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction FloatAfter PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instruction In
TPLAZ
PSEN Low to Address Float
Table 17. AC Parameters for Fix Clock
Speed
(see ordering)
-M
-V
Min
Min
T
25
17
50
ns
TLHLL
40
25
60
ns
TAVLL
10
7
20
ns
TLLAX
10
7
20
ns
70
Max
Min
Units
Symbol
TLLIV
Max
-L
45
Max
125
ns
TLLPL
10
7
20
ns
TPLPH
60
45
105
ns
TPLIV
TPXIX
25
0
TPXIZ
TPXAV
25
0
18
18
60
0
12
12
ns
ns
30
30
ns
ns
TAVIV
85
53
145
ns
TPLAZ
10
10
10
ns
Rev. A - Mar. 19, 1999
31
Preliminary
TS80C31X2
Table 18. AC Parameters for a Variable Clock
Symbol
Type
Standard
Clock
X2 Clock
-M
-V
-L
Units
TLHLL
Min
2T-x
T-x
10
8
40
ns
TAVLL
Min
T-x
0.5 T - x
15
10
30
ns
TLLAX
Min
T-x
0.5 T - x
15
10
30
ns
TLLIV
Max
4T-x
2T-x
30
22
75
ns
TLLPL
Min
T-x
0.5 T - x
15
10
30
ns
TPLPH
Min
3T-x
1.5 T - x
15
5
45
ns
TPLIV
Max
3T-x
1.5 T - x
50
25
90
ns
TPXIX
Min
x
x
0
0
0
ns
TPXIZ
Max
T-x
0.5 T - x
7
5
20
ns
TPXAV
Min
T-x
0.5 T - x
7
5
20
ns
TAVIV
Max
5T-x
2.5 T - x
40
30
105
ns
TPLAZ
Max
x
x
10
10
10
ns
7.4.3 External Program Memory Read Cycle
12 TCLCL
TLHLL
TLLIV
ALE
TLLPL
TPLPH
PSEN
TLLAX
TAVLL
PORT 0
INSTR IN
TPLIV
TPLAZ
A0-A7
TPXAV
TPXIZ
TPXIX
INSTR IN
A0-A7
INSTR IN
TAVIV
PORT 2
ADDRESS
OR SFR-P2
ADDRESS A8-A15
ADDRESS A8-A15
Figure 13. External Program Memory Read Cycle
32
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
7.4.4 External Data Memory Characteristics
Table 19. Symbol Description
Symbol
Parameter
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TRLDV
RD to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
TLLDV
ALE to Valid Data In
TAVDV
Address to Valid Data In
TLLWL
ALE to WR or RD
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data set-up to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE high
Rev. A - Mar. 19, 1999
33
Preliminary
TS80C31X2
Table 20. AC Parameters for a Fix Clock
Speed
(see ordering)
-M
-V
Min
TRLRH
105
85
200
ns
TWLWH
105
90
200
ns
TRHDX
Min
100
0
Max
Min
Units
Symbol
TRLDV
Max
-L
60
0
Max
155
0
ns
ns
TRHDZ
15
13
40
ns
TLLDV
160
100
310
ns
TAVDV
165
100
360
ns
60
ns
TLLWL
40
TAVWL
40
27
100
ns
TQVWX
3
0
18
ns
TQVWH
145
90
280
ns
TWHQX
10
7
20
ns
TRLAZ
TWHLH
110
30
0
5
45
65
90
0
5
29
20
34
0
ns
80
ns
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
Table 21. AC Parameters for a Variable Clock
Symbol
Type
Standard
Clock
X2 Clock
-M
-V
-L
Units
TRLRH
Min
6T-x
3T-x
45
15
100
ns
TWLWH
Min
6T-x
3T-x
45
10
100
ns
TRLDV
Max
5T-x
2.5 T - x
25
23
95
ns
TRHDX
Min
x
x
0
0
0
ns
TRHDZ
Max
2T-x
T-x
35
20
60
ns
TLLDV
Max
8T-x
4T -x
40
33
90
ns
TAVDV
Max
9T-x
4.5 T - x
60
50
90
ns
TLLWL
Min
3T-x
1.5 T - x
35
20
60
ns
TLLWL
Max
3T+x
1.5 T + x
35
15
60
ns
TAVWL
Min
4T-x
2T-x
60
40
100
ns
TQVWX
Min
T-x
0.5 T - x
22
17
32
ns
TQVWH
Min
7T-x
3.5 T - x
30
27
70
ns
TWHQX
Min
T-x
0.5 T - x
15
10
30
ns
TRLAZ
Max
x
x
0
0
0
ns
TWHLH
Min
T-x
0.5 T - x
20
12
30
ns
TWHLH
Max
T+x
0.5 T + x
20
12
30
ns
7.4.5 External Data Memory Write Cycle
TWHLH
ALE
PSEN
TLLWL
TWLWH
WR
TLLAX
PORT 0
TQVWX
A0-A7
TQVWH
TWHQX
DATA OUT
TAVWL
PORT 2
ADDRESS
OR SFR-P2
ADDRESS A8-A15 OR SFR P2
Figure 14. External Data Memory Write Cycle
Rev. A - Mar. 19, 1999
35
Preliminary
TS80C31X2
7.4.6 External Data Memory Read Cycle
TWHLH
TLLDV
ALE
PSEN
TLLWL
TRLRH
RD
TLLAX
PORT 0
TRHDZ
TAVDV
TRHDX
A0-A7
DATA IN
TRLAZ
TAVWL
ADDRESS
OR SFR-P2
PORT 2
ADDRESS A8-A15 OR SFR P2
Figure 15. External Data Memory Read Cycle
7.4.7 Serial Port Timing - Shift Register Mode
Table 22. Symbol Description
Symbol
Parameter
TXLXL
Serial port clock cycle time
TQVHX
Output data set-up to clock rising edge
TXHQX
Output data hold after clock rising edge
TXHDX
Input data hold after clock rising edge
TXHDV
Clock rising edge to input data valid
Table 23. AC Parameters for a Fix Clock
Speed
(see ordering)
-M
-V
Symbol
Min
TXLXL
300
200
600
ns
TQVHX
200
117
367
ns
TXHQX
20
13
50
ns
TXHDX
0
0
0
ns
TXHDV
Max
200
Min
Units
-L
Max
Min
117
36
Max
367
ns
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
Table 24. AC Parameters for a Variable Clock
-M
-V
Units
Symbol
Type
Standard
Clock
X2 Clock
-L
TXLXL
Min
12 T
6T
TQVHX
Min
10 T - x
5T-x
50
50
133
ns
TXHQX
Min
2T-x
T-x
30
20
50
ns
TXHDX
Min
x
x
0
0
0
ns
TXHDV
Max
10 T - x
5 T- x
50
50
133
ns
ns
7.4.8 Shift Register Timing Waveforms
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
TXLXL
CLOCK
TXHQX
TQVXH
OUTPUT DATA
0
WRITE to SBUF
TXHDV
INPUT DATA
1
2
3
4
5
6
7
TXHDX
VALID
VALID
VALID
SET TI
VALID
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
Figure 16. Shift Register Timing Waveforms
Rev. A - Mar. 19, 1999
37
Preliminary
TS80C31X2
7.4.9 External Clock Drive Characteristics (XTAL1)
Table 25. AC Parameters
Symbol
Parameter
Min
Max
Units
TCLCL
Oscillator Period
25
ns
TCHCX
High Time
5
ns
TCLCX
Low Time
5
ns
TCLCH
Rise Time
5
ns
TCHCL
Fall Time
5
ns
60
%
TCHCX/TCLCX
Cyclic ratio in X2 mode
40
7.4.10 External Clock Drive Waveforms
VCC-0.5 V
0.45 V
0.7VCC
0.2VCC-0.1 V
TCHCL
TCHCX
TCLCH
TCLCX
TCLCL
Figure 17. External Clock Drive Waveforms
7.4.11 AC Testing Input/Output Waveforms
VCC-0.5 V
INPUT/OUTPUT
0.2VCC+0.9
0.2VCC-0.1
0.45 V
Figure 18. AC Testing Input/Output Waveforms
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement
are made at VIH min for a logic “1” and VIL max for a logic “0”.
7.4.12 Float Waveforms
FLOAT
VOH-0.1 V VLOAD
VOL+0.1 V
VLOAD+0.1 V
VLOAD-0.1 V
Figure 19. Float Waveforms
38
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA.
7.4.13 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
INTERNAL
CLOCK
STATE4
STATE5
STATE6
STATE1
STATE2
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
STATE3
P1
P2
STATE4
P1
P2
STATE5
P1
P2
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
DATA
SAMPLED
PCL OUT
DATA
SAMPLED
FLOAT
P2 (EXT)
PCL OUT
DATA
SAMPLED
PCL OUT
FLOAT
FLOAT
INDICATES ADDRESS TRANSITIONS
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0
DPL OR Rt OUT
FLOAT
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WRITE CYCLE
WR
P0
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
DPL OR Rt OUT
DATA OUT
P2
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION
OLD DATA
P0 PINS SAMPLED
NEW DATA
P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1, P2, P3)
(INCLUDES INT0, INT1, TO, T1)
P1, P2, P3 PINS SAMPLED
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
Figure 20. Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded)
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.
Rev. A - Mar. 19, 1999
39
Preliminary
TS80C31X2
8. Ordering Information
TS
-M
80C31X2
-M:
-V:
-L:
C
R
B
Packages:
A: PDIL 40
B: PLCC 44
C: PQFP F1 (13.9 mm footprint)
E: VQFP 44 (1.4mm)
VCC: 5V +/- 10%
40 MHz, standard mode
20 MHz, X2 mode
VCC: 5V +/- 10%
40 MHz, standard mode
30 MHz, X2 mode
VCC: 2.7 to 5.5 V
30 MHz, standard mode
20 MHz, X2 mode
Conditioning
R: Tape & Reel
D: Dry Pack
B: Tape & Reel and
Dry Pack
Temperature Range
C: Commercial 0 to 70oC
I: Industrial -40 to 85oC
TEMIC Semiconductors
Table 26. Maximum Clock Frequency
Code
-M
-V
-L
Standard Mode, oscillator frequency
Standard Mode, internal frequency
X2 Mode, oscillator frequency
X2 Mode, internal equivalent frequency
40
40
20
40
40
40
30
60
30
30
20
40
40
Unit
MHz
MHz
Rev. A - Mar. 19, 1999
Preliminary