TSOP A JCET Company Thin Small Outline Package HIGHLIGHTS • Body Sizes: 12 x 20mm (48 lead); 14 x 20mm (56 lead) • Body Thickness: 1.0mm • Lead Pitch: 0.50mm • Stacked Die: available between 2 to 4 die • Stacking Options: same size die, staggered, staircase, pyramid • LF Matrix: LD (196 x 40mm, 2 x 8 units) and HD (250 x 70mm, 4 x 10 units) FEATURES DESCRIPTION • Two body sizes available in TSOP type 1 version STATS ChipPAC offers the Thin Small Outline Package (TSOP). Reliability and thin profile are key TSOP attributes using surface mount technology (SMT). TSOP is available in a thermally enhanced version (TSOP-ep), as well as a stacked die version (TSOP-SD). Die stacking is available from 2 to 4 die, with bonding pads on two sides of the die or single-sided bonding pads. • Lead counts: 48 and 56 • Lead pitch: 0.50mm • Wide range of open tool die pad sizes available; custom size available • Moisture sensitivity: JEDEC Level 3 • JEDEC standard compliant • Lead-free (Pb free) and green material sets available • Copper and alloy 42 leadframes available • Die stacking available up to 4 die APPLICATIONS • Memory • RF / Wireless • Logic and Linear • ASIC / Analog • µProcessor / µController • PC Chipset • End applications including portable electronics, memory modules and networking equipment www.cj-elec.com www.statschippac.com STATS ChipPAC uses the latest leadframe technology and state of the art design and simulation tools to achieve optimum electrical and thermal performance. STATS ChipPAC’s state of the art assembly facility and proven materials assure high yield manufacturing and long term reliability. TSOP A JCET Company Thin Small Outline Package RELIABILITY SPECIFICATIONS Single Die Thickness Stacking Die Thickness Gold Wire Lead Finish Marking Packing Options 10-12mils 75µm (3mils) minimum 0.8mils diameter, 99.99% Au Matte Tin Laser JEDEC tray Moisture Sensitivity Level Temperature Cycling Temp/Humidity Test Pressure Cooker Test JEDEC Level 3 -65°C/150°C, 1000 cycles 85°C/85% RH, 1000 hrs 121°C 100% RH, 2 atm, 250 hrs THERMAL PERFORMANCE, θja (°C/W) Package 48LTSOP 48LTSOP Body Size (mm) 12 x 20 12 x 20 Thermal Resistance θja (1.0W, natural convection) 0 60 C/W 0 75 C/W Die Size(mils) 150 x 150 100 x 100 Note: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-5) under natural convection as defined in JESD51.2. ELECTRICAL PERFORMANCE: TSOP 48L Conductor Body Size Lead/Wire Component (mm) (mm) Lead 12 x 20 6.56-7.60 Wire 1.90 TOTALS Resistance (mOhm) 38.0-44.0 114 152-158 Inductance Self (nH) Mutual (nH) 3.49-4.17 1.58 5.07-5.75 2.32-2.63 Capacitance Self (pF) Mutual (pF) 0.69-0.87 0.08 0.77-0.95 0.36-0.39 Note: Results are simulated values at 100MHz. CROSS-SECTIONS PACKAGE CONFIGURATIONS Package Body Size TSOP 12 x 20mm 14 x 20mm Body Thickness Lead Count 1.0mm 1.0mm 48 56 TSOP TSOP SD4 (4+3) TSOP-SD2 (2+0) staircase Corporate Office Global Offices 10 Ang Mo Kio St. 65, #04-058/09 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 USA 510-979-8000 CHINA 86-21-5976-5858 KOREA 82-32-340-3114 SWITZERLAND 41-21-8047-200 The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Pte. Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2016. STATS ChipPAC Pte. Ltd. All rights reserved. Apr 2016