FLGA-SD A JCET Company Fine Pitch Land Grid Array - Stacked Die HIGHLIGHTS •Stacking of die allows for more functionality in an array molded, cost effective, space saving package solution •Available in a variety of package heights including 2.45mm (LFLGA-SD), 1.2mm (TFLGA-SD), 1.0mm (VFLGA-SD), 0.8mm (WFLGA-SD), 0.65mm (UFLGA-SD) and 0.5mm (XFLGA-SD) maximum thickness •Thinner than FBGA •Exposed thermal/mechanical lands available •Back side SMT •2 to 6 layer laminate substrate DESCRIPTION FEATURES • 2 to 8 die stack with spacer capability • Flexible body sizes range from 4mm x 4mm to 12mm x 18mm • Package height at 0.5, 0.65, 0.80, 1.0, 1.2, 1.4, 2.45mm max • Flexible die stacking options (pyramid, same die, etc.) • 0.5mm minimum land pitch, flexible land pattern • Memory, Logic, Analog and RF combinations • JEDEC standard package outlines • Die thinning to 40µm (1.6mils) capability • Low loop wire bonding; reverse and die to die • Up to 2mm die overhang per side • Halogen-free and Low-K wafer compatible BOM • Film spacer capability for decreased die stack thickness • Very thin substrate capability • Capability to integrate discrete passives or integrated passive devices (IPD) • Solder bump capability • Test capability APPLICATIONS • Handheld devices • Wireless RF • Analog • ASIC • Memory • Simple PLDs www.cj-elec.com www.statschippac.com STATS ChipPAC’s chip stack technology offers the flexibility of stacking 2 to 8 die in a single package. Die to die bonding capability enables device and signal integration to improve electrical performance and reduce overall package I/O requirements. Wafer thinning technology, overhang wire bond technology, and the use of spacers between stacked die provide the flexibility to stack almost any desirable configuration of die in one package. This capability uses existing assembly infrastructure, which results in more functional integration with lower overall package cost. The use of the latest packaging materials allows this package to meet JEDEC Moisture Resistance Test Level 2a with Lead-free reflow condition. This is an ideal package for cell phone applications where Digital, Flash, SRAM, PSRAM and Logic are stacked into a single package. FLGA-SD A JCET Company Fine Pitch Land Grid Array - Stacked Die SPECIFICATIONS Die Thickness Gold Wire Pd/Cu Wire Ag Wire Mold Cap Thickness Marking Packing Options RELIABILITY Moisture Sensitivity Level Temperature Cycling 50-300µm (3-12mils) 15-30µm (0.6/0.8/0.9/1.0/1.2mils) diameter 15-25µm (0.6/0.7/0.8/1.0mils) diameter 18-25µm (0.7/0.8/1.0mils) diameter 0.25 - 1.22mm Laser JEDEC tray/tape and reel High Temp Storage Temperature/Humidity Test Unbiased HAST JEDEC Level 2A, 260°C Reflow Condition C (–65°C to 150°C), 1000 cycles 150°C, 1000 hrs 85°C/85% RH, 1000 hrs 130°C/85% RH/2 atm, 96 hrs ELECTRICAL PERFORMANCE Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific package design to provide the best prediction of electrical behavior. First order approximations can be calculated using parasitics per unit length for the constituents of the signal path. Data below is for a frequency of 100MHz and assumes 1.0 mil gold bonding wire. Conductor Component Wire Net (2L) Length (mm) 2 2 - 7 Resistance (mOhms) 120 25 -110 Inductance (nH) 1.65 1.10 - 4.35 Inductance Mutual (nH) 0.45 - 0.85 0.25 - 2.27 Capacitance (pF) 0.10 0.20 - 0.90 Capacitance Mutual (pF) 0.01 - 0.02 0.05 - 0.41 4 - 0 145 - 230 2.75 - 6.00 0.70 - 3.12 0.30 - 1.00 0.06 - 0.43 2 120 1.65 0.45 - 0.85 0.10 0.01 - 0.02 Total (2L) Wire Net (4L) 2 - 7 25 - 110 0.70 - 2.95 0.17 - 1.57 0.30 - 1.05 0.05 - 0.41 Total (4L) 4 - 9 145 - 230 2.35 - 4.60 0.62 - 2.42 0.40 - 1.15 0.06 - 0.43 Note: Net = Total Trace Length + Via CROSS-SECTION PACKAGE CONFIGURATIONS Body Sizes Terminal Count Terminal Pitch FLGA-SD Typical Package Thickness 4x4 to 12x18mm 8 to 200 0.5 to 0.8mm LFLGA-SD: 2.45mm max. TFLGA-SD: 1.2mm VFLGA-SD: 1.0mm max. WFLGA-SD: 0.8mm max. UFLGA-SD: 0.65mm max. XFLGA-SD: 0.5mm max. d1 controller d2 R Corporate Office Global Offices CAP LED connector 10 Ang Mo Kio St. 65, #04-08/09 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 USA 510-979-8000 CHINA 86-21-5976-5858 KOREA 82-32-340-3114 SWITZERLAND 41-21-8047-200 The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Pte. Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2016. STATS ChipPAC Pte. Ltd. All rights reserved. Apr 2016