IDT74LVC373A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O IDT74LVC373A DESCRIPTION: FEATURES: The LVC373A Octal transparent D-type latch is built using advanced dual metal CMOS technology. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high- impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the highimpedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment. • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range µ W typ. static) • CMOS power levels (0.4µ • Rail-to-rail output swing for increased noise margin • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SOIC, SSOP, QSOP, and TSSOP packages DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM OE 1 LE 11 1D 3 C1 2 1D 1Q TO SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE OCTOBER 1999 1 © 1999 Integrated Device Technology, Inc. DSC-4640/1 IDT74LVC373A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA OE 1 20 VCC 1Q 2 19 8Q IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 –50 mA 1D 3 18 8D mA 4 17 7D Continuous Current through each VCC or GND ±100 2D ICC ISS 2Q 5 16 7Q 3Q 6 15 6Q 3D 7 14 6D 4D 8 13 5D 4Q 9 12 5Q 10 11 LE GND NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol SOIC/ SSOP/ QSOP/ TSSOP TOP VIEW Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 5.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names OE Description Output Enable Inputs (Active LOW) LE Latch Enable Input xD Data Inputs xQ 3-State Data Outputs FUNCTION TABLE (EACH LATCH)(1) Inputs xD LE Outputs OE xQ H H L H L H L L X L L Q(2) X X H Z NOTES: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established. 2 IDT74LVC373A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV µA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 µA IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit VCC – 0.2 — V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74LVC373A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Latch Outputs enabled CPD Power Dissipation Capacitance per Latch Outputs disabled Test Conditions Typical Unit CL = 0pF, f = 10Mhz 46 pF 3 SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol Parameter tPLH Propagation Delay tPHL xD to xQ tPLH Propagation Delay tPHL LE to xQ tPZH Output Enable Time tPZL OE to xQ tPHZ Output Disable Time tPLZ OE to xQ VCC = 3.3V ± 0.3V Min. Max. Min. Max. Unit — 7.8 1.5 6.8 ns — 8.2 2 7.6 ns — 8.7 1.5 7.7 ns — 7.6 1.5 7 ns 3.3 — 3.3 — ns 2 — 2 — ns tW Pulse Duration LE HIGH tSU Set-up Time, data before LE↓ tH Hold Time, data after LE↓ 1.5 — 1.5 — ns Output Skew(2) — — — 1 ns tSK(o) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVC373A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF VIN Pulse (1, 2) Generator GND tPZL OUTPUT SWITCH NORMALLY VLOAD LOW tPZH OUTPUT SWITCH NORMALLY GND HIGH 500Ω LVC Link Switch DATA INPUT VLOAD TIMING INPUT Disable High Enable High GND ASYNCHRONOUS CONTROL All Other Tests Open SYNCHRONOUS CONTROL VIH VT 0V tPHL1 tSK (x) tSK (x) VOH VOH-VHZ 0V VT 0V tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V tH tREM tSU tH Set-up, Hold, and Release Times VOH VT VOL LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE tPHL2 VT Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tPHZ LVC Link VOH VT VOL OUTPUT 2 VLOAD/2 VOL+VLZ VOL Enable and Disable Times SWITCH POSITION Open Drain Disable Low Enable Low tPLZ VLOAD/2 VT NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test VIH VT 0V LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tPLH2 DISABLE ENABLE Test Circuit for All Outputs OUTPUT 1 VIH VT 0V CONTROL INPUT CL tPLH1 tPHL Propagation Delay D.U.T. INPUT tPLH LVC Link VOUT RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 LVC Link IDT74LVC373A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION X LVC IDT XX XXXX XX Bus-Hold Device Type Package Temp. Range SO PY Q PG Small Outline IC (gull wing) Shrink Small Outline Package Quarter Size Small Outline Package Thin Shrink Small Outline Package 373A Octal Transparent D-Type Latch with 3-State Outputs, ±24mA Blank No Bus-hold 74 –40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459