SMP1331_085LF_203591B.pdf

DATA SHEET
SMP1331-085LF: 50 W Surface Mount Shunt Connected
PIN Diode
Applications
Anode
(Pin 3)
Anode
(Pin 1)
 Low-loss, high-power switches
 Low distortion attenuators
Features
 Low-thermal resistance: 28 °C/W
Cathode
(Pin 2, Exposed Paddle)
 Suitable for 50 W Continuous Wave T/R switches
 Low capacitance: 0.35 pF
Figure 1. SMP1331-085LF Block Diagram
 Low distortion performance
 QFN (3-pin, 2 × 2 mm) package
(MSL1, 260 C per JEDEC J-STD-020)
Skyworks Green™ products are compliant with
all applicable legislation and are halogen-free.
For additional information, refer to Skyworks
Definition of Green™, document number
SQ04-0074.
Description
The SMP1331-085LF is a surface mountable, low capacitance
silicon PIN diode designed as a shunt connected PIN diode for
high power, high volume switch and attenuator applications from
10 MHz to beyond 6 GHz.
Maximum resistance at 100 mA is 0.5  and typical capacitance
at 30 V is 0.35 pF. The combination of low junction capacitance,
low parasitic inductance, low thermal resistance, and nominal
30 m I-region width, makes the SMP1331-085LF useful in large
signal switches and attenuator applications.
The device has a 2.5 W dissipation power rating, making it
capable of handling more than 50 W @ 85 °C Continuous Wave
(CW) in a shunt-connected transmit/receive (T/R) switch.
Design information for high power switches may be found in the
Skyworks Application Note, Design With PIN Diodes (document
number 200312).
A block diagram of the SMP1331-085LF is shown in Figure 1.
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DATA SHEET • SMP1331-085LF: 50 W SURFACE MOUNT SHUNT CONNECTED PIN DIODE
Electrical and Mechanical Specifications
Typical DC performance characteristics of the SMP1331-085LF
are illustrated in Figures 2 and 3.
The absolute maximum ratings of the SMP1331-085LF are
provided in Table 1. Electrical specifications are provided in
Table 2.
Table 1. SMP1331-085LF Absolute Maximum Ratings
Maximum
Units
Reverse voltage
Parameter
VR
Symbol
Minimum
200
V
Forward current @ 25 °C
IF
200
mA
CW power dissipation @ 85 °C
PD
2.5
W
25
W
Peak pulse power dissipation @ 85 °C (10% duty cycle)
TSTG
–65
+200
C
Operating temperature
TA
–40
+150
C
Electrostatic discharge:
ESD
1100
1000
400
V
V
V
Storage temperature
Charged Device Model (CDM), Class 4
Human Body Model (HBM), Class 1C
Machine Model (MM), Class C
Note:
Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other
parameters set at or below their nominal value. Exceeding any of the limits listed here may result in permanent damage to the device.
CAUTION: Although this device is designed to be as robust as possible, electrostatic discharge (ESD) can damage this device. This device
must be protected at all times from ESD. Static charges may easily produce potentials of several kilovolts on the human body
or equipment, which can discharge without detection. Industry-standard ESD precautions should be used at all times.
Table 2. SMP1331-085LF Electrical Specifications (Note 1)
(TA = +25 C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Reverse current
IR
VR = 200 V
Capacitance
CT
f = 1 MHz, VR = –30 V
Resistance
RS
f = 100 MHz:
IF = 1.0 mA
IF = 10.0 mA
IF = 100 mA
Forward voltage
Min
Typical
Max
Units
10
μA
0.35
pF
14.5
1.7
0.5



V
VF
IF = 10 mA
0.8
Carrier lifetime
TL
IF = 10 mA
600
ns
I region width
W
30
m
CW thermal resistance
JC
Junction-to-case
28
C/W
Peak thermal resistance
P
Single 1 μs pulse width,
junction-to-case (10% duty cycle)
2.8
C/W
Note 1: Performance is guaranteed only under the conditions listed in this table.
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DATA SHEET • SMP1331-085LF: 50 W SURFACE MOUNT SHUNT CONNECTED PIN DIODE
Typical DC Performance Characteristics
(TA = 25 C, Unless Otherwise Noted)
1.0
100.0
0.8
Forward Voltage (V)
Series Resistance (Ω)
0.9
10.0
1.0
0.7
0.6
0.5
0.4
1
10
100
Forward Current (mA)
Figure 2. Series Resistance vs Current @ 100 MHz
High-Power Switch Design Application
The SMP1331-085LF PIN diode is designed for shunt applications
such as reflective switches or shunt-diode attenuator circuits.
Compared to other surface mount packages, the design of the
QFN package produces lower thermal resistance and also reduces
the effects of the parasitic inductance of the anode bond wires.
A cross-sectional view of the SMP1331-085LF PIN diode is shown
in Figure 4. The cathode of the die is soldered directly to the top
of the exposed paddle. This paddle is composed of copper, so its
thermal resistance is very low.
The copper ground paddle minimizes the total thermal resistance
between the I layer, which is the location where most heat is
generated under normal operation, and the surface to which the
package is mounted. Minimal thermal resistance between the I
layer and the external environment minimizes junction
temperature.
The electrically equivalent circuit of the SMP1331-085LF PIN
diode is shown in Figure 5. The inductances of pins 1 and 2, as
well as the inductances of the bond wires are in series with the
input and output transmission lines of the external circuit rather
than the portion of the circuit that contains the shunt PIN diode.
0.2
0.1
ts613
0.1
0.1
ts612
0.3
1
10
100
Forward Current (mA)
Figure 3. Forward Voltage vs Forward Current
The effects of these parasitic series inductances are negligible,
since they add a very small insertion loss to the shunt PIN but
have no effect on the isolation that the diode produces when it is
forward biased.
A cross section of the suggested printed circuit board design is
shown in Figure 6. The via shown in this view is critical, both for
electrical performance and for thermal performance. It is
recommended that several vias should be placed under the entire
footprint of the exposed paddle (pin 2) to minimize both electrical
inductance to the system ground and thermal resistance to the
system heat sink.
A high-power switch has been designed and tested. This circuit is
shown in Figure 7, and Table 3 lists the Evaluation Board Bill of
Materials for the circuit.
Typical RF performance of the SMP1331-087LF using the circuit
shown in Figure 7 is summarized in Table 3 and illustrated in
Figures 8 through 10.
An assembly drawing for the Evaluation Board is shown in
Figure 11. The layer detail physical characteristics are provided in
Figure 12.
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DATA SHEET • SMP1331-085LF: 50 W SURFACE MOUNT SHUNT CONNECTED PIN DIODE
Bond Wire
(2 Places)
Encapsulated
Epoxy
SMP1331-085LF Die
Anode
(Pin 1)
Cathode
(Pin 2)
Anode
(Pin 3)
Not to scale
Y2094
Figure 4. Cross-Sectional View of the SMP1331-085LF
LSERIES
LSERIES
Pin 3
Pin 1
CPKG
CPKG
SMP1331-085LF
Die
LPADDLE
Pin 2
Y2095
Figure 5. SMP1331-085LF Electrically Equivalent Circuit
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DATA SHEET • SMP1331-085LF: 50 W SURFACE MOUNT SHUNT CONNECTED PIN DIODE
SMP1331-085LF
Thermal Via
Y2096
Figure 6. Cross-Sectional View of Suggested Printed Circuit Board
IF = 50 mA
VR = –30 V
OR
DC
100 pF
22 nH
100 pF
100 pF
50 Ω
Term
50 Ω
Term
SMP1331-085LF
ts614
Figure 7. High-Power Switch Design
Table 3. Evaluation Board Bill of Materials for EN33-D515-001_V4
Component
Value
Size
QTY
Manufacturer
Mfg. Part Number
Characteristics
C
100 pF
0402
3
Murata
GRM1555C1H101JZ01
5% C0G 50 V
L
22 nH
0402
1
Taiyo Yuden
HK100522NJ-T
5% 300 mA SRF 1.9 GHz
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DATA SHEET • SMP1331-085LF: 50 W SURFACE MOUNT SHUNT CONNECTED PIN DIODE
Table 4. Typical RF Performance Characteristics @ 25 °C, f = 2.6 GHz
(TA = +25 C, Characteristic Impedance [ZO] = 50 , EVB Optimized with Bias Circuit, Unless Otherwise Noted)
Parameter
Symbol
Test Conditions
Typical
Units
Insertion loss
IL
VR = −30 V
−0.18
dB
Return loss
RL
VR = −30 V
−18.7
dB
Isolation
ISO
IF = 50 mA
29.8
dB
Max power
PMAX
VR = −30 V
47
dBm
Typical RF Performance Characteristics
(TOP = +25 °C, Characteristic Impedance [ZO] = 50 Ω, EVB Optimized with Bias Circuit, Unless
Otherwise Noted)
+10
0
–10
–10
|S-Parameters| (dB)
–20
–30
–40
S11
S21
–30
–40
S11
S21
–50
ts615
–50
–20
–60
0
1
2
3
4
5
ts616
|S-Parameters| (dB)
0
–60
6
0
1
2
Frequency (GHz)
3
4
Figure 8. S-Parameter Magnitude vs Frequency, IF = 50 mA
Figure 9. S-Parameter Magnitude vs Frequency, VR = −30 V
0
–0.05
–0.15
–0.2
VR = –5 V
–0.3
VR = –10 V
VR = –20 V
–0.35
VR = –30 V
–0.4
15
ts617
Insertion Loss (dB)
–0.1
–0.25
20
25
30
35
40
45
50
CW Power In (dBm)
Figure 10. Insertion Loss vs CW Power In at Different VR, f = 2.6 GHz
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5
Frequency (GHz)
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DATA SHEET • SMP1331-085LF: 50 W SURFACE MOUNT SHUNT CONNECTED PIN DIODE
ts618
Figure 11. Evaluation Board Assembly Diagram
Cross Section
Name
Thickness (in)
Material
Top Soldermask
L1
(0.0028)
Cu foil
0.012 ± 0.0006
Rogers RO4003C Core
L2
(0.0014)
Cu foil
Laminate
(Note 1)
FR4 Prepreg
L3
(0.0014)
Cu foil
0.010 ± 0.0006
FR4 Core
(0.0028)
Cu foil
Laminate
Laminate
L4
Bottom Soldermask
Note 1: Adjust this thickness to meet total thickness goal of 0.062 ± 0.005 inches.
S2531
Figure 12. Evaluation Board Layer Detail Physical Characteristics
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DATA SHEET • SMP1331-085LF: 50 W SURFACE MOUNT SHUNT CONNECTED PIN DIODE
Package Dimensions
Package and Handling Information
The PCB layout footprint for the SMP1331-085LF is shown in
Figure 13. Typical part markings are shown in Figure 14. Package
dimensions for the 3-pin QFN are provided in Figure 15, and
Figure 16 provides the tape and reel dimensions.
Instructions on the shipping container label regarding exposure to
moisture after the container seal is broken must be followed.
Otherwise, problems related to moisture absorption may occur
when the part is subjected to high temperature during solder
assembly.
The SMP1331-085LF is rated to Moisture Sensitivity Level 1
(MSL1) at 260 C. It can be used for lead or lead-free soldering.
For additional information, refer to the Skyworks Application Note,
Solder Reflow Information, document number 200164.
Care must be taken when attaching this product, whether it is
done manually or in a production solder reflow environment.
Production quantities of this product are shipped in a standard
tape and reel format.
2X 0.60
Part Outline
2X 0.55
Exposed Soldering
Area Typ.
2X 0.27
Pin 3
2X 0.85
Pin 1
Pin 2
R0.20
2X 0.25
S2923
Figure 13. SMP1331-085LF PCB Layout Footprint
RJ
Skyworks
Part Number
3
1
Orientation
Indicator
3
1
2
ts619
Figure 14. Typical Part Markings
(Top View)
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DATA SHEET • SMP1331-085LF: 50 W SURFACE MOUNT SHUNT CONNECTED PIN DIODE
0.5 ± 0.15
2 ± 0.2
Exposed Pad
Detail B
2 ± 0.2
1.7 ± 0.15
1
3
2
0.90 ± 0.1
Orientation
Indicator
Top View
Side View
Bottom View
1
3
0.4 ± 0.1
2
0.27 ± 0.15
Detail B
All dimensions in millimeters
S1632
Figure 15. SMP1331-085LF QFN Package Dimension Drawing
∅1.50+ 0.10/–0.00
0.30 ± 0.05 (T)
Pin #1
4.00 ± 0.10
2.00 ± 0.05
4.00 (see Note 4)
1.75 ± 0.10
2.30 (Bo)
A
B
1.00 (Ko)
2.30 (Ao)
8.00 +0.30/–0.10
A
3.50 ± 0.05
B
∅1.00 Min.
R0.30 Typ.
B
Notes:
1. Carrier tape: black conductive polystyrene.
2. Cover tape material: transparent conductive HSA.
3. Cover tape size: 5.40 mm width.
4. Ten sprocket hole pitch cumulative tolerance = ±0.20 mm.
5. ESD surface resistivity is ≤1 x 108 Ohms/square per EIA, JEDEC
tape and reel specification.
6. Ao and Bo measurement point to be 0.30 mm from bottom pocket.
7. All measurements are in millimeters.
A
S1601
Figure 16. SMP1331-085LF Tape and Reel Dimensions
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DATA SHEET • SMP1331-085LF: 50 W SURFACE MOUNT SHUNT CONNECTED PIN DIODE
Ordering Information
Model Name
SMP1331-085LF: Surface Mount PIN Diode
Manufacturing Part Number
SMP1331-085LF
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