ICS844071 FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR General Description Features The ICS844071 is a Serial ATA (SATA)/Serial Attached SCSI (SAS) Clock Generator and a HiPerClockS™ member of the HiPerClocksTM family of high performance devices from IDT. The ICS844071 uses an 18pF parallel resonant crystal over the range of 20.833MHz - 28.3MHz. For SATA/SAS applications, a 25MHz crystal is used and either 75MHz or 150MHz may be selected with the FREQ_SEL pin. The ICS844071 has excellent <1ps phase jitter performance, over the 900kHz - 7.5MHz integration range. The ICS844071 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • • One differential LVDS output • • • Output frequency range: 62.5MHz – 170MHz • • • Full 3.3V or 2.5V operating supply ICS Crystal oscillator interface, 18pF parallel resonant crystal (20.833MHz – 28.3MHz) VCO range: 500MHz – 680MHz RMS phase jitter at 150MHz, using a 25MHz crystal (900kHz – 7.5MHz): 0.45ps (typical) 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Table 1. Common Configuration Table Inputs Crystal Frequency (MHz) FREQ_SEL M N Multiplication Value M/N Output Frequency (MHz) 25 0 24 4 6 150 25 1 24 8 3 75 26.041666 0 24 4 6 156.25 26.041666 1 24 8 3 78.125 26.5625 0 24 4 6 159.375 26.5625 1 24 8 3 79.675 Pin Assignment Block Diagram FREQ_SEL VDD GND XTAL_OUT XTAL_IN Pullup XTAL_IN OSC XTAL_OUT Phase Detector VCO 500MHz - 680MHz FREQ_SEL N 0 ÷4 1 (Default) ÷8 M = ÷24 (fixed) IDT™ / ICS™ LVDS CLOCK GENERATOR 1 Q nQ 1 8 2 3 4 7 6 5 VDD Q nQ FREQ_SEL ICS844071 8 Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Table 1. Pin Descriptions Number Name Type Description 1 VDDA Power Analog supply pin. 2 GND Power Power supply ground. 3, 4 XTAL_OUT XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 5 FREQ_SEL Input 6, 7 nQ, Q Output Differential output pair. LVDS interface levels. 8 VDD Power Core supply pin. Pullup Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to intenal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ IDT™ / ICS™ LVDS CLOCK GENERATOR Test Conditions Minimum 2 Typical Maximum Units ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characterisitcs is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VDD = 3.3V ± 10%, TA = 0°C to 70°C Symbol Parameter VDD Core Supply Voltage VDDA Analog Supply Voltage IDD IDDA Test Conditions Minimum Typical Maximum Units 2.97 3.3 3.63 V VDD – 0.12 3.3 3.63 V Power Supply Current 135 mA Power Supply Current 12 mA Table 3B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Core Supply Voltage VDDA Analog Supply Voltage IDD IDDA Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V VDD – 0.12 2.5 2.625 V Power Supply Current 120 mA Power Supply Current 12 mA Maximum Units Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 10% or 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VDD = VIN = 3.63V or 2.625V IIL Input Low Current VDD = 3.63V or 2.625V, VIN = 0V IDT™ / ICS™ LVDS CLOCK GENERATOR Test Conditions Minimum VDD = 3.3V 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 5 µA 3 -150 Typical µA ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Table 3D. LVDS DC Characteristics, VDD = 3.3V ± 10%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 275 365 455 mV 50 mV 1.55 V 50 mV 1.125 1.3 Table 3E. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 205 335 465 mV 50 mV 1.48 V 50 mV 0.89 1.2 Table 4. Crystal Characteristics Parameter Test Conditions Minimum Maximum Units 28.3 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Mode of Oscillation Fundamental Frequency IDT™ / ICS™ LVDS CLOCK GENERATOR Typical 20.833 4 ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR AC Electrical Characteristics Table 5A. AC Characteristics, VDD = 3.3V ± 10%, TA = 0°C to 70° Parameter Symbol fOUT Output Frequency tjit(Ø) RMS Phase Jitter, Random; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum 62.5 170 Units MHz 150MHz, Integration Range: 900kHz – 7.5MHz 0.45 ps 75MHz, Integration Range: 900kHz – 7.5MHz 0.46 ps 20% to 80% 150 400 ps 48 52 % NOTE 1: Please refer to Phase Noise Plots. Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70° Parameter Symbol fOUT Output Frequency tjit(Ø) RMS Phase Jitter, Random; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum 62.5 170 Units MHz 150MHz, Integration Range: 900kHz – 7.5MHz 0.56 ps 75MHz, Integration Range: 900kHz – 7.5MHz 0.60 ps 20% to 80% 150 400 ps 48 52 % NOTE 1: Please refer to Phase Noise Plots. IDT™ / ICS™ LVDS CLOCK GENERATOR 5 ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Typical Phase Noise at 150MHz (3.3V) 0 -10 150MHz RMS Phase Jitter (Random) 900kHz to 7.5MHz = 0.45ps (typical) -20 -30 -40 -50 -60 dBc Hz -80 Noise Power -70 -90 -100 ➝ -110 -120 Raw Phase Noise Data -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz) IDT™ / ICS™ LVDS CLOCK GENERATOR 6 ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Parameter Measurement Information SCOPE VDD 3.3V±10% POWER SUPPLY + Float GND – SCOPE Qx VDDA 2.5V±5% POWER SUPPLY + Float GND – LVDS Qx VDD VDDA nQx LVDS nQx - - 3.3V LVDS Output Load AC Test Circuit 2.5V LVDS Output Load AC Test Circuit Phase Noise Plot Noise Power nQ Q t PW Phase Noise Mask t odc = f1 Offset Frequency PERIOD t PW x 100% t PERIOD f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS Phase Jitter Output Duty Cycle/Pulse Width/Period VDD out 80% VOD Clock Outputs DC Input LVDS ➤ 80% 20% 20% tR tF out ➤ VOS/∆ VOS ➤ Offset Voltage Setup Output Rise/Fall Time IDT™ / ICS™ LVDS CLOCK GENERATOR 7 ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Parameter Measurement Information, continued VDD LVDS 100 ➤ VOD/∆ VOD out ➤ DC Input ➤ out Differential Output Voltage Setup Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS44071 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a 0.01µF bypass capacitor should be connected to each VDDA pin. 3.3V or 2.5V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering IDT™ / ICS™ LVDS CLOCK GENERATOR 8 ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Crystal Input Interface The ICS844071 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 33p X1 18pF Parallel Crystal XTAL_OUT C2 22p Figure 2. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 3. General Disgram for LVCMOS Driver to XTAL Input Interface IDT™ / ICS™ LVDS CLOCK GENERATOR 9 ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR 3.3V, 2.5V LVDS Driver Termination A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V or 2.5V VDD 50Ω LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 4. Tyical LVDS Driver Termination IDT™ / ICS™ LVDS CLOCK GENERATOR 10 ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS844071. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844071 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.63V * (135mA + 12mA) = 533.61mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.533W * 90.5°C/W = 118.3°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ LVDS CLOCK GENERATOR 0 1 2.5 101.7°C/W 90.5 89.8 11 ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Reliability Information Table 7. θJA vs. Air Flow Table for a 8 Lead TSSOP θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5 89.8 Transistor Count The transistor count for ICS844071 is: 2533 Package Outline and Package Dimension Package Outline - G Suffix for 8 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ LVDS CLOCK GENERATOR 12 ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Ordering Information Table 8. Ordering Information Part/Order Number ICS844071AG ICS844071AGT ICS844071AGLF ICS844071AGLFT Marking 4071A 4071A 071AL 071AL Package 8 Lead TSSOP 8 Lead TSSOP “Lead-Free” 8 Lead TSSOP “Lead-Free” 8 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVDS CLOCK GENERATOR 13 ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Revision History Sheet Rev Table Page A T8 9 13 Description of Change Date Added LVCMOS to XTAL Interface section. Ordering Information Table - added lead-free marking. Updated datasheet format. IDT™ / ICS™ LVDS CLOCK GENERATOR 14 9/26/07 ICS844071AG SEPTEMBER 26, 2007 ICS844071 FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA