201912B.pdf

DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
General Description
Features
The AAT4712 is a programmed, current limited P-channel
MOSFET power switch designed for high-side load-switching applications for SSD memory buffer saving solutions.
With the programmed current limit, the AAT4712 ensures
that the power ratings of the host are not exceeded and
balances the system load and supercap charging current
automatically to provide enough system load current in
top-priority. The integrated discharge path control assures
that the system load can still be supported in the short
term when the input power has not fully charged the
supercap. The current limit is programmed by an external
resistor allowing ±10% accuracy at room temperature.
•VCC Range: 2.5V – 5.5V
• Input Current Limits:
▪ 150mA - 2400mA
▪ ±10% Current Accuracy at 2A Input Current Limit
Setting
•Low Quiescent Current:
▪ 70µA Typical (VCC Input)
▪ 12µA Typical (OUT Input)
• Under-Voltage Lockout
• Integrated Discharge Path for SYS (to System Load)
from VCC Input or OUT Input (Connect to Supercap)
• Maximum 100mΩ RDS(ON) from OUT to SYS at 5V VCC
• Reverse Blocking Protection
• Power Loop Current Reduction
• Over-Temperature Protection
• SYS Short Circuit Protection
• Input Power Good Detect Threshold Setting (ADJ)
• Input Power Good Indicate (POK)
• Supercap Charge Ready (RDY) Output
• Temperature Range: -40 to 85°C
• 16-Pin TDFN34 Package
The AAT4712 integrates discharge path for SYS (to
system load) from VCC input or OUT input (connect to
supercap). The low RDS(ON) from OUT to SYS prolongs the
supercap backup time when VCC drops below a threshold
voltage which is programmed by an external resistor
from ADJ to ground.
The AAT4712 incorporates a POK function which can
indicate system input power good. An ADJ pin is provided with the addition of an external resistor for setting
the input power good detect threshold. The AAT4712
also incorporates a supercap charge ready (RDY) indicate
function. The quiescent supply current is typically a low
70µA from the discharge path of VCC to SYS.
Applications
•SSD
The AAT4712 is available in a 16-pin TDFN34 package
and is specified over a -40 to 85°C temperature range.
Typical Application
VIO
VSYS
VCC
2.5V - 5.5V
VCC
ADJ
CIN
10µF
SYS
AAT4712
ISET
RADJ
RDY
RDY
POK
POK
OUT
RSET
GND
CSYS
10µF
Super
Capacitor
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DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Pin Descriptions
Pin #
Symbol
1
RDY
2
ISET
3
4, 5, 6, 7, 8
9, 10, 11
12, 13
14
15
16
N/C
SYS
OUT
VCC
ADJ
GND
POK
Function
Supercap charge ready output, initiated when the capacitor is 98% charged. Open drain, active high.
Input current-limit set input. A resistor from ISET to ground is necessary and sets the maximum current limit for the switch. The current limit can be programmed from 150mA to 2000mA.
No connect.
System power output supplied from the VCC input or OUT input.
Connect to super capacitor from OUT to GND.
Input pins to the P-channel MOSFET source. Connect a 10µF capacitor from VCC to GND.
Input power good detect threshold. An internal 50kΩ resistor is integrated between ADJ and VCC.
Device ground connection.
Input power good indicator. Push pull, active high.
Pin Configuration
TDFN34-16
(Top View)
RDY
ISET
N/C
SYS
SYS
SYS
SYS
SYS
2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
POK
GND
ADJ
VCC
VCC
OUT
OUT
OUT
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DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Absolute Maximum Ratings1
Symbol
VP
VRDY, VPOK , VADJ
VISET, VSYS
IMAX
TJ
TSTG
TLEAD
Description
VCC, OUT to GND
RDY, POK, ADJ to GND
ISET, SYS to GND
Maximum Continuous Switch Current
Operating Junction Temperature Range
Storage Temperature
Maximum Soldering Temperature (at Leads)
Value
Units
-0.3 to 6
-0.3 to VP + 0.3
-0.3 to VP + 0.3
2.5
-40 to 150
-40 to 150
300
V
V
V
A
°C
°C
°C
Value
Units
50
2
°C/W
W
Thermal Characteristics2
Symbol
ΘJA
PD
Description
Maximum Thermal Resistance3
Maximum Power Dissipation3
1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions
specified is not implied. Only one Absolute Maximum Rating should be applied at any one time.
2. Mounted on a FR4 board.
3. Derate 50mW/°C above 25°C.
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DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Electrical Characteristics1
VCC = 2.5V to 5.5V, TA = -40°C to 85°C unless otherwise noted. Typical values are at TA = 25°C
Symbol
VCC
IQ
Description
IOUT_OP
Normal Operation Voltage
VCC Quiescent Current
OUT Operating Current
VUVLO_VCC
VCC Under-Voltage Lockout
VUVLO_OUT
OUT Under-Voltage Lockout
RDS(ON)_SWA
VCC to SYS On-Resistance
RDS(ON)_SWB
VCC to OUT On-Resistance
RDS(ON)_SWC
ILIMHACC
ILIM(MIN)
TRESP
TDEL(OFF)
OUT to SYS On-Resistance
Input High Current Limit Accuracy
Minimum Input Current Limit
Current Limit Response Time
Turn-Off Delay Time
TSW
OUT to SYS Switch Turn On Response Time
VADJ
ADJ Pin Voltage with Trigger Comparator
TDETECT
ADJ Pin Detect Delay Time
VPOK(L)
Output Low Voltage
VPOK(H)
Conditions
Min
Typ
2.5
IOUT = 0, No Load at SYS Pin
VOUT = 5V, VCC = GND, No Load at SYS Pin
Falling Edge
Hysteresis
Falling Edge
Hysteresis
VCC = 5V, RSET = 1.24MΩ, ILOAD = 600mA
VCC = 3.3V, RSET = 1.24MΩ, ILOAD = 600mA
VCC = 5V, RSET = 1.24MΩ, ILOAD = 600mA
VCC = 3.3V, RSET = 1.24MΩ, ILOAD = 600mA
VOUT = 3V ~ 5V
RSET = 1.24MΩ, TA = 25°C
70
12
2.1
150
1.8
250
50
65
140
160
1800
VCC = 5V, RSET = 1.24MΩ
VCC = 5V
VCC Voltage Step-Down Signal from 5V to
4.5V
ADJ Voltage Step Down Signal from 1.3V
to 1.1V
ADJ ≤ 1.2V
Output High Voltage
ADJ > 1.2V
VRDY
Supercap Charge Ready Trip Threshold
VOUT Rising, TA = 25°C
VRDYSYS
VRDY(L)
OTMP
THYS
Supercap Charge Ready Hysteresis
RDY Output Low Voltage
Shutdown Temperature
Over-Temperature Shutdown Hysteresis
2000
150
2
0.4
Max
Units
5.5
120
30
2.4
V
µA
µA
V
mV
V
mV
2
100
120
300
320
100
2200
10
mΩ
mΩ
mΩ
mA
mA
µs
µs
6
µs
1.2
V
2
µs
0.4
0.8
VCC
V
V
98
200
RDY Pin Sinks 1mA
0.4
150
15
% of
VCC
mV
V
°C
°C
1. The AAT4712 is guaranteed to meet performance specifications over the -40°C to 85°C operating temperature range and is assured by design, characterization and correlation
with statistical process controls.
4
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DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Typical Characteristics
VOUT Quiescent Current vs. Temperature
90
25
80
20
70
15
IQ (µA)
IQ (µA)
VCC Quiescent Current vs. Temperature
60
VCC = 5.5V
VCC = 5.0V
VCC = 3.0V
VCC = 2.5V
50
40
-40
-15
10
35
10
5
60
0
-40
85
Temperature (°C)
2.26
2.12
2.22
2.06
VUVLO_OUT (V)
VUVLO_VCC (V)
2.18
2.18
2.14
2.10
2.06
10
35
60
1.88
1.82
1.64
-40
RDS(ON)_SWC (mΩ)
RDS(ON)_SWA (mΩ)
100
68
52
VCC = 3.3V
VCC = 5.0V
Temperature (°C)
35
60
85
RDS(ON)_SWC vs. Temperature
84
60
10
(Load Current = 600mA, RSET = 1.24MΩ)
120
35
-15
Temperature (°C)
100
10
VOUT Rising
VOUT Falling
RDS(ON)_SWA vs. Temperature
-15
85
1.94
(Load Current = 600mA, RSET = 1.24MΩ)
20
-40
60
2.00
1.70
85
Temperature (°C)
36
35
1.76
VCC Rising
VCC Falling
-15
10
VUVLO_OUT vs. Temperature
2.30
1.98
-40
-15
Temperature (°C)
VUVLO_VCC vs. Temperature
2.02
VOUT = 5.5V
VOUT = 5.0V
VOUT = 3.0V
VOUT = 2.5V
80
60
40
20
-40
85
VOUT = 3.3V
VOUT = 5.0V
-15
10
35
60
85
Temperature (°C)
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DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Typical Characteristics
RDS(ON) vs. Input Voltage
Current Limit Error vs. Temperature
(Load Current = 600mA, RSET = 1.24MΩ)
(VCC = 5.0V, RSET = 1.24MΩ)
80
4
Current Limit Error (%)
RDS(ON)_SWA
RDS(ON)_SWC
75
RDS(ON) (mΩ)
70
65
60
55
50
45
40
2.5
3
3.5
4
4.5
5
0
-2
-4
-6
-40
5.5
Input Voltage (V)
2
-15
Current Limit vs. SYS Voltage
2.00
2.00
Current Limit (A)
Current Limit (A)
2.50
1.50
1.00
0.50
4.5
4
3.5
3
2.5
2
VSYS (V)
1.5
1.00
0.50
0.00
1
0
200
400
600
800
1000
1200
RSET (kΩ)
POK Delay Time
(VCC = 5.0V, RSET = 1.24MΩ)
(RADJ = 18.2kΩ)
VADJ
(0.2V/div)
VCC
(1V/div)
VPOK
(2V/div)
VPOK
(2V/div)
Time (0.8µs/div)
85
1.50
ADJ Detect Delay Time
6
60
(VCC = 5.0V)
2.50
5
35
Current Limit vs. RSET
(RADJ = 18.2kΩ, RSET = 1.24MΩ, CIN = CSYS = 10μF)
0.00
10
Temperature (°C)
Time (100µs/div)
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1400
1600
DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Typical Characteristics
RDY Delay Time From High to Low
RDY Delay Time From Low to High
(VCC = 5.0V, RSET = 1.24MΩ)
(VCC = 5.0V, RSET = 1.24MΩ)
VOUT
(1V/div)
VOUT
(1V/div)
VRDY
(2V/div)
VRDY
(2V/div)
4.5
4.5
0
0
Time (2µs/div)
Time (100µs/div)
Current Limit Response
Load Transient
(VCC = 5.0V, RSET = 1.24MΩ, RLOAD = 5Ω to 1Ω)
(VCC = 5.0V, VOUT = 2.0V,
RSET = 1.24MΩ, ISYS = 1A to 2A)
VSYS
(2V/div)
VCC
(0.2V/div)
ISYS
(2A/div)
ISYS
(2A/div)
0
1
VSYS
(1V/div) 4.5
ICC 2
(1A/div)
IOUT
(2A/div) 0
5
0
Time (20µs/div)
Time (10ms/div)
Discharge Path Switching
(VOUT = 5.0V, RSET = 1.24MΩ, RADJ = 18.2kΩ,
VCC = 5V to 4V, 1A Load)
VCC
(1V/div)
ICC
(1A/div)
IOUT
(1A/div)
ISYS
(1A/div)
4
0
0
1
Time (100ms/div)
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DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Functional Block Diagram
Reverse
Blocking
VCC
SYS
Over-Temp
Protection
Under Voltage
Lockout
1.2V
Reference
ADJ
OUT
Current Limit
Control
RDY
Voltage
Detector
Control
System
POK
GND
Functional Description
The AAT4712 is an integrated P-channel MOSFET load
switch with adjustable current limits, integrated discharge
path, over temperature protection, a power loop and a
super capacitor charger. The input current limit control is
combined with an over-temperature thermal limit and
power loop circuit to provide a comprehensive system to
protect the load switch and its supply from load conditions exceeding the supply specifications. The AAT4712
integrates the discharge path for SYS (to system load)
from the VCC input or OUT input (connected to supercap)
determined by whether VCC is higher than the programmed
threshold setting by ADJ through an external resistor.
The input current is limited and is programmed by an
external resistor for both system load and supercapacitor charging; system load always has higher priority.
The device decreases supercapacitor charging current to
provide more current to system load when the system
load increases and keeps the host power rating from
exceeding the input current limit.
8
Power
Loop
ISET
The integrated over-temperature circuits act independently of the input current limit. The device input current limit is activated when the output load current
exceeds an internal threshold level. The input current
limit threshold in each case is determined by external
resistors connected between the ISET pin and ground.
The minimum input current limit threshold is specified
by ILIM(MIN). If the load condition maintains the device in
current limit and the chip temperature reaches a critical
point, then an internal power loop will reduce the current to a safe level.
VCC pin under-voltage lockout circuitry ensures that the
VCC supply is high enough for correct operation of the IC.
OUT pin under-voltage lockout circuitry ensures that the
VOUT supply is high enough for correct operation of the
IC when no VCC input power or VCC below UVLO voltage.
An integrated POK function is adopted to indicate the
system input power good.
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DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Setting the Input Current Limit
Discharge Path Control
The AAT4712 current limit is set via the ISET resistor.
The ISET node operates within a window of 0.6V to 1.2V
for resistor values ranging from 93.75kΩ to 1.5MΩ.
Resistor values outside this range are not recommended.
The ISET source current varies with the resistor value as
shown in Table 1.
When the input voltage drops below the power good
detect threshold programmed by the external resistor
from ADJ pin to GND and the OUT pin voltage is greater
than the VUVLO_OUT and SYS pin voltage, the AAT4712
turns on the OUT to SYS switch discharge path after 6µs
(TSW) response time, then turns off the path of VCC to
the SYS P-channel load switch. The OUT to SYS switch
remains continuously on until the OUT pin voltage falls
below VUVLO_OUT.
VISET = RSET · IISET = 0.6V to 1.2V
If the set pin is open circuit or allowed to exceed 2V, all
power devices are disabled and the input is disconnected
from the output.
SYS Load and Capacitor Charge
The input current limit is equal to the SYS current plus
the OUT charging current. If the SYS current increases/
decreases, the OUT charging current will automatically
decrease/increase accordingly by the device control
loop. For example, if the input current limit is programmed to 1A and the SYS load current is 0.5A, then
the OUT charging current is 0.5A; if the SYS load current
increases to 0.8A, the OUT current decreases to 0.2A
accordingly; if the SYS load current decreases to 0.2A,
the OUT current increases to 0.8A dynamically.
Power Loop
The AAT4712's power loop limits the load current if
device power dissipation becomes excessive. The power
loop decreases the load current gradually to 1/32 of the
current limit set point when the die temperature exceeds
130°C. The load current then increases in increments of
1/32 of the current limit set point until the set current
limit point is reached or the die temperature exceeds
130°C. Figures 1 and 2 show the the power loop function
as the device temperature increases and decreases at a
1A current limit setting.
RSET Range (Ω)
IISET (µA)
ILIM/VISET (A/V)
Current Limit Range (A)
Current Limit
1.5M - 750k
750k - 375k
375k - 187.5k
187.5k - 93.75k
0.8
1.6
3.2
6.4
2
1
0.5
0.25
2.4-1.2
1.2-0.6
0.6-0.3
0.3-0.15
RSET*0.8*2
RSET*1.6*1
RSET*3.2*0.5
RSET*6.4*0.25
Table 1: RSET Values for Setting the Input Current.
Increase Ambient Temperature
ICC
(100mA/div)
ICC
(100mA/div)
Drop to 1/32 of
1A Current Limit
0A
0A
Time (20ms/div)
Figure 1: AAT4712 Power Loop Function at 1A Current Limit with Ambient Temperature Increasing.
Time (20ms/div)
Figure 2: AAT4712 Power Loop Function at 1A
Current Limit with Ambient Temperature Decreasing.
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9
DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Application Information
The delay time between die temperature measurements
varies depending on the load current limit set point. The
delay ranges from 0.5ms for a 150mA current limit set
point to 4ms for a 2.4A current limit set point.
Over-Temperature Protection
If the die temperature rises quickly enough to exceed
the power loop regulated temperature, over-temperature shutdown disables the device. The over-temperature threshold is 150°C. After over-temperature shutdown, soft start is initiated once the die temperature
drops to 135°C.
Input Current Limit Setting
The input current limit is programmed by RSET from ISET
to ground in the range from 150mA to 2.4A. The current
limit limits the maximum current of both VCC to SYS and
VCC to OUT. The RSET can be calculated by:
RSET =
Table 2 lists some 1% standard metal film resistor values for current limit settings from 150mA to 2.4A.
RSET (kΩ)
Current Limit (A)
1500
1240
1000
750
620
499
374
249
187
93.1
2.4
2
1.6
1.2
1
0.8
0.6
0.4
0.3
0.15
Power OK Indicator (POK)
On initial power-up, if VCC is higher than the power good
detect threshold programmed by the external resistor
from the ADJ pin to GND, the POK signal switches from
low to high after 2µs delay time (TDETECT) to indicate input
power good.
If VCC drops below the power good detect point, the
POK signal switches from high to low after 2µs delay
time (TDETECT).
Capacitor Charge Ready Indicator (RDY)
The internal comparator senses the OUT voltage and
delivers a high level as ready signal to the external
microcontroller when the OUT voltage reaches 98% of
the VCC voltage with fixed 200mV hysteresis.
The capacitor charge ready pin (RDY) is an open drain
output. A external pull up resistor with a typical value of
100kΩ is required.
Table 2: Recommended Current Limit RSET Values.
Power Good Detect Threshold Setting
The power good detect threshold (VPOK_TH) determines the
point at which the discharge path changes from VCC –
SYS to OUT – SYS if the OUT pin voltage is above VUVLO_
OUT and the SYS pin voltage. The power good detect
threshold is programmed by the external resistor RADJ
connected from the ADJ pin to GND. The RADJ value can
be calculated by:
RADJ =
10
ILIM
(Current in A, resistance in kΩ)
1.6
60
(Voltage in V, resistance in kΩ)
VPOK_TH - 1.2
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DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Table 3 summarizes some 1% standard metal film resistor values for various VPOK_TH settings. RADJ (kΩ)
VPOK_TH (V)
15.8
18.2
20.5
26.1
33.2
47
5.0
4.5
4.0
3.5
3.0
2.5
Table 3: Recommended Resistor Values
for VPOK_TH Settings.
Discharge Path Control
As the AAT4712 powers the system load, the device
automatically selects VCC or OUT as the power source.
OUT is designed to connect a supercapacitor as a backup
source. Figure 3 shows the discharge path control operation at 1A current limit setting. When VCC is powered on
from zero to 5V, the SYS voltage also rises to 5V and
500mA current is passed through from VCC to SYS as
system load. With the 1A current limit, the additional
500mA is used to charge the supercapacitor via IOUT as
shown. After 3.5 seconds, the 550mF supercapacitor is
fully charged; the charging current decreases to zero,
and ICC current decreases to 500mA. When VCC drops
from 5V to zero, the backup power source VOUT provides the 500mA load current to SYS until the supercapacitor voltage is discharged to below the UVLO voltage
threshold (typ. 1.8V).
VCC
(5V/div)
VOUT
(5V/div)
VSYS
(5V/div)
ISYS
(1A/div)
ICC
(1A/div)
IOUT
(1A/div)
Reverse Blocking
The internal reverse blocking comparator disconnects
the VCC to SYS path by turning off the power PMOSFETs
when SYS is higher than VCC minus 18mV, preventing
any reverse current from the system load to the input.
With 22mV hysteresis, the VCC to SYS path will be
reconnected by turning on the power PMOSFETs when
the SYS voltage drops to VIN minus 40mV. The reverse
blocking comparator has a typical 5µs delay time, which
may lead to output voltage ripple on the SYS output at
light load. Increasing the SYS output capacitor value can
improve the output voltage ripple when the application
has special SYS voltage ripple requirements.
Input Capacitor
A 10μF capacitor is typically recommended for CIN. CIN
should be located as close to the device VCC pin as practically possible. Ceramic, tantalum, or aluminum electrolytic capacitors may be selected for CIN. There is no specific capacitor equivalent series resistance (ESR) requirement for CIN. However, for higher current operation,
ceramic capacitors are recommended for CIN due to their
inherent capability over tantalum capacitors to withstand
input current surges from low impedance sources.
System Output Capacitor
A small output capacitance of approximately 10μF is
required at the system output. The output capacitor
helps to filter the SYS voltage when the device works
between reverse blocking and normal operation. For
higher output voltage ripple requirements at light load
(below 1/3 current limit), a greater output capacitor
value is required.
OUT Supercapacitor
Time (2s/div)
Figure 3: Discharge Path Control with 550mF
Supercapacitor at 1A Current Limit Setting and
500mA System Load.
The AAT4712's OUT pin is designed to connect a supercapacitor to ground to give the system a backup when
VCC experiences short power interrupts. A supercapacitor offers high capacitance in a small package; it adopts
special electrodes and some electrolyte. Three types of
electrode materials are suitable for the supercapacitor:
high surface area activated carbons, metal oxide, and
conducting polymers. The first option is the lowest cost
to manufacture; the electrolyte usually is aqueous or
organic. An aqueous electrolyte offers low internal resis-
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11
DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
tance but limits the voltage to 1V; the organic allows
2.5V of charge but has higher internal resistance. For
higher voltage applications, supercapacitors are connected in series. To prevent any cell from charging overvoltage, a balance resistor is required on a string of
more than three cells.
The AAT4712 also includes short-circuit protection circuitry for the discharge path from OUT to SYS to avoid
large current discharging through the device over a long
term and avoid damage to the device.
Three parameters should be considered when selecting
a supercapacitor. These parameters are capacitance,
rated voltage, and ESR. Table 4 shows some recommended supercapacitors. Other parameters such as
temperature range, RMS current, leakage current, etc.
should also be considered during the system design.
For proper thermal management and to take advantage
of the low RDS(ON) of the AAT4712, certain circuit board
layout rules should be followed:
SYS Short Circuit Protection
The series pass power MOSFET from VCC to SYS limits
the current to a low level after the SYS output shorts to
ground to protect the device and downstream components. During the fault condition, the power loop is still
active to monitor the die temperature and reduce the
current when the die temperature exceeds 130°C. Once
the short-circuit fault is removed, the SYS voltage recovers to the normal value automatically.
Manufacturer
Cap-xx
TDK
PCB Layout Recommendations
1.VCC, VOUT, and VSYS should be routed using wide
traces.
2. GND should be connected to a ground plane. The
ground plane area connected to the ground pins
should be made as large as possible.
3. For best performance, CIN and CSYS should be placed
close to the VCC and SYS pins.
4. For maximum power dissipation of the AAT4712
TDFN package, the exposed pad should be soldered
to the board ground plane to further increase local
heat dissipation. A ground pad below the exposed
pad is strongly recommended.
Part Number
Capacitance (mF)
Rated Voltage (V)
ESR
(mΩ)
Size LxWxH (mm)
HS 203F
HS 211F
HS 206F
HW 207F
EDLC152344-551-2F-30
EDLC262020-501-2F-50
250
370
600
450
550
500
5.5
5.5
5.5
5.5
5.5
5.5
70
55
70
100
30
50
39x17x2.15
39x17x2.9
39x17x2.4
28.5x17x2.9
44x23x1.5
20x20x2.6
Table 4: Recommended Supercapacitors
12
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Evaluation Board Schematic
POK
U1 AAT4712
VCC
RDY
RADJ 18.2k
14
N/C
3
RSET 1.24M
ADJ
2
ISET
RDY
1
R1 1.74k
D1 LED
R2 1.74k
D2 LED
GND
SYS
15
GND
POK
16
4
SYS
VCC
13
5
SYS
VCC
12
6
SYS
OUT
11
7
SYS
OUT
10
8
SYS
OUT
9
C2
10µF
C1
10µF
OUT
C3
22µF
Super
Cap
RB1
RB2
Figure 4: AAT4712 Evaluation Board Schematic.
Evaluation Board Layout
a: Top Side b: Bottom Side
Figure 5: AAT4712 Evaluation Board Layout.
Component
Part Number
Description
Manufacturer
U1
R1,R2
RSET
RADJ
C1, C2
C3
D1, D2
SUPERCAP, RB1, RB2
AAT4712
RC0603FR-071K74L
RC0603FR-071M24L
RC0603FR-0718K2L
GRM21BR61C106K
GRM21BR60J226M
0805KRCT
Not populated
Current Limited Switch with Capacitor Charger
Res 1.74KΩ 1/10W 1% 0603 SMD
Res 1.24MΩ 1/10W 1% 0603 SMD
Res 18.2KΩ 1/10W 1% 0603 SMD
Cap Ceramic 10μF 0805 X5R 16V 10%
Cap Ceramic 22μF 0805 X5R 6.3V 20%
Red LED 0805
Skyworks
Yageo
Murata
HB
Table 5: AAT4712 Evaluation Board Bill of Materials.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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13
DATA SHEET
AAT4712
Power Path with Input Current Limit and Capacitor Charger
Ordering Information
Package
Marking1
Part Number (Tape and Reel)2
TDFN34-16
G9XYY
AAT4712IRN-T1
Skyworks Green™ products are compliant with
all applicable legislation and are halogen-free.
For additional information, refer to Skyworks
Definition of Green™, document number
SQ04-0074.
Package Information3
TDFN34-16
3.000 ± 0.050
0.450 ± 0.050
1.600 ± 0.050
Detail "A"
0.230 ± 0.050
0.450 ± 0.050
3.300 ± 0.050
4.000 ± 0.050
Index Area
Top View
Bottom View
0.750 ± 0.050
Detail "A"
0.000
+ 0.100
-0.000
0.203 REF
Side View
All dimensions in millimeters.
1. XYY = assembly and date code.
2. Sample stock is generally held on part numbers listed in BOLD.
3.The leadless package family, which includes QFN, TQFN, DFN, TDFN and STDFN, has exposed copper (unplated) at the end of the lead terminals due to the manufacturing
process. A solder fillet at the exposed copper edge cannot be guaranteed and is not required to ensure a proper bottom solder connection.
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14
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201912B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • August 30, 2012