AEC-Q100-REV G Qualification IXD_614SI VIS Foundry Process CU05UMS12010 Qualification No: 2014-001 Reliability Report AEC-Q100-REV G Qualification for IXD_614SI VIS Foundry Process CU05UMS12010 Report Number: 2014-001 Date: 2/6/15 IXYS Integrated Circuits Division, 78 Cherry Hill Drive, Beverly, MA 01915, USA Tel: 1-978-524-6700, Fax: 1-978-272-5273, WWW.IXYSIC.COM Page 1 of 5 AEC-Q100-REV G Qualification IXD_614SI VIS Foundry Process CU05UMS12010 Qualification No: 2014-001 Introduction This report summarizes the AEC-Q100-REV G qualification of IXYS Integrated Circuits Division’s IXD_614SI. The qualification data presented here were collected by IXYS ICD AV. The IXD_614SI silicon is foundered at Vanguard International Semiconductor Corp. (VIS) and is assembled at Greatek Electronics Inc. in Taiwan. The VIS process is CU05UMS12010. Qualification Tests Table 1 below provides the qualification tests that were performed. The stress tests and sample size are per AEC-Q100-REV G. Table 1: AEC-Q100-REV G Qualification Tests Product IXD_614SI Stress Test HTOL Applicable Specs Stress Conditions HAST JESD22-A110-C 130C, 85% RH, 18.8psi, 96 hrs Mil-Std-883, 0 to 100C, 10/10 M1011 dwells, 15 cycles JESD22-A108 1000 hrs, 150C Number Sample Total of Lots Size (SS) SS 3 77 231 3 77 231 2 15 30 Temp Cycle JESD22-A104-C -65 to 150C, 10/10 (T/C) dwells, 500 cycles 3 77 231 High Temp Storage Autoclave Solderability Latch Up Wirebond Pull Wirebond Shear Gate Leakage ELFR PTC JESD22-A103C 150C, 1000 hrs 3 45 135 J-STD-020D.1, JESD22-A102 AEC-Q100-004 T=121C, RH=100%, t=96 hrs unbiased T=125C, 35V, 100mA Examine 30 bonds From a min of 5 pcs Examine 30 bonds From a min of 5 pcs T=RT 3 77 231 1 8 8 2 15 30 2 15 30 1 8 8 3 800 2400 1 45 45 AEC-Q100008-REV A AEC-Q100008-REV A RTN-0441D REV AEC-Q100T=150C, t=48 hrs 008-REV A With bias JESD22-A105-C T=-40C/+125C, 1000 cycles, t=45 min IXYS Integrated Circuits Division, 78 Cherry Hill Drive, Beverly, MA 01915, USA Tel: 1-978-524-6700, Fax: 1-978-272-5273, WWW.IXYSIC.COM Page 2 of 5 AEC-Q100-REV G Qualification IXD_614SI VIS Foundry Process CU05UMS12010 Qualification No: 2014-001 Stress Test ESD CDM ESD HBM Applicable Specs Stress Conditions JESD22-A114-E 1.5k, 100pF JESD22-A114-E 1.5k, 100pF Number Sample Total of Lots Size (SS) SS 1 9 9 1 12 12 Qualification Test Results The stress tests and associated results for the IXD_614SI AEC-Q100-REV G qualification are summarized in Table 2. The devices chosen for the qualification were from standard material manufactured through normal production test flow and electrically tested to datasheet limits prior to stressing. Qualification stresses were conducted and parts then electrically tested to datasheet limits at each interval and the final readpoints. Table 2: AEC-Q100-Rev G Qualification Test Results Product IXD_614SI Stress Test HTOL Readpoint / (Reject/SS) 1000 hrs 0/231 HAST 96 hrs 0/231 Solderability 15 Cycles 0/30 Temp Cycle 500 Cycles 0/231 High Temp Storage 1000 hrs 0/135 Autoclave 96 hrs 0/231 Latch-Up Trigger Pulse 0/8 Wirebond Pull 30 Bonds Tested 0/30 IXYS Integrated Circuits Division, 78 Cherry Hill Drive, Beverly, MA 01915, USA Tel: 1-978-524-6700, Fax: 1-978-272-5273, WWW.IXYSIC.COM Page 3 of 5 AEC-Q100-REV G Qualification IXD_614SI VIS Foundry Process CU05UMS12010 Qualification No: 2014-001 Stress Test Wirebond Shear Readpoint / (Reject/SS) 30 Bonds Tested 0/30 Gate Leakage Neg./Pos.Potential 0/8 ELFR 48 hrs 0/2400 PTC 1000 cycles 0/45 ESD Testing Results As part of this AEC-Q100-REV G qualification, the IXD_614SI product family was subjected to Human Body Model (HBM) ESD Sensitivity Classification testing using a KeyTek Zapmaster system. Charged Device Model testing was subcontracted to Integra Technologies LLC. The results are summarized in Table 3. Table3: AEC-Q100-REV G ESD Testing Results Product IXD_614SI ESD Model CDM HBM Package ESD Test Spec RC Network SOIC – 8L EP AEC- Q100-011 1 meas resistor SOIC – 8L EP JESD22, A114-E 1.5k, 100pF Highest Passed Class 500V/all pins 750Vcorner pins 2000V C4B H2 FIT (Failure in Time) Table 4 summarizes the number of devices used for the IXD_614SI AEC-Q100-REV G qualification testing and the associated failures. Using the HTOL data, FIT rates were calculated based on the Acceleration Factor (AF) and equivalent device hours at 0.7eV of activation energy for 150C test temperature and 40C use temperatures. Using the HAST data, FIT rates were calculated based on the Acceleration Factor (AF) and equivalent device hours at 0.7eV of activation energy for 130C test temperature and 40C use temperatures. The calculated FIT rates from the reliability stress is 15.59 for HTOL and 28.98 for HAST IXYS Integrated Circuits Division, 78 Cherry Hill Drive, Beverly, MA 01915, USA Tel: 1-978-524-6700, Fax: 1-978-272-5273, WWW.IXYSIC.COM Page 4 of 5 AEC-Q100-REV G Qualification IXD_614SI VIS Foundry Process CU05UMS12010 Qualification No: 2014-001 Table 4: FIT Rate Summary Product IXD_614SI Qual# Stress # of # of Hours Act. Devices Fails Tested Energy 1 HTOL 231 0 1000 0.7 1 HAST 231 0 96 0.7 Acc. Factor Equivalent FIT Rate Dev. Hours @ 60% CL 255.41 58,998,778 15.59 1.4318E +03 31,751,277 28.98 Conclusion The qualification of the IXD_614SI has been successfully completed according to AECQ100-REV G, and therefore the IXD_614SI is AEC Q100 qualified. APPROVAL: Prepared by: Martha W. Brandt * _______________2/6/15__ Martha W. Brandt Date Quality Engineer Approved by: George Belezos *_________________2/6/15__ George Belezos Date Quality Manager Approved by: James Archibald *________________2/6/15__ James Archibald Date Director of Development Engineering * Signature on File IXYS Integrated Circuits Division, 78 Cherry Hill Drive, Beverly, MA 01915, USA Tel: 1-978-524-6700, Fax: 1-978-272-5273, WWW.IXYSIC.COM Page 5 of 5