ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS843031-01 is an 10Gb Ethernet Clock ICS Generator and a member of the HiPerClocks TM HiPerClockS™ family of high performance devices from IDT. The ICS843031-01 uses an 18pF parallel resonant crystal. The ICS843031-01 has excellent <1ps phase jitter perfor mance, over the 1.875MHz - 20MHz integration range. The ICS843031-01 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • One differential 3.3V or 2.5V LVPECL output • Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal • Output frequencies: 280MHz – 340MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 312.5MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.46ps (typical) • Full 3.3V or 2.5V operating supply • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages COMMON CONFIGURATION TABLE Inputs Crystal Frequency (MHz) M N 25 25 2 Multiplication Value M/N 25 Output Frequency (MHz) 312.5 BLOCK DIAGRAM PIN ASSIGNMENT OE Pullup XTAL_IN OSC XTAL_OUT Phase Detector VCO N = ÷2 (fixed) 1 2 3 4 8 7 6 5 VCC Q nQ OE ICS843031-01 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View M = ÷25 (fixed) IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR Q nQ VCCA VEE XTAL_OUT XTAL_IN 1 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VCCA Power Analog supply pin. 2 Power 5 VEE XTAL_OUT, XTAL_IN OE Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Output Enable pin. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential clock outputs. LVPECL interface levels. 8 VCC Power Power supply pin. 3, 4 Type Description Input Input Pullup NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLDOWN Input Pullup Resistor 51 kΩ TABLE 3. OE FUNCTION TABLE Input Outputs OE Q/nQ 0 Hi-Z 1 Enabled IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 2 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VCC Power Supply Voltage Test Conditions 3.135 3.3 3.465 V VCC – 0.12 3.3 V CCA Analog Supply Voltage 3.465 V I CCA Analog Supply Current 12 mA I EE Power Supply Current 105 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VCC Power Supply Voltage Test Conditions 2.375 2.5 2.625 V VCC – 0.12 2.5 V CCA Analog Supply Voltage 2.625 V I CCA Analog Supply Current 12 mA I EE Power Supply Current 90 mA TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Maximum Units VCC = 3.3V 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V 5 µA VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VCC = VIN = 3.465V or 2.625V IIL Input Low Current VCC = 3.465V or 2.625V, VIN = 0V IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 3 -150 Typical µA ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum V CC - 1.4 Typical V CC - 0.9 V VOL Output Low Voltage; NOTE 1 V CC - 2.0 V CC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1. 0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 27.2 MHz Equivalent Series Resistance (ESR) Frequency 22.4 25 40 Ω Shunt Capacitance 7 pF 300 mW Drive Level TABLE 6A. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time tjit(Ø) t R / tF Test Conditions 312.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. Minimum Typical Maximum Units 280 312.5 340 MHz 0.46 ps 150 500 ps 48 52 % TABLE 6B. AC CHARACTERISTICS, VCC = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time tjit(Ø) tR / tF Test Conditions 312.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 4 Minimum Typical Maximum Units 280 312.5 340 MHz 0.48 ps 150 500 ps 48 52 % ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TYPICAL PHASE NOISE AT 312.5MHZ AT 3.3V 0 ä -30 -40 10Gb Ethernet Filter -50 -60 -70 RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.46ps 312.5MHz -80 -90 Raw Phase Noise Data -100 -110 ä NOISE POWER dBc Hz -10 -20 -120 -130 -140 -190 100 ä -150 -160 -170 -180 1k Phase Noise Result by adding 10Gb Ethernet Filter to raw data 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 5 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V 2V 2V 2V VCC Qx SCOPE VCC Qx VCCA VCCA LVPECL LVPECL nQx nQx VEE -1.3V ± 0.165V SCOPE -0.5V ± 0.125V 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot Noise Power nQ Q t PW t odc = PERIOD t PW Phase Noise Mask x 100% t PERIOD f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% RMS PHASE JITTER 80% VSW I N G Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 6 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843031-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V or 2.5V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS843031-01 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p FIGURE 2. CRYSTAL INPUt INTERFACE IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 7 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT FIN 125Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION 8 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TERMINATION FOR 2.5V LVPECL OUTPUT Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 9 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843031-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843031-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 105mA = 363.8mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 363.8mW + 30mW = 393.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.394W * 90.5°C/W = 105.6°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W 10 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V L CC_MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) = L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) = [(2V - (V L CC_MAX - VOL_MAX))/R ] * (VCC_MAX - VOL_MAX) = L [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 11 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS843031-01 is: 2377 IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 12 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.2 0 A1 0.05 0.1 5 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.1 0 6.40 BASIC 4.30 e 4.5 0 0.65 BASIC L 0.45 0.7 5 α 0° 8° aaa -- 0.1 0 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 13 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843031AG-01 31A01 8 Lead TSSOP tube 0°C to 70°C ICS843031AG-01T 31A01 8 Lead TSSOP 2500 tape & reel 0°C to 70°C ICS843031AG-01LF 1A01L 8 Lead "Lead-Free" TSSOP tube 0°C to 70°C ICS843031AG-01LFT 1A01L 8 Lead "Lead-Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuraiton and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 14 ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR REVISION HISTORY SHEET Rev Table Page A T3 2 Added OE Function Table. Description of Change 1/23/07 A T1 0 14 Order Information Table - Added Lead Free marking 8/1/07 IDT ™ / ICS™ 3.3V, 2.5V LVPECL CLOCK GENERATOR 15 Date ICS843031AG-01 REV. A AUGUST 1, 2007 ICS843031-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA