IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: – – – – – – – – – Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages Extended commercial range of -40°C to +85°C VCC = 3.3V ±0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range CMOS power levels (0.4µ W typ. static) All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion The LVC16646A 16-bit bus transceiver/register is built using advanced dual metal CMOS technology. This high-speed, low power device is organized as two independent 8-bit D-type transceivers with 3-state D-type registers. The control circuitry is organized for multiplexed transmission of data between the A bus and B bus either directly or from the internal storage registers. Each 8-bit transceiver/register features direction control (DIR), over-riding Output Enable control (OE) and Select lines (SAB and SBA) to select either real-time data or stored data. Separate clock inputs are provided for A and B port registers. Data on the A or B data bus, or both, can be stored in the internal registers by the low-to-high transitions at the appropriate clock pins. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. Drive Features for LVC16646A: – High Output Drivers: ±24mA – Reduced system switching noise All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. APPLICATIONS: The LVC16646A has been designed with a ±24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance. • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems Functional Block Diagram 29 56 2 OE 1 OE 1 DIR 1 28 2 DIR 55 1 CLKBA 2 CLKBA 54 2 SBA 1 SBA 2 30 31 27 2 CLKAB 1 CLKAB 3 1 SAB 2 SAB 26 B REG B REG 1A 1 5 1D 1D C1 C1 52 A REG 1B 1 2A 1 15 1D 42 A REG 2B 1 1D C1 C1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS EXTENDED COMMERCIAL TEMPERATURE RANGE APRIL 1999 1 c 1998 Integrated Device Technology, Inc. DSC-4488/1 IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER EXTENDED COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION 1DIR 1 56 1OE 1CLKAB 2 55 1CLKBA 1 SAB 3 54 1 SBA GND 4 53 GND 1A 1 5 52 1B 1 51 1B 2 1A 2 6 V CC 7 50 V CC 1A 3 8 49 1B 3 1A 4 9 48 1B 4 10 47 1B 5 GND 11 46 GND 1A 6 12 45 1B 6 1A 7 13 44 1B 7 43 1B 8 42 2B 1 16 41 2B 2 17 40 2B 3 18 39 GND 1A 5 1A 8 2A 1 2A 2 2A 3 GND 14 15 SO56-1 SO56-2 SO56-3 2A 4 19 38 2B 4 2A 5 20 37 2B 5 21 36 2B 6 V CC 22 35 V CC 2A 7 23 34 2B 7 2A 8 24 33 2B 8 GND 25 32 GND 2 SAB 26 31 2 SBA 2 CLKAB 27 30 2 CLKBA 2 DIR 28 29 2 OE 2A 6 (1) Symbol VTERM(2) Description Terminal Voltage with Respect to GND Max. – 0.5 to +6.5 Unit V VTERM(3) Terminal Voltage with Respect to GND – 0.5 to +6.5 V TSTG Storage Temperature – 65 to +150 °C IOUT DC Output Current – 50 to +50 mA IIK IOK ICC Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through – 50 mA ±100 mA ISS each VCC or GND LVC Link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25OC, f = 1.0MHz) Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 4.5 Max. 6 Unit pF COUT Output Capacitance I/O Port Capacitance VOUT = 0V 6.5 8 pF VIN = 0V 6.5 8 pF CI/O LVC Link NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names xAx xCLKAB, xCLKBA Description Data Register A Inputs Data Register B 3-State Outputs Data Register B Inputs Data Register A 3-State Outputs Clock Pulse Inputs xSAB, xSBA Output Data Source Select Inputs xBx xOE Output Enable Inputs xDIR Direction Control Inputs SSOP/ TSSOP/ TVSOP TOP VIEW c 1998 Integrated Device Technology, Inc. 2 DSC-123456 IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER FUNCTION TABLE EXTENDED COMMERCIAL TEMPERATURE RANGE (1) Data I/O(2) Inputs xOE xDIR xCLKAB xCLKBA xSAB xSBA xAx xBx X X H H L L L L X X X X L L H H ↑ X ↑ H or L X X X H or L X ↑ ↑ H or L X H or L X X X X X X X X L H X X X X L H X X Input Unspecified(2) Input Input Output Output Input Input Unspecified(2) Input Input Input Input Input Output Output Operation or Function Store A, B unspecified(2) Store B, A unspecified(2) Store A and B Data Isolation, hold storage Real Time B Data to A Bus Stored B Data to A Bus Real Time A Data to B Bus Stored A Data to B Bus NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW-to-HIGH Transition 2. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40OC to +85OC Symbol VIH Parameter Input HIGH Voltage Level VCC = 2.3V to 2.7V Min. 1.7 Typ.(1) — Max. — VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 Test Conditions Unit V VIL Input LOW Voltage Level — — 0.8 IIH IIL IOZH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V — 100 — mV ICCL ICCH ICCZ Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC — — 10 µA 3.6 ≤ VIN ≤ 5.5V(2) — — 10 ∆ICC Quiescent Power Supply Current Variation — — 500 VCC = 2.7V to 3.6V VCC = 0V, VIN or VO ≤ 5.5V One input at VCC - 0.6V other inputs at VCC or GND V µA LVC Link NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. 3 IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER BUS A xDIR L xOE L EXTENDED COMMERCIAL TEMPERATURE RANGE BUS A BUS B xCLKAB X xCLKBA X xSAB X xSBA L xDIR H xOE L xDIR X X X xOE X X H ↑ xCLKBA X X ↑ ↑ ↑ xCLKBA X BUS A BUS B xCLKAB xCLKAB X xSAB L xSBA X REAL-TIME TRANSFER BUS A TO B REAL-TIME TRANSFER BUS B TO A BUS A BUS B xSAB X X X xSBA X X X xDIR L H STORAGE FROM A, B, OR A AND B (1) BUS B xOE L L xCLKAB X H or L xCLKBA H or L X xSAB X H TRANSFER STORED DATA TO A AND/OR B NOTE: 1. Cannot transfer data to A Bus and B Bus simultaneously. 4 xSBA H X IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER EXTENDED COMMERCIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage VCC = 2.3V to 3.6V Test Conditions(1) IOH = – 0.1mA Min. VCC – 0.2 Max. — VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3.0V 2.4 — 2.2 — VCC = 3.0V IOH = – 24mA VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3.0V IOL = 24mA — 0.55 Unit V V LVC Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to +85°C. OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol CPD Parameter Power Dissipation Capacitance per Transceiver Outputs enabled CPD Power Dissipation Capacitance per Transceiver Outputs disabled Test Conditions CL = 0pF, f = 10Mhz 5 Typical 60 Unit pF 12 pF IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER EXTENDED COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS (1) VCC = 2.7V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay xAx to xBx or xBx to xAx Propagation Delay CLKBA to xAx or CLKAB to xBx Propagation Delay xSBA or xSAB to xAx or xBx Output Enable Time xOE to xAx or xBx Output Enable Time xDIR to xAx or xBx Output Disable Time xOE to xAx or xBx Output Disable Time xDIR to xAx or xBx Set-up Time HIGH or LOW xAx or xBx before CLKAB↑ or CLKBA↑ Hold Time HIGH or LOW xAx or xBx after CLKAB↑ or CLKBA↑ Clock Pulse Width HIGH or LOW Output Skew(2) Min. 150 Max. — Min. 150 Max. — Unit MHz — 6.8 1.3 5.7 ns — 7.9 1.8 6.7 ns — 9.2 1.7 7.7 ns — 8.5 1.3 6.9 ns — 8.5 1.4 7.2 ns — 7.7 2.1 6.9 ns — 7.8 2 7 ns 3.2 — 2.9 — ns — — 0.3 — ns 3.3 — 3.3 — ns — — — 500 ps NOTES: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 6 VCC = 3.3V±0.3V IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) = 2.7V VCC(2)= 2.5V ±0.2V Unit 2 x Vcc V 6 6 VIH 2.7 2.7 Vcc V VT 1.5 1.5 VCC / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF t PHL V IH VT 0V ENABLE AND DISABLE TIMES V LOAD V IN t PLH DISABLE ENABLE GND V IH CONTROL INPUT V OUT VT tPZL D.U.T. OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH 500 Ω RT V OH VT V OL LVC Link Open Pulse (1, 2) Generator tPHL OPPOSITE PHASE INPUT TRANSITION TEST CIRCUITS FOR ALL OUTPUTS 500 Ω t PLH OUTPUT LVC Link V CC V IH VT 0V SAME PHASE INPUT TRANSITION CL LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 0V tPLZ V LOAD/2 V LOAD/2 VT V OL+ V LZ V OL tPHZ VT V OH V OH-V HZ 0V 0V LVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. SWITCH POSITION SET-UP, HOLD, AND RELEASE TIMES Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD DATA INPUT tSU V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH TIMING INPUT GND tREM ASYNCHRONOUS CONTROL Open LVC Link SYNCHRONOUS CONTROL OUTPUT SKEW - tsk (x) t SU tH LVC Link V IH INPUT tPLH1 VT 0V tPHL1 PULSE WIDTH V OH OUTPUT 1 tSK (x) tSK (x) LOW -HIGH-LOW PULSE VT V OL tW V OH VT V OL OUTPUT 2 VT HIGH-LOW -HIGH PULSE VT LVC Link t PLH2 t PHL2 tSK (x) = tPLH2 - tPLH1 or t PHL2 - tPHL1 LVC NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. Link 7 IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX LVC Temp. R ange X XX XXXX XX Bus-Hold Family Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA PF Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 646A 16-Bit Bus Transceiver/R egister 16 Double-D ensity with Resistors, ±24m A Blank No Bus-hold 74 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 8