WM8233
210MSPS 6-Channel AFE with Sensor
Timing Generation and LVDS/CMOS Data Output
DESCRIPTION
FEATURES
210MSPS conversion rate
16-bit ADC resolution
Current consumption – 350mA
3.3V single supply operation
The device has six analogue signal processing channels
each of which contains Reset Level Clamping, Correlated
Double Sampling (also Sample and Hold), Programmable
Gain, Automatic Gain Control (AGC) and Offset adjust
functions.
Sample and hold /correlated double sampling
Programmable offset adjust (8-bit resolution)
Flexible clamp timing
Pixel clamp / line clamp mode
Programmable clamp voltage
The output from each of these channels is time multiplexed,
in pairs, into three high-speed 16-bit Analogue to Digital
Converters. The digital data is available in a variety of
output formats via the flexible data port.
Programmable CIS/CCD timing generator
Internally generated voltage references
Compliant for Spread Spectrum Clock
The WM8233 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 35MSPS per channel.
The WM8233 has a user selectable LVDS or CMOS output
architecture.
An internal 5-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during clamping to clamp CCD signals. An
external reference level may also be supplied. ADC
references are generated internally, ensuring optimum
performance from the device.
A programmable automatic Black-Level Calibration function
is available to adjust the DC offset of the output data.
The WM8233 features a sensor timing clock generator for
both CCD and CIS sensors. The clock generator can accept
a slow or fast reference clock input and also has a flexible
timing adjustment function for output timing clocks to allow
use of many different sensors.
http://www.cirrus.com
LVDS/CMOS output options
LVDS 5pair 490MHz 35-bit data
CMOS 90MHz output maximum
Complete on chip clock generator. MCLK 5MHz to 35MHz
Internal timing adjustment
Automatic Gain Control
Automatic Black Level Calibration
56-lead QFN package 8mm x 8mm
Serial control interface
APPLICATIONS
Digital copiers
USB2.0 compatible scanners
Multi-function peripherals
High-speed CCD/CIS sensor interface
Copyright Cirrus Logic, Inc., 2010–2016
(All Rights Reserved)
Rev 4.7
APR ‘16
WM8233
BLOCK DIAGRAM
VRLC/VBIAS
AVDD2
DBVDD
VREF1C VREF2C VREF3C
AVDD1
VREF
/BIAS
IN1
IN2
RLC
RLC
CDS
S/H
+
CDS
S/H
I/P SIGNAL
POLARITY
ADJUST
+
PGA
OFFSET
DAC
WM8233
+
PGA
OFFSET
DAC
+
M
U
X
16bit
ADC
10/16
+
I/P SIGNAL
POLARITY
ADJUST
D
I
G
I
T
A
L
HZCTRL
7
IN3
IN4
RLC
RLC
CDS
S/H
+
I/P SIGNAL
POLARITY
ADJUST
OFFSET
DAC
CDS
S/H
+
PGA
OFFSET
DAC
IN5
IN6
RLC
RLC
CDS
S/H
+
M
U
X
16bit
ADC
10/16
+
&
I/P SIGNAL
POLARITY
ADJUST
+
D
A
T
A
+
PGA
I/P SIGNAL
POLARITY
ADJUST
OFFSET
DAC
CDS
S/H
+
PGA
+
OFFSET
DAC
PGA
C
O
N
T
R
O
L
+
M
U
X
16bit
ADC
10/16
+
D1P/OP[0]
D1N/OP[1]
7
D2P/OP[2]
D2N/OP[3]
7
7
LVDS(
Chanel
link)/
CMOS
7
7
D3P/OP[4]
D3N/OP[5]
D4P/OP[6]
D4N/OP[7]
D5P/OP[8]
D5N/OP[9]
DCLKP/OC[1]
DCLKN/OC[2]
M
A
P
P
I
N
G
I/P SIGNAL
POLARITY
ADJUST
RLC
DAC
LDO1
LDO1VDD
LDO1GND
LDO1VOUT
LDO2
LDO2VDD
LDO2GND
LDO2VOUT
BLACK LEVEL
CALIBRATION
Phase
Adjustment
AUTO GAIN
CONTROL
2
SERIAL
CONTROL
INTERFACE
TGSYNC
CLK9
CLK10
CLK11
AGND1
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
AGND3 AGND2
CLK1
CLK2
SENSOR
TIMING GENERATION
MON
DSLCT1
DSLCT2
MCLK
SDO
SEN
SCK
SDI
DBGND
Rev 4.7
WM8233
TABLE OF CONTENTS
DESCRIPTION ................................................................................................................ 1
FEATURES ..................................................................................................................... 1
APPLICATIONS.............................................................................................................. 1
BLOCK DIAGRAM ......................................................................................................... 2
TABLE OF CONTENTS .................................................................................................. 3
PIN CONFIGURATION ................................................................................................... 5
ORDERING INFORMATION ........................................................................................... 5
PIN DESCRIPTION ......................................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ................................................................................. 7
RECOMMENDED OPERATING CONDITIONS .............................................................. 7
ELECTRICAL CHARACTERISTICS .............................................................................. 8
INTERNAL POWER ON RESET CIRCUIT ................................................................... 11
SIGNAL TIMING REQUIREMENTS ............................................................................. 12
SERIAL CONTROL INTERFACE ............................................................................................ 12
DEVICE IDENTIFICATION ...................................................................................................... 12
REGISTER WRITE .................................................................................................................. 13
REGISTER READ-BACK ........................................................................................................ 13
INPUT VIDEO SAMPLING ...................................................................................................... 14
NON-CDS (S/H) MODE ....................................................................................................................................... 14
CDS MODE .......................................................................................................................................................... 14
OUTPUT DATA TIMING (CMOS OUTPUT) ............................................................................ 16
OUTPUT DATA TIMING (LVDS OUTPUT) ............................................................................. 16
DEVICE DESCRIPTION ............................................................................................... 17
INTRODUCTION ..................................................................................................................... 17
RESET LEVEL CLAMPING (RLC) .......................................................................................... 17
CDS/NON-CDS PROCESSING............................................................................................... 19
OFFSET ADJUST AND PROGRAMMABLE GAIN.................................................................. 20
ADC INPUT BLACK LEVEL ADJUST ..................................................................................... 20
OVERALL SIGNAL FLOW SUMMARY ................................................................................... 21
ADC PGA BIAS CURRENT CONTROL .................................................................................. 22
PLL DLL SETUP ...................................................................................................................... 23
OUTPUT DATA FORMAT ....................................................................................................... 25
LVDS 10-BIT 5PAIR MODE ................................................................................................................................. 25
LVDS 16-BIT 5PAIR MODE ................................................................................................................................. 26
LVDS 10-BIT 3PAIR MODE ................................................................................................................................. 27
LVDS 16-BIT 3PAIR MODE ................................................................................................................................. 28
LVDS 12-BIT 4PAIR MODE ................................................................................................................................. 29
LVDS DATA OUTPUT ORDER............................................................................................................................ 30
CMOS OUTPUT MODE ....................................................................................................................................... 31
CLOCK TIMING CONFIGURATION ........................................................................................ 31
SENSOR TIMING GENERATION ........................................................................................... 32
TG MASTER MODE OPERATION ...................................................................................................................... 34
TG SLAVE MODE OPERATION .......................................................................................................................... 34
TG PULSE AND TRIGGER DATA ....................................................................................................................... 35
TG PULSE ........................................................................................................................................................... 36
TRIGGER DATA .................................................................................................................................................. 36
CHANNEL ID ....................................................................................................................................................... 36
TG MASK TIMING ............................................................................................................................................... 40
TG CYCLE MODE ............................................................................................................................................... 41
PROGRAMMABLE AUTOMATIC BLACK LEVEL CALIBRATION (BLC) ................................ 42
Rev 4.7
3
WM8233
TARGET CODES ................................................................................................................................................. 42
BLC SCENARIOS OF OPERATION........................................................................................ 43
SCENARIO 1 ....................................................................................................................................................... 43
SCENARIO 2 ....................................................................................................................................................... 44
SCENARIO 3 ....................................................................................................................................................... 45
AUTOMATIC GAIN CONTROL (AGC) .................................................................................... 46
LINE-BY-LINE OPERATION ................................................................................................... 47
TEST PATTERN GENERATOR .............................................................................................. 49
REGISTER SETTING PROCEDURE ...................................................................................... 51
OVERALL............................................................................................................................................................. 51
PLL/DLL CONFIGURATION ................................................................................................................................ 52
SAMPLING CONFIGURATION............................................................................................................................ 52
CLAMP CONFIGURATION .................................................................................................................................. 53
VRLC CONFIGURATION..................................................................................................................................... 54
OFFSET DAC CONFIGURATION ....................................................................................................................... 54
PGA CONFIGURATION ...................................................................................................................................... 55
TG CLOCK CONFIGURATION ............................................................................................................................ 57
TG PULSE CONFIGURATION ............................................................................................................................ 58
DATA OUTPUT CONFIGURATION ..................................................................................................................... 59
REGISTER MAP ........................................................................................................... 62
EXTENDED PAGE REGISTERS............................................................................................. 67
REGISTER BITS BY ADDRESS ............................................................................................. 67
APPLICATIONS INFORMATION ............................................................................... 141
RECOMMENDED EXTERNAL COMPONENTS ................................................................... 141
RECOMMENDED EXTERNAL COMPONENT DESCRIPTION ............................................ 142
PACKAGE DIMENSIONS ........................................................................................... 143
IMPORTANT NOTICE ................................................................................................ 144
REVISION HISTORY .................................................................................................. 145
4
Rev 4.7
WM8233
CLK10
CLK9
51 50
CLK11
IN3
52
AGND3
IN4
53
IN1
IN5
54
49 48 47
46
45
44
43
IN2
IN6
55
AGND2
AVDD1
56
AVDD2
AGND1
PIN CONFIGURATION
VREF2C 1
42 CLK8
VRLC/VBIAS 2
41 CLK7
VREF3C 3
40 CLK6
VREF1C 4
39 CLK5
SEN 5
38 CLK4
SDO 6
37 CLK3
SCK 7
36 CLK2
WM8233
SDI 8
35 CLK1
LDO2VDD 9
34 TGSYNC
LDO2GND 10
33 LDO1VDD
LDO2VOUT 11
32 LDO1GND
DSLCT2 12
31 LDO1VOUT
30 MON
MCLK 13
DSLCT1 14
16
17
18
19
20
21
22
23
24
25
26
27
28
D5N/OP9
D5P/OP8
D4N/OP7
D4P/OP6
DCLKN/OC2
DCLKP/OC1
DBGND
DBVDD
D3N/OP5
D3P/OP4
D2N/OP3
D2P/OP2
D1N/OP1
D1P/OP0
29 HZCTRL
15
ORDERING INFORMATION
DEVICE
TEMPERATURE
RANGE
PACKAGE
MOISTURE
SENSITIVITY
LEVEL
PEAK
SOLDERING
TEMPERATURE
MSL3
260C
MSL3
260C
56-lead QFN
WM8233GEFL/V
-40 to 85oC
(8 x 8 x 0.85 mm)
(Pb-free)
56-lead QFN
WM8233GEFL/RV
-40 to 85oC
(8 x 8 x 0.85 mm)
(Pb-free, tape and reel)
Reel quantity = 2,200
Rev 4.7
5
WM8233
PIN DESCRIPTION
PIN
NAME
TYPE
1
VREF2C
Analogue output
DESCRIPTION
2
VRLC/VBIAS
Analogue I/O
3
VREF3C
Analogue output
Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
4
VREF1C
Analogue output
Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Mid reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Reference voltage input/output
Enables the serial interface when high.
5
SEN
Digital input
6
SDO
Digital output
7
SCK
Digital input
Serial interface clock.
8
SDI
Digital input
Serial interface data input
9
LDO2VDD
Supply
Analogue supply
10
LDO2GND
Supply
Analogue ground
11
LDO2VOUT
Supply
LDO output
12
DSLCT2
Analogue input
Device select 2
13
MCLK
Analogue input
Master clock
14
DSLCT1
Analogue input
Device select 1
15
D5N/OP[9]
LVDS output
LVDS Data output 5 – Negative / CMOS output 9.
16
D5P/OP[8]
LVDS output
LVDS Data output 5 – Positive / CMOS output 8.
17
D4N/OP[7]
LVDS output
LVDS Data output 4 – Negative / CMOS output 7.
18
D4P/OP[6]
LVDS output
LVDS Data output 4 – Positive / CMOS output 6.
19
DCLKN/OC[2]
LVDS output
LVDS Clock Output – Negative/ CMOS flag output.
20
DCLKP/OC[1]
LVDS output
LVDS Clock Output – Positive/ CMOS clock output.
21
DBGND
Supply
Analogue ground
Analogue supply
Serial interface data output
This pin must be connected to AGND via a decoupling capacitor.
22
DBVDD
Supply
23
D3N/OP[5]
LVDS output
LVDS Data output 3 – Negative / CMOS output 5.
24
D3P/OP[4]
LVDS output
LVDS Data output 3 – Positive / CMOS output 4.
25
D2N/OP[3]
LVDS output
LVDS Data output 2 – Negative / CMOS output 3.
26
D2P/OP[2]
LVDS output
LVDS Data output 2 – Positive / CMOS output 2.
27
D1N/OP[1]
LVDS output
LVDS Data output 1 – Negative / CMOS output 1.
28
D1P/OP[0]
LVDS output
LVDS Data output 1 – Positive / CMOS output 0.
29
HZCTRL
Digital input
Internal use only. Must be connected to AGND.
30
MON
Analogue output
31
LDO1VOUT
Supply
32
LDO1GND
Supply
Analogue ground
33
LDO1VDD
Supply
Analogue supply
34
TGSYNC
Digital I/O
35
CLK1
Digital output
Sensor Timing Output 1
36
CLK2
Digital output
Sensor Timing Output 2
37
CLK3
Digital output
Sensor Timing Output 3
38
CLK4
Digital output
Sensor Timing Output 4
39
CLK5
Digital output
Sensor Timing Output 5
40
CLK6
Digital output
Sensor Timing Output 6
41
CLK7
Digital output
Sensor Timing Output 7
42
CLK8
Digital output
Sensor Timing Output 8
43
CLK9
Digital output
Sensor Timing Output 9
44
CLK10
Digital output
Sensor Timing Output 10
45
CLK11
Digital output
Sensor Timing Output 11
46
AGND3
Supply
Clock monitor
LDO output.
This pin must be connected to AGND via a decoupling capacitor.
6
Sensor Timing Sync pulse
Analogue ground
Rev 4.7
WM8233
PIN
NAME
TYPE
DESCRIPTION
47
IN1
Analogue input
Analogue input 1
48
IN2
Analogue input
Analogue input 2
49
AGND2
Supply
Analogue ground
50
AVDD2
Supply
Analogue supply
51
IN3
Analogue input
Analogue input 3
52
IN4
Analogue input
Analogue input 4
53
IN5
Analogue input
Analogue input 5
54
IN6
Analogue input
Analogue input 6
55
AVDD1
Supply
Analogue supply
56
AGND1
Supply
Analogue ground
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of
this device.
Cirrus Logic tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
MAX
Analogue supply voltage: AVDD1-2, LDO1VDD-2, DBVDD
GND - 0.3V
GND + 5V
Analogue grounds: AGND1-3, LDO1GND-LDO2GND, DBGND
GND - 0.3V
GND + 0.3V
Analogue inputs (IN1-6)
GND - 0.3V
AVDD + 0.3V
Other Analogue pins
GND - 0.3V
AVDD + 0.3V
Digital I/O pins
GND - 0.3V
AVDD + 0.3V
-40C
+85C
Operating temperature range: TA
30C max / 85% RH max
Storage temperature prior to soldering
-65C
Storage temperature after soldering
+150C
Notes:
1.
GND denotes the voltage of any ground pin.
2.
AGND, LDOGND and DBGND pins are intended to be operated at the same potential. Differential voltages
between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
Operating temperature range
Analogue Supply voltage
SYMBOL
MIN
TA
-40
AVDD1-2
2.97
TYP
3.3
MAX
UNITS
85
C
3.63
V
LDO1VDDLDO2VDD
DBVDD
Rev 4.7
7
WM8233
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 35MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
35
MSPS
Overall System Specification (including 10-bit ADC, PGA, Offset and CDS functions)
Conversion rate per channel
5
Full-scale input voltage
(see Note 1)
Input signal voltage range
Input capacitance
VIN
CIN
Full-scale transition error
ADCFS=0, Max Gain
0.12
Vp-p
ADCFS=0, Min Gain
2.0
Vp-p
ADCFS=1, Max Gain
0.18
Vp-p
ADCFS=1, Min Gain
3.0
Vp-p
SF_INP=0
AGND
AVDD
SF_INP=1
AGND
1.2
V
V
12
pF
Inputs to AGND
10
Gain = 0dB;
AGAIN[4:0] = 02(hex)
20
mV
20
mV
DGAIN[11:0] = 6AB(hex)
Zero-scale transition error
Gain = 0dB;
AGAIN[4:0] = 02(hex)
DGAIN[11:0] = 6AB(hex)
Differential non-linearity
Integral non-linearity (pk-pk/2)
Channel to channel gain matching
DNL
10-bit
+/-0.5
+/-1.5
LSB
INL
10-bit
+/-1
+/-4
LSB
Min Gain
5
Max Gain
15
Output noise
10-bit, Unity Gain
%
%
0.5
2.5
LSB rms
(Unused channels grounded)
Channel to channel crosstalk
Channel to channel offset
matching
10-bit
+/-0.5
BLC disabled
70
LSB
210
mV
Programmable Gain Amplifier
Total Resolution (Ga + Gd)
GT
12
bits
Analogue Gain
Ga
0.6 + 0.3 * AGAIN[4:0]
V/V
Max gain, each channel (Ga)
Ga MAX
AGAIN[4:0] = 1F(hex)
8.00
9.9
11.43
V/V
Min gain, each channel (Ga)
Ga MIN
AGAIN[4:0] = 0(hex)
0.44
0.6
0.77
V/V
Digital Gain
Gd
DGAIN[11:0] / 211
V/V
Max gain, each channel (Gd)
Gd MAX
DGAIN[11:0] = FFF(hex)
2
V/V
Min gain, each channel (Gd)
Gd MIN
DGAIN[11:0] = 400 (hex)
0.5
V/V
Max gain, each channel
GTMAX
AGAIN[4:0] = 1F(hex)
19.8
V/V
0.3
V/V
(Ga + Gd)
Min gain, each channel
(Ga + Gd)
DGAIN[11:0] = FFF(hex)
GTMIN
AGAIN[4:0] = 0(hex)
DGAIN[11:0] = 400 (hex)
Analogue to Digital Converter
Resolution
Speed
8
16
bits
70
MSPS
Rev 4.7
WM8233
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 35MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
VREF1C
ADCFS=0
2.05
V
ADCFS=1
2.25
V
ADCFS=0
1.25
V
ADCFS=1
1.05
V
References
Upper reference voltage
Lower reference voltage
VREF3C
Input return bias voltage
VREF2C
Diff. Reference voltage
(VREF1C-VREF3C)
VREF1C3C
1.14
1.2
1.26
V
ADCFS=0
0.72
0.8
0.88
V
ADCFS=1
1.00
1.2
1.35
Output resistance
VREF1C, VREF3C, VREF2C
V
1
VRLC/Reset-Level Clamp (RLC)
VRLC input voltage range
(see Note 2)
VRLC
SF_INP=0
0.11
3.0
SF_INP=1
0.11
1.2
V
RLC switching impedance
50
RLC short-circuit current
2
mA
RLC output resistance
2
RLC Hi-Z leakage current
VRLC = 0 to AVDD
1
RLCDAC resolution
A
5
bits
VRLC_TOP_SEL=0
0.09
V/step
VRLC_TOP_SEL=1
0.048
VRLC_TOP_SEL=0,
0.2
V
0.11
V
3.0
V
1.6
V
VRLC DNL
0.5
LSB
VRLC INL
0.5
LSB
RLCDAC step size
RLCDAC output voltage at
code 0(hex)
VRLCSTEP
VRLCBOT
VRLC_VSEL[4:0]=00000
VRLC_TOP_SEL=1,
VRLC_VSEL[4:0]=00000
RLCDAC output voltage at
code 1F(hex)
VRLCTOP
VRLC_TOP_SEL=0,
VRLC_VSEL[4:0]=11111
VRLC_TOP_SEL=1,
VRLC_VSEL[4:0]=11111
Offset DAC, Monotonicity Guaranteed
Resolution
8
Differential non-linearity
DNL
Integral non-linearity
INL
Step size
bits
0.5
1
0.5
1
2.04
Output voltage
LSB
LSB
mV/step
Code 00(hex)
-400
-250
-100
mV
Code FF(hex)
+100
+250
+400
mV
DIGITAL SPECIFICATIONS
Digital Inputs
0.7
AVDD
High level input voltage
VIH
Low level input voltage
VIL
0.2
AVDD
V
High level input current
IIH
1
A
Low level input current
IIL
1
A
Input capacitance
CI
Rev 4.7
V
5
pF
9
WM8233
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 35MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
High level output voltage
VOH
IOH = 6mA
AVDD
– 0.5
Low level output voltage
VOL
IOL = 1mA
High impedance output current
IOZ
TYP
MAX
UNIT
CMOS Outputs
V
0.5
V
1
A
TG Outputs
High level output voltage
VOHTG
Low level output voltage
VOLTG
IOL = 1mA
0.5
V
High impedance output current
IOZTG
Grounded
1
A
IOH = 1mA
AVDD
– 0.5
V
Digital IO Pins
0.7
AVDD
Applied high level input voltage
VIH
Applied low level input voltage
VIL
High level output voltage
VOH
IOH = 1mA
Low level output voltage
VOL
IOL = 1mA
Low level input current
IIL
High level input current
IIH
Input capacitance
CI
Output Impedance
RO
High impedance output current
IOZ
V
0.2
AVDD
AVDD
– 0.5
V
0.5
V
1
A
1
A
5
IO = 1mA
V
pF
Ω
22
1
A
110
Ω
LVDS Outputs
Differential load impedance
Differential steady-state output
voltage magnitude
RL
90
|VOD|
LVDS_AMP=011,
RL=100Ω
Change in the steady-state
differential output voltage
magnitude between opposite
binary states
Δ|VOD|
RL=100Ω
Steady-state common-mode
output voltage
VOC(SS)
Peak-to-peak common-mode
output
VOC(PP)
100
200
mV
15
RL=100Ω
1.25
20
mV
V
50
mV
Short-circuit output current
IOS
–6
6
mA
High-impedance state output
current
IOZ
–10
10
uA
Supply Currents
Total supply current active
SF_INP=0, SF_VRLC=0
350
mA
SF_INP=1, SF_VRLC=1
390
mA
1.2
mA
Total supply current full power
down mode
Notes:
1.
Full-scale input voltage denotes the differential input signal amplitude (VIN-VRLC in non-CDS mode, VIN-RESET level in CDS
mode) that corresponds to the ADC full-scale input level.
2.
If AVDD < 3.0V, the VRLC input voltage must not exceed AVDD.
10
Rev 4.7
WM8233
INTERNAL POWER ON RESET CIRCUIT
AVDD
VDD
INTERNAL PORB
LDOOUT
T
Power On Reset
Circuit
GND
AGND
Figure 1 Internal Power On Reset Circuit Schematic
The WM8233 includes an internal Power-On-Reset Circuit, as shown in Figure 1, which is used reset
the digital logic into a default state after power up. The POR circuit is powered from AVDD and
monitors LDOOUT. It asserts PORB low if AVDD or LDOOUT is below a minimum threshold.
LDOOUT
Vpord_on
LDOGND
AVDD
Vpora
Vpora_off
AGND
HI
INTERNAL PORB
LO
No Power
POR
Undefined
Internal
POR active
Device Ready
Internal POR active
Figure 2 Typical Power up Sequence where AVDD is Powered before LDOOUT
Figure 2 shows a typical power-up sequence where AVDD is powered up first. When AVDD rises
above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is
asserted low and the chip is held in reset. In this condition, all writes to the control interface are
ignored. When LDOOUT rises to Vpord_on, PORB is released high and all registers are in their
default state and writes to the control interface may take place. On power down, where AVDD falls
first, PORB is asserted low whenever AVDD drops below the minimum threshold Vpora_off.
SYMBOL
MIN
TYP
MAX
UNIT
Vpora
0.4
0.6
0.8
V
Vpora_off
0.4
0.6
0.8
V
Vpord_on
0.5
0.7
0.9
V
Table 1 Typical POR Operation (typical values, not tested)
Rev 4.7
11
WM8233
SIGNAL TIMING REQUIREMENTS
SERIAL CONTROL INTERFACE
tCSU
tCHO
SEN
(input)
tSCY
SCK
(input)
tSCH
tSCL
SDI
(input)
tDSU
tDHO
SDO
(output)
tDL
Figure 3 Serial Interface Timing
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SEN falling edge to SCK rising edge
tCSU
20
ns
SCK falling edge to SEN rising edge
tCHO
20
ns
SCK pulse cycle time
tSCY
83.3
ns
SCK pulse width low
tSCL
33
ns
SCK pulse width high
tSCH
33
ns
SDI to SCK set-up time
tDSU
20
ns
SDI to SCK hold time
tDHO
20
SCK falling edge to SDO transition
tDL
ns
33
ns
The internal control registers are programmable via the serial digital control interface. The register
contents can be read back via the serial interface on pin SDO.
It is recommended that a software reset is carried out after the power-up sequence, before writing to
any other register. This ensures that all registers are set to their default values.
DEVICE IDENTIFICATION
Up to 4 WM8233 devices can share a common set of serial interface pins. Each device on the
common interface bus must be given a different device ID. The device ID is set by the input pin
DSLCT2 and DSLCT1 as shown in Table 2.
DSLCT2
DSLCT1
DEVICE ID
L
L
00
L
H
01
H
L
10
H
H
11
(ID[1:0])
Table 2 Device Identification
12
Rev 4.7
WM8233
REGISTER WRITE
Figure 4 shows the sequence of operations for performing a register write. Three pins, SCK, SDI and
SEN are used for the control interface. A 16-bit address (R/W, CS0, CS1, CS2, A11 to A0) is clocked
in through SDI, MSB first, followed by an 8-bit data word (b7 to b0), also MSB first. Setting address bit
R/W to 0 indicates that the operation is a register write. The device ID bits (CS0 and CS1) indicate
which device is being written to on a shared control bus. A register write with CS2 set to 1 writes data
to all devices on the common bus. Each bit is latched on the rising edge of SCK. When the data has
been shifted into the device, a rising edge on the SEN pin transfers the data to the appropriate internal
register.
CS2
CS1
CS0
(DSLCT2)
(DSLCT1)
0
DESCRIPTION
ID[1:0]
1
Indicated a device to write data
X
X
Writes data to all devices
Table 3 Device Identification
SEN
SCK
SDI
0
CS2
R/W
CS1
CS0
CS0
A11
3bit device ID
A2
A1
A0
B7
B6
12-bit Control register address
B5
B2
B1
B0
8-bit control register data
Figure 4 Serial Interface Register Write
REGISTER READ-BACK
Figure 5 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus as
described above but with address bit R/W set to 1, followed by an 8-bit dummy data word. Writing
address (A11 to A0) will cause the contents (B7 to B0) of corresponding register in the addressed
device to be output MSB first on pin SDO (on the following edge of SCK). In this mode, the CS2
register should be set to 0.
SEN
SCK
SDI
1
0
CS1
CS0
CS0
A11
A2
A1
Hi-Z
SDO
R/W
3bit device ID
12-bit Read back register address
A0
X
B7
X: Don’t care
X
X
B6
B5
X
X
X
B2
B1
B0
Hi-Z
8-bit outputl register data
Figure 5 Serial Interface Register Read-back
Rev 4.7
13
WM8233
INPUT VIDEO SAMPLING
NON-CDS (S/H) MODE
tMCLKD
tPER
tMCLKH
tMCLKL
MCLK (input)
tVSMPD
Input Video (Input)
VSMP_RISE[5:0]
tVSMPH
VSMP_FALL[5:0]
VSMP (Internal)
Figure 6 Input Video Timing (Non-CDS (S/H) mode)
CDS MODE
tMCLKD
tPER
tMCLKH
tMCLKL
MCLK (input)
tRSMPD
Input Video (Input)
tVSMPD
RSMP_RISE[5:0]
RSMP_FALL[5:0]
tRSMPH
tRV
tVR
RSMP (Internal)
VSMP_RISE[5:0]
VSMP_FALL[5:0]
tVSMPH
VSMP (Internal)
Figure 7 Input Video Timing (CDS mode)
14
Rev 4.7
WM8233
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 35MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
MCLK cycle period (see note 2)
tPER
28.6
200
ns
MCLK high period (see note 2)
tMCLKH
0.4 * tPER
0.5 * tPER
0.6 * tPER
ns
MCLK low period (see note 2)
tMCLKL
0.4 * tPER
0.5 * tPER
0.6 * tPER
ns
MCLK rising edge to DLL tap 0
tMCLKD
18
ns
Aperture delay
tRSMPD
5
ns
tVSMPD
5
ns
(from RSMP falling edge)
Aperture delay
(from VSMP falling edge)
RSMP high period
tRSMPH
5
VSMP high period
tVSMPH
5
ns
13 *
ns
tPER/60
RSMP falling edge to VSMP rising edge
tRV
0.5
VSMP falling edge to RSMP rising edge
tVR
0.5
Output data latency
LAT
(from 1st falling edge of VSMP)
ns
ns
LVDS 10-bit 5pair mode
10
clock
Other output modes
9
clock
Notes:
1.
1clock = tPER (MCLK cycle period)
2.
MCLK cycle period and MCLK high/low period are measured at 50% of the respective rising/falling edges
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
5:0
RSMP_RISE[5:0]
01_1100
RSMP rise edge (0 to 59)
5:0
RSMP_FALL[5:0]
10_0110
RSMP fall edge (0 to 59)
5:0
VSMP_RISE[5:0]
00_1000
VSMP rise edge (0 to 59)
5:0
VSMP_FALL[5:0]
10_1000
VSMP fall edge (0 to 59)
ADDRESS
R130 (82h)
RSMP rise
R131 (83h)
RSMP fall
R132 (84h)
VSMP rise
R133 (85h)
VSMP fall
Rev 4.7
15
WM8233
OUTPUT DATA TIMING (CMOS OUTPUT)
tSKOP
OP[9:0]
(Output)
OC1
(Output)
Figure 8 CMOS Output Data Timing
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 35MHz unless otherwise stated.
PARAMETER
SYMBOL
Data output skew
TEST CONDITIONS
MIN
tSKOP
TYP
MAX
UNITS
+/-500
ps
OUTPUT DATA TIMING (LVDS OUTPUT)
tSKLV
tSKLV
D1,D2,D3
D4,D5
80%
DCLK
20%
tLVTf
tLVTr
Figure 9 LVDS Output Data Timing
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 15MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LVDS output skew
tSKLV
LVDS output signal rise time
tLVTr
1
ns
LVDS output signal fall time
tLVTf
1
ns
16
+/-250
ps
Rev 4.7
WM8233
DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on the front page of this
datasheet.
The WM8233 samples up to six inputs (IN1, IN2IN2, IN3, IN4, IN5 and IN6) simultaneously. The
device then processes the sampled video signal with respect to the video reset level or an
internally/externally generated reference level using between one and six processing channels.
Each processing channel consists of an Input Sampling block with optional Reset Level Clamping
(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and a 12-bit
Programmable Gain Amplifier (PGA).
The processing channel outputs are switched, in pairs, alternately by a 2:1 multiplexer to the three
ADC inputs.
The ADC then converts each resulting analogue signal to a digital word. The digital output from the
ADC is presented in a variety of possible output formats in LVDS and CMOS format.
On-chip control registers determine the configuration of the device, including the offsets and gains
applied to each channel. These registers are programmable via a serial interface.
The device has an automatic Black-Level Calibration function which allows the D.C. offset determined
during the optically-black pixels at the beginning of the linear sensor to be removed during the imagepixels.
The WM8233 also has an Automatic Gain Control function which automatically adjusts the gain to an
appropriate level for a detected input level.
The device incorporates a sensor timing generation function which allows CCD and CMOS sensor
timing to be controlled directly from the device using internal clock generation and register settings.
RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8233 lies within the supply voltage range (0V to AVDD),
the output signal from a CCD is usually level shifted by coupling through a capacitor, CIN. The RLC
circuit clamps the WM8233 side of this capacitor to a suitable voltage through a CMOS switch during
the CCD reset period (pixel clamping) or during the black pixels (line clamping). In order for clamping
to produce correct results the input voltage during the clamping must be a constant value.
Note that if the A.C. coupling capacitor (CIN) is used in non-CDS mode (CDS=0), then to minimise
code drift, line clamping should be used and internal input voltage buffers enabled using the SF_INP
and SF_VRLC register bit. Alternatively, if the input signal contains a stable reference/reset level, then
pixel clamping should be used, and the voltage buffers need not be enabled.
The WM8233 allows the user to control the RLC switch in a variety of ways as illustrated in Figure 10.
This figure shows a single channel; however, all 6 channels are identical, each with its own clamp
switch controlled by the common CLMP signal.
The method of control chosen depends upon the characteristics of the input video. The VRLCEN
register bit must be set to 1 to enable clamping; otherwise, the RLC switch cannot be closed (by
default VRLCEN=1).
Note that unused inputs should be left floating, or grounded through a decoupling capacitor, if reset
level clamping is used.
Rev 4.7
17
WM8233
VSMP
CIN
IN*
'Video'
sample
capacitor
CLAMP
RLC switch
CONTROL
INTERFACE
CLAMP
VSMP (if CDS=0)
RSMP (if CDS=1)
VSMP (if CDS=0)
RSMP (if CDS=1)
VSMP
VRLC/
VBIAS
'Reference'
sample
capacitor
5-BIT
RLCDAC
VRLC_VSEL[4:0]
VRLCEN
Figure 10 RLC Clamp Control Options
In CDS operation, when an input waveform has a stable reference level on every pixel, it may be
desirable to clamp every pixel during this period. Setting CLAMP=high means that the RLC switch is
closed whenever the RSMP is high, as shown in Figure 11.
In non-CDS operation, setting CLAMP=high means that the RLC switch is closed whenever the VSMP
is high, as shown in Figure 12.
INPUT VIDEO
SIGNAL
reference
("black") level
video level
Pixel counter
VSMP
Video sample taken on
fallling edge of VSMP
Reset/reference sample taken
on fallling edge of RSMP
RSMP
CLAMP
RLC switch closed
when RSMP=1
RLC switch control
"CLAMP"
Figure 11 Reset Level Clamp Operation, CDS operation shown
INPUT VIDEO
SIGNAL
video level
Pixel counter
VSMP
Video sample taken on
fallling edge of VSMP
CLAMP
RLC switch control
"CLAMP"
RLC switch closed
when VSMP=1
Figure 12 Line Clamp Operation, non-CDS operation shown
18
Rev 4.7
WM8233
CDS/NON-CDS PROCESSING
For CCD type input signals, containing a fixed reference/reset level, the signal may be processed
using Correlated Double Sampling (CDS), which will remove pixel-by-pixel common mode noise. With
CDS processing, the input waveform is sampled at two different points in time for each pixel, once
during the reference/reset level and once during the video level. To sample using CDS, register bit
CDS must be set to 1 (default = 0). This causes the signal reference to come from the video reference
level as shown in Figure 13.
For input signals that do not contain a reference/reset level (e.g. CIS sensor signals), non-CDS
processing is used (CDS=0). In this case, the video level is processed with respect to the voltage on
pin VRLC/VBIAS. The VRLC/VBIAS voltage is sampled at the same time as input samples the video
level in this mode. Note that if the A.C. coupling capacitor (CIN) is used in non-CDS mode (CDS=0),
then to minimise code drift, line clamping should be used and internal input voltage buffers enabled
using the CLPMD register bit. Alternatively, if the input signal contains a stable reference/reset level,
then pixel clamping should be used, and the voltage buffers need not be enabled.
VSMP
CIN
IN*
'Video'
sample
capacitor
CLAMP
RLC switch
CONTROL
INTERFACE
CLAMP
VSMP (if CDS=0)
RSMP (if CDS=1)
VSMP (if CDS=0)
RSMP (if CDS=1)
VSMP
VRLC/
VBIAS
'Reference'
sample
capacitor
5-BIT
RLCDAC
VRLC_VSEL[4:0]
VRLCEN
Figure 13 CDS/non-CDS Input Configuration
Rev 4.7
19
WM8233
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by a 12-bit PGA. The gain and offset for each
channel are independently programmable by writing to control bits DACINP[7:0] for the Offset DAC,
and AGAIN[4:0] and DGAIN[11:0] for the PGA.
The gain characteristic of the WM8233 PGA is shown in Figure 14.
9.9V/V
9.9
7.8
Total Gain Range
0.3V/V≦ APGA*DPGA ＜ 19.8V/V
5.4
32step
3.0
0.6
0
8
16
24
GAIN CODE (AGAIN[4:0])
31
0.6V/V
1.99V/V
1.99
DPGA GAIN (V/V)
APGA GAIN (V/V)
APGA = 0.6 + 0.3 * AGAIN[4:0]
DPGA = DGAIN[11:0] / 2^11
3072
step
1.0
0.5
1024
2048
3072
4095
GAIN CODE (DGAIN[11:0])
0.5V/V
Figure 14 PGA Gain Characteristic
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA can be offset to match the full-scale range of the differential ADC
(1.5*[VREF1C-VREF3C]).
For negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS=0. For positive going input signals
the black level should be offset to the bottom of the ADC range by setting PGAFS=1.
PGAFS= 0, PGA gain=0.9V/V, Offset = 0V
Output code
= (VRLC - VIN) * Gain * 65535/(1.5*[VREF1C-VREF3C])
PGAFS= 1, PGA gain=0.9V/V, Offset = 0V
Output code
= (VIN - VRLC) * Gain * 65535/(1.5*[VREF1C-VREF3C])
VRLC/VBIAS
1.33V
or
2.0V
VIN (INPx)
1.33V
or
2.0V
OP=0
OP=32768
VIN (INPx)
OP=65535
OP=0
OP=32768
VRLC/VBIAS
OP=65535
Figure 15 ADC Input Black Level Adjust Settings
20
Rev 4.7
WM8233
OVERALL SIGNAL FLOW SUMMARY
Figure 16 represents the processing of the video signal through the WM8233.
INPUT
INVERT
BLOCK
INPUT
SAMPLING
BLOCK
OFFSET DAC PGA
BLOCK
BLOCK
V1
+
VIN
V2
+
-
ADC BLOCK
-
D1
V3
X
16bits
analog
digital
CDS = 1
V1=V1 if PGAFS = 1
V1= -V1 if PGAFS = 0
VRESET
APGA gain
A= 0.6+0.3*AGAIN[4:0]
CDS = 0
VVRLC
VRLCEN=0
Offset
DAC
250mV*(DAC[7:0]-127.5)/127.5
VRLCEN=1
RLC
DAC
See parametrics for
DAC voltages.
VIN is IN*
VRESET is VIN sampled during reset clamp
VRLC is voltage applied to VRLC/VBIAS pin
Figure 16 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the
difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the
difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally
set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the black
level of the input signal towards 0V, producing V2.
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V3.
The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1.
Rev 4.7
21
WM8233
ADC PGA BIAS CURRENT CONTROL
The WM8233 can be changed the bias current for PGA and ADC comparator as the following step. It
would be effective for high frequency operation.
REGISTER
1.
R1C0h=1
2.
R1CBh=11h
BIT
LABEL
DEFAULT
0
User_KEY2
0
DESCRIPTION
ADDRESS
R448 (1C0h)
REGISTER
0 = User access2 disabled
1 = User access2 enabled
User access
control2
BIT
LABEL
DEFAULT
1:0
PT_COMP
01
DESCRIPTION
ADDRESS
R459 (1CBh)
Comp control
01 = Standard operation
11 = High performance operation
Other = Inhibit.
Notes:
1.
To change the Comp control, the USER_KEY2 bit must be set to ‘1’.
2.
If it’s not required to change this register, must be set as default.
22
Rev 4.7
WM8233
PLL DLL SETUP
WM8233 is supporting wide range of input frequency. PLL_EXDIV_SEL[2:0], LVDLGAIN[1:0] and
DLGAIN[1:0] must be configured by MCLK clock rate and data output format.
Note that after PLL and DLL configuration, the device must be reset as the following step.
R03[1:0]=11 (PDMD=1, PD=1)
Delay 1ms
R03[1:0]=00 (Normal operation)
Also, several LVDS operation mode is required to change internal LDO configuration to perform LVDS
clocking properly. The following register need to set to change the LDO configuration.
CMOS 10 bit
LVDS 5pair 10bit
LVDS 5pair 16bit
LVDS 3pair 10bit
LVDS 4pair 12bit
LVDS 3pair 16bit
R1B0h=1
R1B4h=12h
MCLK Clock rate
Max sample rate [MHz]
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
15MHz
DLGAIN[1:0]
LDO setting
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
35MHz
DLGAIN[1:0]
LDO setting
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
23.3MHz
DLGAIN[1:0]
LDO setting
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
21.0MHz
DLGAIN[1:0]
LDO setting
PLL_EXDIV_SEL[2:0]
LVDLGAIN[1:0]
10.5MHz
DLGAIN[1:0]
LDO setting
23.4
~
35.0
001
00
01
12h
21.1
~
23.3
001
00
01
12h
001
00
01
12h
20.0 17.5 15.0 12.5 12.0 8.33 7.5
~
~
~
~
~
~
~
21.0 19.99 17.49 14.99 12.49 11.99 8.32
000 000 000 001 001
001
00
01
12h
001
00
01
12h
001
00
01
12h
6.0
~
7.49
001
5.0
~
5.99
001
01
10
10
10
10
10
10
001
01
01
001
01
01
001
01
10
010
01
10
010
01
10
010
01
10
011
10
10
011
10
10
001
00
01
12h
001
00
01
12h
001
00
01
12h
001
00
01
12h
001
01
10
001
01
10
001
01
10
010
01
10
010
01
10
010
01
10
001
01
10
001
01
10
001
01
10
010
01
10
010
01
10
010
01
10
001
00
10
12h
001
00
10
12h
001
01
10
001
01
10
Table 4 PLL and DLL Setting
Rev 4.7
23
WM8233
REGISTER
BIT
LABEL
DEFAULT
6:4
PLL_EXDIV_
SEL[2:0]
001
DESCRIPTION
ADDRESS
R28 (1Ch)
PLL divider
control 1
Select EX DIV ratio.
Need to set according to input frequency. See Table 4.
000 = 1
001 = 2
010 = 4
011 = 8
100 = 16
101 to 111 = reserved.
REGISTER
BIT
LABEL
DEFAULT
5:4
DLGAIN[1:0]
01
DESCRIPTION
ADDRESS
R128 (80h)
REGISTER
gain control of DLL delay line
Need to set according to input frequency. See Table 4.
DLL config 1
BIT
LABEL
DEFAULT
5:4
LVDLGAIN[1:0]
00
DESCRIPTION
ADDRESS
R129 (81h)
REGISTER
gain control of LVDS DLL delay line
Need to set according to input frequency. See Table 4.
DLL config 2
BIT
LABEL
DEFAULT
0
USER_KEY
0
DESCRIPTION
ADDRESS
R432 (1B0h)
1 = User access enabled
User access
control
REGISTER
0 = User access disabled
BIT
LABEL
DEFAULT
4:0
LDO2 VSEL
1_0000
DESCRIPTION
ADDRESS
R436 (1B4h)
LDO2 control
24
1_0000 = 1.8V
1_0010 = 2.0V
Rev 4.7
WM8233
OUTPUT DATA FORMAT
The output from the WM8233 can be presented in several different formats under control of the
CMOSMODE and the LVDSMODE register. Depending on the output modes, the maximum MCLK
rate is different as shown in Table 5.
MODES
DESCRIPTION
OUTPUT
MAXIMUM
DATA RATE
MCLK RATE
1
LVDS 10-bit 5pair
MCLK x14
35MSPS
2
LVDS 16-bit 5pair
MCLK x21
23.3MSPS
3
LVDS 10-bit 3pair
MCLK 21
21.0MSPS
4
LVDS 16-bit 3pair
MCLK x42
10.5MSPS
5
LVDS 12-bit 4pair
MCLK 21
21.0MSPS
6
CMOS 10-bit
MCLK x6
15MSPS
Table 5 Output Format and Data Rate
LVDS 10-BIT 5PAIR MODE
MCLK x1
IN1
IN2
IN3
IN4
IN5
IN6
IN1
IN2
IN3
IN4
IN5
IN6
MCLK x2
ADC1
ADC2
ADC3
(ADCLK)
IN1
IN3
IN5
IN2
IN4
IN6
MCLK x2 (OCLK)
D5
D4
D3
D2
D1
DCLK
A
H
H
L
L
B
L
H
H
H
H
L
L
L
H
H
MCLK x14 (LVCK)
A
D5
S0
S1
S2
IN1[0]
IN1[1]
IN1[2]
IN1[3]
D4
IN1[4]
IN1[5]
IN1[6]
IN1[7]
IN1[8]
IN1[9]
S3
D3
S4
IN2[0]
IN2[1]
IN2[2]
IN2[3]
IN2[4]
IN2[5]
D2
IN2[6]
IN2[7]
IN2[8]
IN2[9]
IN3[0]
IN3[1]
IN3[2]
D1
IN3[3]
IN3[4]
IN3[5]
IN3[6]
IN3[7]
IN3[8]
IN3[9]
DCLK
H
H
L
L
L
H
H
D5
S0
S1
S2
IN4[0]
IN4[1]
IN4[2]
IN4[3]
D4
IN4[4]
IN4[5]
IN4[6]
IN4[7]
IN4[8]
IN4[9]
S3
D3
S4
IN5[0]
IN5[1]
IN5[2]
IN5[3]
IN5[4]
IN5[5]
D2
IN5[6]
IN5[7]
IN5[8]
IN5[9]
IN6[0]
IN6[1]
IN6[2]
D1
IN6[3]
IN6[4]
IN6[5]
IN6[6]
IN6[7]
IN6[8]
IN6[9]
DCLK
H
H
L
L
L
H
H
B
Table 6 10-bit 5pair LVDS Output Format
Rev 4.7
25
WM8233
LVDS 16-BIT 5PAIR MODE
MCLK x1
IN1
IN2
IN3
IN4
IN5
IN6
IN1
IN2
IN3
IN4
IN5
IN6
MCLK x2
ADC1
ADC2
ADC3
(ADCLK)
IN1
IN3
IN5
IN2
IN4
IN6
MCLK x3 (OCLK)
D5
D4
D3
D2
D1
DCLK
A
H
H
L
L
B
L
H
H
H
H
L
L
C
L
H
H
H
H
L
L
L
H
H
MCLK x21 (LVCK)
A
D5
S0
S1
S2
IN1[0]
IN1[1]
IN1[2]
IN1[3]
D4
IN1[4]
IN1[5]
IN1[6]
IN1[7]
IN1[8]
IN1[9]
IN1[10]
D3
IN1[11]
IN1[12]
IN1[13]
IN1[14]
IN1[15]
IN2[0]
IN2[1]
D2
IN2[2]
IN2[3]
IN2[4]
IN2[5]
IN2[6]
IN2[7]
IN2[8]
D1
IN2[9]
IN2[10]
IN211]
IN2[12]
IN2[13]
IN2[14]
IN2[15]
DCLK
H
H
L
L
L
H
H
D5
S0
S1
S2
IN3[0]
IN3[1]
IN3[2]
IN3[3]
D4
IN3[4]
IN3[5]
IN3[6]
IN3[7]
IN3[8]
IN3[9]
IN3[10]
D3
IN3[11]
IN3[12]
IN3[13]
IN3[14]
IN3[15]
IN4[0]
IN4[1]
D2
IN4[2]
IN4[3]
IN4[4]
IN4[5]
IN4[6]
IN4[7]
IN4[8]
D1
IN4[9]
IN4[10]
IN411]
IN4[12]
IN4[13]
IN4[14]
IN4[15]
DCLK
H
H
L
L
L
H
H
D5
S0
S1
S2
IN5[0]
IN5[1]
IN5[2]
IN5[3]
D4
IN5[4]
IN5[5]
IN5[6]
IN5[7]
IN5[8]
IN5[9]
IN5[10]
D3
IN5[11]
IN5[12]
IN5[13]
IN5[14]
IN5[15]
IN6[0]
IN6[1]
D2
IN6[2]
IN6[3]
IN6[4]
IN6[5]
IN6[6]
IN6[7]
IN6[8]
D1
IN6[9]
IN6[10]
IN611]
IN6[12]
IN6[13]
IN6[14]
IN6[15]
DCLK
H
H
L
L
L
H
H
B
C
Table 7 16-bit 5pair LVDS Output Format
26
Rev 4.7
WM8233
LVDS 10-BIT 3PAIR MODE
MCLK x1
IN1
IN2
IN3
IN4
IN5
IN6
IN1
IN2
IN3
IN4
IN5
IN6
MCLK x2
ADC1
ADC2
ADC3
(ADCLK)
IN1
IN3
IN5
IN2
IN4
IN6
MCLK x3 (OCLK)
D3
D2
D1
DCLK
A
H
H
L
L
B
L
H
H
H
H
L
L
C
L
H
H
H
H
L
L
L
H
H
MCLK x21 (LVCK)
A
D3
S0
IN1[0]
IN1[1]
IN1[2]
IN1[3]
IN1[4]
IN1[5]
D2
IN1[6]
IN1[7]
IN1[8]
IN1[9]
IN2[0]
IN2[1]
IN2[2]
D1
IN2[3]
IN2[4]
IN2[5]
IN2[6]
IN2[7]
IN2[8]
IN2[9]
DCLK
H
H
L
L
L
H
H
D3
S0
IN3[0]
IN3[1]
IN3[2]
IN3[3]
IN3[4]
IN3[5]
D2
IN3[6]
IN3[7]
IN3[8]
IN3[9]
IN4[0]
IN4[1]
IN4[2]
D1
IN4[3]
IN4[4]
IN4[5]
IN4[6]
IN4[7]
IN4[8]
IN4[9]
DCLK
H
H
L
L
L
H
H
D3
S0
IN5[0]
IN5[1]
IN5[2]
IN5[3]
IN5[4]
IN5[5]
D2
IN5[6]
IN5[7]
IN5[8]
IN5[9]
IN6[0]
IN6[1]
IN6[2]
D1
IN6[3]
IN6[4]
IN6[5]
IN6[6]
IN6[7]
IN6[8]
IN6[9]
DCLK
H
H
L
L
L
H
H
B
C
Rev 4.7
27
WM8233
LVDS 16-BIT 3PAIR MODE
MCLK x1
IN1
IN2
IN3
IN4
IN5
IN6
IN1
IN2
IN3
IN4
IN5
IN6
MCLK x2
ADC1
ADC2
ADC3
(ADCLK)
IN1
IN3
IN5
IN2
IN4
IN6
MCLK x6 (OCLK)
D3
D2
D1
DCLK
A
B
D
C
E
F
HHL L L HHHHL L L HH HHL L L HHHHL L L HHHHL L L HH HHL L L HH
MCLK x42
(LVCK)
A
D3
S0
S1
S2
IN1[0]
IN1[1]
IN1[2]
IN1[3]
D2
IN1[4]
IN1[5]
IN1[6]
IN1[7]
IN1[8]
IN1[9]
IN1[10]
D1
IN1[11]
IN1[12]
IN1[13]
IN1[14]
IN1[15]
S3
S4
DCLK
H
H
L
L
L
H
H
D3
S0
S1
S2
IN2[0]
IN2[1]
IN2[2]
IN2[3]
D2
IN2[4]
IN2[5]
IN2[6]
IN2[7]
IN2[8]
IN2[9]
IN2[10]
D1
IN2[11]
IN2[12]
IN2[13]
IN2[14]
IN2[15]
S3
S4
DCLK
H
H
L
L
L
H
H
D3
S0
S1
S2
IN6[0]
IN6[1]
IN6[2]
IN6[3]
D2
IN6[4]
IN6[5]
IN6[6]
IN6[7]
IN6[8]
IN6[9]
IN6[10]
D1
IN6[11]
IN6[12]
IN6[13]
IN6[14]
IN6[15]
S3
S4
DCLK
H
H
L
L
L
H
H
B
F
Table 8 16-bit 3pair LVDS Output Format
Note:
A: IN1, B:IN2, C:IN3, D:IN4, E:IN5, F:IN6.
28
Rev 4.7
WM8233
LVDS 12-BIT 4PAIR MODE
MCLK x1
IN1
IN2
IN3
IN4
IN5
IN6
IN1
IN2
IN3
IN4
IN5
IN6
MCLK x2
ADC1
ADC2
ADC3
(ADCLK)
IN1
IN3
IN5
IN2
IN4
IN6
MCLK x3 (OCLK)
D4
D3
D2
D1
DCLK
A
H
H
L
L
B
L
H
H
H
H
L
L
C
L
H
H
H
H
L
L
L
H
H
MCLK x21 (LVCK)
A
D4
S0
IN1[0]
IN1[1]
IN1[2]
IN1[3]
IN1[4]
IN1[5]
D3
IN1[6]
IN1[7]
IN1[8]
IN1[9]
IN1[10]
IN1[11]
S1
D2
S2
S3
IN2[0]
IN2[1]
IN2[2]
IN2[3]
IN2[4]
D1
IN2[5]
IN2[6]
IN2[7]
IN2[8]
IN2[9]
IN2[10]
IN2[11]
DCLK
H
H
L
L
L
H
H
D4
S0
IN3[0]
IN3[1]
IN3[2]
IN3[3]
IN3[4]
IN3[5]
D3
IN3[6]
IN3[7]
IN3[8]
IN3[9]
IN3[10]
IN3[11]
S1
D2
S2
S3
IN4[0]
IN4[1]
IN4[2]
IN4[3]
IN4[4]
D1
IN4[5]
IN4[6]
IN4[7]
IN4[8]
IN4[9]
IN4[10]
IN4[11]
DCLK
H
H
L
L
L
H
H
D4
S0
IN5[0]
IN5[1]
IN5[2]
IN5[3]
IN5[4]
IN5[5]
D3
IN5[6]
IN5[7]
IN5[8]
IN5[9]
IN5[10]
IN5[11]
S1
D2
S2
S3
IN6[0]
IN6[1]
IN6[2]
IN6[3]
IN6[4]
D1
IN6[5]
IN6[6]
IN6[7]
IN6[8]
IN6[9]
IN6[10]
IN6[11]
DCLK
H
H
L
L
L
H
H
B
C
Table 9 12-bit 4pair LVDS Output Format
Rev 4.7
29
WM8233
LVDS DATA OUTPUT ORDER
The WM8233 can be presented 2 types of LVDS data output order, Ascending order mode and
Descending order mode as the following.
Ascending Order Mode
Decending Order Mode
10bit 5pair mode
10bit 5pair mode
D5
S0
S1
S2
IN1[0]
IN1[1]
IN1[2]
IN1[3]
D5
S4
S3
S2
IN1[9]
IN1[8]
IN1[7]
D4
IN1[4]
IN1[5]
IN1[6]
IN1[7]
IN1[8]
IN1[9]
S3
D4
IN1[5]
IN1[4]
IN1[3]
IN1[2]
IN1[1]
IN1[0]
S1
D3
S4
IN2[0]
IN2[1]
IN2[2]
IN2[3]
IN2[4]
IN2[5]
D3
S0
IN2[9]
IN2[8]
IN2[7]
IN2[6]
IN2[5]
IN2[4]
D2
IN2[6]
IN2[7]
IN2[8]
IN2[9]
IN3[0]
IN3[1]
IN3[2]
D2
IN2[3]
IN2[2]
IN2[1]
IN2[0]
IN3[9]
IN3[8]
IN3[7]
D1
IN3[3]
IN3[4]
IN3[5]
IN3[6]
IN3[7]
IN3[8]
IN3[9]
D1
IN3[6]
IN3[5]
IN3[4]
IN3[3]
IN3[2]
IN3[1]
IN3[0]
DCLK
H
H
L
L
L
H
H
DCLK
H
H
L
L
L
H
H
S1
S0
16bit 5pair mode
IN1[6]
16bit 5pair mode
D5
S0
S1
S2
IN1[0]
IN1[1]
IN1[2]
IN1[3]
D5
D4
IN1[4]
IN1[5]
IN1[6]
IN1[7]
IN1[8]
IN1[9] IN1[10]
D4
IN1[11] IN1[10] IN1[9]
IN1[8]
IN1[7]
D3
IN1[11] IN1[12] IN1[13] IN1[14] IN1[15] IN2[0]
IN2[1]
D3
IN1[4]
IN1[1]
IN1[0] IN2[15] IN2[14]
D2
IN2[2]
IN2[8]
D2
IN2[13] IN2[12] IN2[11] IN2[10] IN2[9]
IN2[8]
IN2[7]
D1
IN2[9] IN2[10] IN211] IN2[12] IN2[13] IN2[14] IN2[15]
D1
IN2[6]
IN2[5]
IN2[4]
IN2[3]
IN2[2]
IN2[1]
IN2[0]
DCLK
H
H
L
L
L
H
H
DCLK
H
IN2[3]
IN2[4]
IN2[5]
IN2[6]
IN2[7]
H
L
L
L
H
H
10bit 3pair mode
S2
IN1[3]
IN1[2]
IN1[15] IN1[14] IN1[13] IN1[12]
IN1[6]
IN1[5]
10bit 3pair mode
D3
S0
IN1[0]
IN1[1]
IN1[2]
IN1[3]
IN1[4]
IN1[5]
D3
S0
IN1[9]
IN1[8]
IN1[7]
IN1[6]
IN1[5]
IN1[4]
D2
IN1[6]
IN1[7]
IN1[8]
IN1[9]
IN2[0]
IN2[1]
IN2[2]
D2
IN1[3]
IN1[2]
IN1[1]
IN1[0]
IN2[9]
IN2[8]
IN2[7]
D1
IN2[3]
IN2[4]
IN2[5]
IN2[6]
IN2[7]
IN2[8]
IN2[9]
D1
IN2[6]
IN2[5]
IN2[4]
IN2[3]
IN2[2]
IN2[1]
IN2[0]
DCLK
H
H
L
L
L
H
H
DCLK
H
H
L
L
L
H
H
S3
S2
16bit 3pair mode
16bit 3pair mode
D3
S0
S1
S2
IN1[0]
IN1[1]
IN1[2]
IN1[3]
D3
D2
IN1[4]
IN1[5]
IN1[6]
IN1[7]
IN1[8]
IN1[9] IN1[10]
D2
IN1[11] IN1[10] IN1[9]
D1
IN111] IN1[12] IN1[13] IN1[14] IN1[15]
DCLK
H
S4
IN1[15] IN1[14] IN1[13] IN1[12]
IN1[8]
IN1[7]
IN1[6]
IN1[5]
S3
S4
D1
IN1[4]
IN1[3]
IN1[2]
IN1[1]
IN1[0]
S1
S0
DCLK
H
H
L
L
L
H
H
IN1[6]
H
L
L
L
H
H
IN1[3]
IN1[4]
IN1[5]
D4
S3
IN1[11] IN1[10] IN1[9]
IN1[8]
IN1[7]
S1
D3
IN1[5]
IN1[4]
IN1[1]
IN1[0]
S2
IN2[11] IN2[10] IN2[9]
IN2[8]
IN2[7]
12bit 4pair mode
12bit 4pair mode
D4
S0
IN1[0]
IN1[1]
IN1[2]
D3
IN1[6]
IN1[7]
IN1[8]
IN1[9] IN1[10] IN1[11]
D2
S2
S3
IN2[0]
IN2[1]
IN2[2]
IN2[4]
D2
S1
S0
D1
IN2[5]
IN2[6]
IN2[7]
IN2[8]
IN2[9] IN2[10] IN211]
D1
IN2[6]
IN2[5]
IN2[4]
IN2[3]
IN2[2]
IN2[1]
IN2[0]
DCLK
H
H
L
L
DCLK
H
H
L
L
L
H
H
REGISTER
L
IN2[3]
H
H
BIT
LABEL
DEFAULT
3
LVDSORDER
0
IN1[3]
IN1[2]
DESCRIPTION
ADDRESS
R7 (07h)
output
control
30
control LVDS data output order
0 = descending order
1 = ascending order
Rev 4.7
WM8233
CMOS OUTPUT MODE
MCLK x1
IN1
IN2
IN3
IN4
IN5
IN6
IN1
IN2
IN3
IN4
IN5
IN6
MCLK x2
ADC1
ADC2
ADC3
(ADCLK)
IN1
IN3
IN5
IN2
IN4
IN6
MCLK x6 (OCLK)
OP9
OP8
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
A
MCLK x6 (OC1)
A
OP9
IN1[9]
IN2[9]
IN3[9]
IN4[9]
IN5[9]
IN6[9]
OP8
IN1[8]
IN2[8]
IN3[8]
IN4[8]
IN5[8]
IN6[8]
OP7
IN1[7]
IN2[7]
IN3[7]
IN4[7]
IN5[7]
IN6[7]
OP6
IN1[6]
IN2[6]
IN3[6]
IN4[6]
IN5[6]
IN6[6]
OP5
IN1[5]
IN2[5]
IN3[5]
IN4[5]
IN5[5]
IN6[5]
OP4
IN1[4]
IN2[4]
IN3[4]
IN4[4]
IN5[4]
IN6[4]
OP3
IN1[3]
IN2[3]
IN3[3]
IN4[3]
IN5[3]
IN6[3]
OP2
IN1[2]
IN2[2]
IN3[2]
IN4[2]
IN5[2]
IN6[2]
OP1
IN1[1]
IN2[1]
IN3[1]
IN4[1]
IN5[1]
IN6[1]
OP0
IN1[0]
IN2[0]
IN3[0]
IN4[0]
IN5[0]
IN6[0]
Table 10 10-bit CMOS Output Format
CLOCK TIMING CONFIGURATION
The RSMP signal, VSMP signal and clock output from CLK pin are generated internally by 60 tap DLL
circuit. The rising and falling timing of each clock is set by DLL tap setting. The following setting and
timing chart shows example configuration for RSMP, VSMP and CLK1.
RSMP: 0x82(RSMP_RISE)=0x07(dec7), 0x83(RSMP_FALL)=0x10(dec16)
VSMP: 0x84(VSMP_RISE)=0x1C(dec28), 0x85(VSMP_FALL=0x29(dec41)
CLK1: 0x87(CLK1_RISE)=0x39(dec57), 0x88(CLK1_FALL)=0x0B(dec11)
Rev 4.7
31
WM8233
tMCLKD Tap 0
MCLK (input)
Tap 0
tPER
tPER/60
7
16
RSMP
28
41
VSMP
57
11
57
CLK1
DLL TAP
59 0 1 2
30
59 0 1
Figure 17 Clock Timing Configuration
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
R130 (82h) RSMP
rise
5:0
RSMP_RISE
[5:0]
01_1100
RSMP rise edge
R131 (83h) RSMP
fall
5:0
RSMP_FALL
[5:0]
10_0110
RSMP fall edge
R132 (84h)
5:0
VSMP_RISE
[5:0]
11_0111
VSMP rise edge
5:0
VSMP_FALL
[5:0]
00_1000
VSMP fall edge
R134 (86h)
TGCKO rise
5:0
TCLKO_RISE
[5:0]
11_0111
TCLKO rise edge
R135 (87h)
5:0
CLK1_RISE[5:0]
00_1010
CLK1 rise edge
5:0
CLK1_FALL[5:0]
01_1001
CLK1 fall edge
5:0
CLK2_RISE[5:0]
01_1001
CLK2 rise edge
R138 (8Ah)
CLK2fall
5:0
CLK2_FALL[5:0]
10_1000
CLK2 fall edge
R139 (8Bh)
5:0
CLK3_RISE[5:0]
10_1000
CLK3 rise edge
5:0
CLK3_FALL[5:0]
00_1010
CLK3 fall edge
5:0
CLK4_RISE[5:0]
00_0000
CLK4 rise edge
5:0
CLK5_RISE[5:0]
00_1010
CLK5 rise edge
5:0
CLK5_FALL[5:0]
10_1000
CLK5 fall edge
R145 (91h)
CLK6 rise
5:0
CLK6_RISE[5:0]
00_1010
CLK6 rise edge
R146 (92h)
CLK6 fall
5:0
CLK6_FALL[5:0]
10_1000
CLK6 fall edge
ADDRESS
VSMP rise
R133 (85h)
VSMP fall
CLK1 rise
R136 (88h)
CLK1 fall
R137 (89h)
CLK2 rise
CLK3 rise
R140 (8Ch)
CLK3 fall
R141 (8Dh)
CLK4 rise
R143 (8Fh)
CLK5 rise
R144 (90h)
CLK5 fall
SENSOR TIMING GENERATION
The WM8233 provides two types of clock internally. C_CK* are high speed clocks, these clocks can
set the clock phase by using fine pitch phase control. P_CK* are pixel rate signals which is selected
32
Rev 4.7
WM8233
by PO0 to PO7. The WM8233 has eleven sensor TG outputs pins. CLK1 is for clock type use only.
CLK2, CLK3, CLK4, CLK5 and CLK6 are selectable high speed type signal or pulse type signal. CLK7,
CLK8, CLK9, CLK10 and CLK11 are pulse type use only.
C_CK1
C_CK2
C_CK3
C_CK4
inv
en
OE
CLK1
Delay
C_CK5
C_CK6
inv
en
OE
CLK2
Delay
inv
en
OE
CLK3
Delay
inv
en
OE
CLK4
Delay
inv
en
OE
CLK5
Delay
inv
en
OE
CLK6
inv
en
Delay
P_CK2
P_CK3
P_CK4
P_CK5
P_CK6
CLK7
Delay
inv
en
OE
CLK8
Delay
P_CK7
P_CK8
P_CK9
P_CK10
P_CK11
inv
en
OE
CLK9
Delay
inv
en
OE
CLK10
Delay
tMCLKD
inv
OE
en
PO0
PO1
PO2
PO3
PO4
PO5
PO6
PO7
MAP
OE
CLK11
tPER
MCLK (input)
VSMP_RISE[5:0]
VSMP_FALL[5:0]
VSMP (Internal)
2*tPER/60
TGCK (Internal)
Duty=50%
Pixel Counter
(Internal)
CK_RISE[5:0]
CK1,2,3,4,5,6
(Clock Output)
CK_FALL[5:0]
TCLKO_RISE[5:0]
TGCO (Internal)
CK2-11
(Pulse output)
Duty=50%
DEL_PCK [1:0]
Figure 18 TG Output Timing
Rev 4.7
33
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
5:0
DEL_PCK*[1:0]
00
R135 (81h)
5:0
CLK*_RISE[5:0]
CLK* rise edge (0 to 59)
– R146 (92h)
5:0
CLK*_FALL[5:0]
CLK* fall edge (0 to 59)
ADDRESS
R176 (B0h)
– R177 (B1h)
control delay for pulse output
00 = 0nsec, 01 = 1nsec, 10 = 2nsec, 11 = 3nsec
TG MASTER MODE OPERATION
In master mode, line length is defined by LLENGTH register.
L-1
L
0
1
2
P2
P1
L-1
L
0
1
2
P2
0
1
2
3
TGEN(Serial I/F)
VSMP
TGCK
Pixel counter
2*tPER/60
VSMP
TGCK
P1
master
L=LLENGTH[14:0]
pixcnt=0
TGSYNC(Output)
pixcnt=0
TPn=P1
pixcnt=0
TPm=P2
POn(Internal)
CLKn(TG pulse out)
PO_ Flag
(LVDS/CMOS out)
tPCKD
tTRIGD
FLAGPIX=P1
Datatrig(Internal)
Datatrig
(LVDS/CMOS output)
tTRIGD
Figure 19 Master Mode Pixel Counter and Line Start Timing
TG SLAVE MODE OPERATION
In slave mode, line length depends on TGSYNC input. The pixel counter is reset by TGSYNC input.
slave
2*tPER/60
VSMP
TGCK
tSCKSY
TGSYNC
tSYH
TGEN(Serial I/F)
VSMP
TGCK
pixcnt=0
pixcnt=0
Q=OFFSET[3:0]
TPm=P2
P2
Q
Q+1
Q+2
Q+3
TPn=P1
P1
32767
P2
0
tSYL
pixcnt=0
P1
Pixel counter
tSYH
tCOUNTD
Q
Q+1
Q+2
Q+3
Linestart(Internal)
Q
Q+1
Q+2
Q+3
TGSYNC(Input)
POn(Internal)
CLKn(TG pulse out)
PO_Flag
(LVDS/CMOS out)
Flag(Internal)
Flag
(LVDS/CMOS out)
tPCKD
tTRIGD
FLAGPIX=P1
tTRIGD
Figure 20 Slave Mode Pixel Counter and Line Start Timing
34
Rev 4.7
WM8233
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 35MHz unless otherwise stated.
PARAMETER
SYMBOL
TGSYNC Setup time
TEST CONDITIONS
tSCKSY
MIN
TYP
MAX
UNITS
tPER / 4
tPER / 2
3 * tPER / 4
ns
(only for slave mode)
Pixel counter start timing
tCOUNTD
2
clock
(only for slave mode)
TGSYNC high period
tSYH
1
clock
tSYL
1
clock
(only for slave mode)
TGSYNC low period
(only for slave mode)
Data trigger timing delay
tTRIGD
TG pulse output timing delay
LVDS 10-bit 5pair mode
14
clock
Other output mode
13
clock
2
clock
tPCKD
Note:
1clock = tPER (MCLK cycle period)
REGISTER
BIT
LABEL
DEFAULT
7:4
OFFSET[3:0]
0000
2
POLSYNC
0
1
TGMD
0
0
TG_EN
0
DESCRIPTION
ADDRESS
R160 (A0h)
offset count (only for slave mode)
polarity of Sync signal
0 = POSITIVE EDGE, 1 = NEGATIVE EDGE
TG operation mode
0 = SLAVE, 1 = MASTER
TG enable
0 = DISABLE, 1 = ENABLE
R161 (A1h)
7:0
LLENGTH[7:0]
0000_0000
the number of pixels in 1line (only for master mode)
R162 (A2h)
6:0
LLENGTH[6:0]
000_0000
the number of pixels in 1line (only for master mode)
TG PULSE AND TRIGGER DATA
C_CK1
C_CK2
VSMP
TGCK
pixcnt
P_CK1
(Selected from P0-P7)
P_CK2
(Selected from P0-P7)
TP1
TP2
TP1
High@TP1
TP3
FLUGPIX
TP3
TP4
Low@TP2
TP3
TP3
High@TP3
P_CK3
(Selected from P0-P7)
TP5
High@TP4
Low@TP3
TP6
TP5
TP4
TP2
Low@TP5
TP4
TP6
High@TP4
DataTrig
(FLUGPIX is selected )
Datatrig_out
(FLUGPIX is selected )
DataTrig
(P_CK1 is Selectd )
DataTrig
(P_CK1 is Selectd )
Low@TP6
tTRIGD
tTRIGD
tTRIGD
Figure 21 TG Pulse Toggle Setting and Data Trigger Timing
Rev 4.7
35
WM8233
TG PULSE
The WM8233 can generate 8 TG pulses internally (PO0 – PO7). These pulses are generated by the
toggle point setting registers (TP*) and polarity setting registers (POL*_PO*). WM8233 provided up to
32 toggle point by using TP0 to TP31. PO0-PO7 signals can be assigned to CLK2-CLK11 by
SEL_PCK* and SEL_CLK* register.
TRIGGER DATA
The WM8233 can implement trigger data in LVDS output.(S0,S1,S2,S3 and S4) This can be selected
by two methods. One is the FLAGPIX register which can be set one pixel for each line. The other is to
apply a PO* pulse. Figure 21 shows the trigger data implementation timing.
CHANNEL ID
Also WM8233 can implement channel identification data instead of trigger data. Table 11 shows the
matrix of input channel and channel ID.
ID[2]
ID[1]
ID[0]
IN1
0
0
1
IN2
0
1
0
IN3
0
1
1
IN4
1
0
0
IN5
1
0
1
IN6
1
1
0
Table 11 Channel ID
Channel ID can be assigned to flag data (S0, S1, S2, S3 or S4). The following is the example of
channel ID assignment.
Example: Assigned channel ID to flag data as ID[2] =S1, ID[1]=S2, ID[0]=S3.
If output data is as follows, channel ID will be IN1. (i.e. ID[2] =S1=0, ID[1]=S2=0, ID[0]=S3=1)
A
36
D5
S0
S1
S2
IN1[0]
IN1[1]
IN1[2]
IN1[3]
D4
IN1[4]
IN1[5]
IN1[6]
IN1[7]
IN1[8]
D3
S4
IN2[0]
IN2[1]
IN2[2]
IN2[3]
IN2[4]
IN2[5]
D2
IN2[6]
IN2[7]
IN2[8]
IN2[9]
IN3[0]
IN3[1]
IN3[2]
D1
IN3[3]
IN3[4]
IN3[5]
IN3[6]
IN3[7]
IN3[8]
IN3[9]
DCLK
H
H
L
L
L
H
H
S3
Rev 4.7
WM8233
Channel ID Setting Limitation
There are some notices to assign channel ID. It’s depending on LVDS output format. (refer to
OUTPUT DATA FORMAT)
1) 10-bit 5pair mode LVDS output
In this mode, channel ID will be IN1 or IN4 only.
Case-1 ID indicate IN1
A
D5
S0
S1
S2
IN1[0]
IN1[1]
IN1[2]
IN1[3]
D4
IN1[4]
IN1[5]
IN1[6]
IN1[7]
IN1[8]
IN1[9]
S3
D3
S4
IN2[0]
IN2[1]
IN2[2]
IN2[3]
IN2[4]
IN2[5]
D2
IN2[6]
IN2[7]
IN2[8]
IN2[9]
IN3[0]
IN3[1]
IN3[2]
D1
IN3[3]
IN3[4]
IN3[5]
IN3[6]
IN3[7]
IN3[8]
IN3[9]
DCLK
H
H
L
L
L
H
H
IN4[3]
Case-2 ID indicate IN4
B
D5
S0
S1
S2
IN4[0]
IN4[1]
IN4[2]
D4
IN4[4]
IN4[5]
IN4[6]
IN4[7]
IN4[8]
IN4[9]
S3
D3
S4
IN5[0]
IN5[1]
IN5[2]
IN5[3]
IN5[4]
IN5[5]
D2
IN5[6]
IN5[7]
IN5[8]
IN5[9]
IN6[0]
IN6[1]
IN6[2]
D1
IN6[3]
IN6[4]
IN6[5]
IN6[6]
IN6[7]
IN6[8]
IN6[9]
DCLK
H
H
L
L
L
H
H
2) 16-bit 5pair mode LVDS output
In this mode, channel ID will be IN1 or IN3 or IN5.
A
D5
S0
S1
S2
IN1[0]
IN1[1]
IN1[2]
IN1[3]
D4
IN1[4]
IN1[5]
IN1[6]
IN1[7]
IN1[8]
IN1[9]
IN1[10]
D3
IN1[11]
IN1[12]
IN1[13]
IN1[14]
IN1[15]
IN2[0]
IN2[1]
D2
IN2[2]
IN2[3]
IN2[4]
IN2[5]
IN2[6]
IN2[7]
IN2[8]
D1
IN2[9]
IN2[10]
IN211]
IN2[12]
IN2[13]
IN2[14]
IN2[15]
DCLK
H
H
L
L
L
H
H
S0
S1
S2
IN3[0]
IN3[1]
IN3[2]
IN3[3]
B
D5
Rev 4.7
D4
IN3[4]
IN3[5]
IN3[6]
IN3[7]
IN3[8]
IN3[9]
IN3[10]
D3
IN3[11]
IN3[12]
IN3[13]
IN3[14]
IN3[15]
IN4[0]
IN4[1]
D2
IN4[2]
IN4[3]
IN4[4]
IN4[5]
IN4[6]
IN4[7]
IN4[8]
D1
IN4[9]
IN4[10]
IN411]
IN4[12]
IN4[13]
IN4[14]
IN4[15]
DCLK
H
H
L
L
L
H
H
37
WM8233
C
REGISTER
BIT
D5
S0
S1
S2
IN5[0]
IN5[1]
IN5[2]
IN5[3]
D4
IN5[4]
IN5[5]
IN5[6]
IN5[7]
IN5[8]
IN5[9]
IN5[10]
D3
IN5[11]
IN5[12]
IN5[13]
IN5[14]
IN5[15]
IN6[0]
IN6[1]
D2
IN6[2]
IN6[3]
IN6[4]
IN6[5]
IN6[6]
IN6[7]
IN6[8]
D1
IN6[9]
IN6[10]
IN611]
IN6[12]
IN6[13]
IN6[14]
IN6[15]
DCLK
H
H
L
L
L
H
H
LABEL
DEFAULT
SEL_PCK*
000
DESCRIPTION
ADDRESS
R171 (ABh)
pulse mapping control for CLK*
000 = PO1, 001 = PO2, 010 = PO3, 011 = PO4
- R175 (AFh)
100 = PO5, 101 = PO6, 110 = PO7, 111 = PO8
SEL_CLK*
0
EN_TP*
0
mapping control
0 = output clock, 1 = output pulse
R208 (D0h)
7
enable toggle point
0 = disable and subsequent toggle point
- R270 (10Eh)
1 = enable toggle point
6:0
R271 (10Fh)
pixel count of toggle point
TP*
polarity of PO* pulse at TP*
POL*_PO*
- R310 (136h)
R163 (A3h)
7:0
FLAGPIX[7:0]
0000_0000
flag pixel
R164 (A4h)
6:0
FLAGPIX[6:0]
000_0000
flag pixel
R180 (B4h)
3:0
SEL_FLAG[3:0]
0000
select signal to be output as datatrig
0xxx = flagpix, 1000 = PO0, 1001 = PO1, 1010 = PO2,
1011 = PO3, 1100 = PO4, 1101 = PO5, 1110 = PO6
1111 = PO7
R10 (0Ah)
7:4
FLAG_S1[3:0]
0001
output dataflag as S1
(valid only LVDS mode)
0000 = always low, 0001 = start flag
0010 = reserved, 0011 = reserved, 0100 = reserved
0101 = channel ID[0], 0110 = channel ID[1],
0111 = channel ID[2], 1000 = reserved
1001 = reserved, 1010 = reserved, 1011 = reserved,
1100 = reserved, 1101 = reserved, 1110 = reserved
1111 = always high
3:0
FLAG_S0[3:0]
0000
output dataflag as S0
(valid only LVDS mode)
0000 = always low, 0001 = start flag
0010 = reserved, 0011 = reserved, 0100 = reserved
0101 = channel ID[0], 0110 = channel ID[1],
0111 = channel ID[2], 1000 = reserved
1001 = reserved, 1010 = reserved, 1011 = reserved,
1100 = reserved, 1101 = reserved, 1110 = reserved
1111 = always high
38
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
7:4
FLAG_S3[3:0]
0001
DESCRIPTION
ADDRESS
R11 (0Bh)
output dataflag as S3
(valid only LVDS mode)
0000 = always low, 0001 = start flag
0010 = reserved, 0011 = reserved, 0100 = reserved
0101 = channel ID[0], 0110 = channel ID[1],
0111 = channel ID[2], 1000 = reserved
1001 = reserved, 1010 = reserved, 1011 = reserved,
1100 = reserved, 1101 = reserved, 1110 = reserved
1111 = always high
3:0
FLAG_S2[3:0]
0000
output dataflag as S2
(valid only LVDS mode)
0000 = always low, 0001 = start flag
0010 = reserved, 0011 = reserved, 0100 = reserved
0101 = channel ID[0], 0110 = channel ID[1],
0111 = channel ID[2], 1000 = reserved
1001 = reserved, 1010 = reserved, 1011 = reserved,
1100 = reserved, 1101 = reserved, 1110 = reserved
1111 = always high
R12 (0Ch)
3:0
FLAG_S4[3:0]
0000
output dataflag as S4
(valid only LVDS mode)
0000 = always low, 0001 = start flag
0010 = reserved, 0011 = reserved, 0100 = reserved
0101 = channel ID[0], 0110 = channel ID[1],
0111 = channel ID[2], 1000 = reserved
1001 = reserved, 1010 = reserved, 1011 = reserved,
1100 = reserved, 1101 = reserved, 1110 = reserved
1111 = always high
Rev 4.7
39
WM8233
TG MASK TIMING
The WM8233 has a TG clock mask function. M1, M2 and M3 pulses specify the mask period; T1 and
T2 pulses are used for changing the signal polarity during the mask period. C_CK1 and C_CK2 are
applied to the M pulse only; they cannot be applied to the T pulse. C_CK3 and C_CK4 are applied to
M1 and T1; C_CK5 and C_CK6 are applied to M2 and T2. The mask timing is synchronized with
TGCKO rise edge.
CKGO3
(Internal)
VSMP
TGCK
pixcnt
N-1
N
N+1
N+2
N+3
P1 TP1
P2 TP2
M-2
M
M-1
M+1
M+2
M+3
k
TGCKO
M-1
M2@TGCK
M2@TGCK
O
CKGO3 + M2
T2@TGCK
T2@TGCK
O
C_CK3
fall@count M-1
rise@count N
TP1
Low@TP1
TP2
High@TP2
Figure 22 TG Mask Timing
TG CLOCK
C_CK1
APPLIED
APPLIED
“M” PULSE
“T” PULSE
M3
none
M1
T1
M2
T2
C_CK2
C_CK3
C_CK4
C_CK5
C_CK6
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
R195 (C3h)
7:0
M1_RISE[7:0]
0000_0000
M1 pulse rise count (mask start)
R196 (C4h)
6:0
M1_RISE[6:0]
000_0000
M1 pulse rise count (mask start)
R197 (C5h)
7:0
M1_FALL[7:0]
0000_0000
M1 pulse fall count (mask end)
R198 (C6h)
6:0
M1_FALL[6:0]
000_0000
M1 pulse fall count (mask end)
R199 (C7h)
7:0
M2_RISE[7:0]
0000_0000
M2 pulse rise count (mask start)
R200 (C8h)
6:0
M2_RISE[6:0]
000_0000
M2 pulse rise count (mask start)
R201 (C9h)
7:0
M2_FALL[7:0]
0000_0000
M2 pulse fall count (mask end)
R202 (CAh)
6:0
M2_FALL[6:0]
000_0000
M2 pulse fall count (mask end)
R203 (CBh)
7:0
M3_RISE[7:0]
0000_0000
M3 pulse rise count (mask start)
R204 (CCh)
6:0
M3_RISE[6:0]
000_0000
M3 pulse rise count (mask start)
R205 (CDh)
7:0
M3_FALL[7:0]
0000_0000
M3 pulse fall count (mask end)
R206 (CEh)
6:0
M3_FALL[6:0]
000_0000
M3 pulse fall count (mask end)
R271 (010Fh)
7:0
POL*_T1
1111_1111
polarity of T1 pulse at TP*
– R278 (116h)
7:0
POL*_T2
1111_1111
polarity of T2 pulse at TP*
ADDRESS
40
Rev 4.7
WM8233
TG CYCLE MODE
The TG cycle mode can set a different TG pulse line by line. This mode can only be used in slave
mode.
No SH
No pulse generation
No SH
No pulse generation
Cycmd [Serial I/F]
TGSYNC
15'h7FFF
pixel counter
cyccnt
000
001
010
100
cycpat_p0[0]
cycpat_p0[1]
001
01
0
100
001
010
000
Generated pulse0
Generated pulse1
Generated pulse2
Generated pulse3
cycen_p0
High
cycen_p1
cycen_p2
High
cycen_p3
cycpat_p1[0]
High
cycpat_p2[0]
High
cycpat_p3[0]
cycpat_p1[1]
cycpat_p2[1]
cycpat_p3[1]
cycpat_p0[2]
cycpat_p1[2]
cycpat_p2[2]
cycpat_p3[2]
cycpat_p0[0]
cycpat_p1[0]
cycpat_p2[0]
cycpat_p3[0]
cycpat_p0[1]
cycpat_p1[1]
cycpat_p2[1]
cycpat_p3[1]
cycpat_p0[2]
cycpat_p1[2]
cycpat_p2[2]
cycpat_p3[2]
cycpat_p0[0]
cycpat_p1[0]
cycpat_p2[0]
cycpat_p3[0]
cycpat_p0[1]
High
cycpat_p1[1]
cycpat_p2[1]
High
cycpat_p3[1]
High
High
PO0
PO1
PO2
PO3
Figure 23
TG Cycle Mode
REGISTER
BIT
LABEL
DEFAULT
3
CYCMD
0
DESCRIPTION
ADDRESS
R160 (A0h)
cycle mode enable
0 = normal (same operation at every line)
1 = cycle mode
R181 (B5h)
– R184 (B8h)
CYCPAT_PO*[2:0]
000
PO* cycle mode control
[0] = pulse enable at cycle-1
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
Rev 4.7
41
WM8233
PROGRAMMABLE AUTOMATIC BLACK LEVEL CALIBRATION (BLC)
The Programmable Automatic Black-Level Calibration (BLC) function is to adjust the D.C. offset of the
output data such that the digital output code for black pixels is calibrated to a target black level value.
The D.C. offset is determined during the optically-black pixels at the beginning of the linear sensor
and removed during the image-pixels as shown in Figure 24.
Black Pixel Period
Image Pixel Period
Determine Black
Level Offset
Remove Black Level Offset
from Image Pixels
Figure 24 Linear Sensor Model
The automatic black level calibration operates assuming 12-bits ADC resolution. Adjustments to
calculations must be made for different ADC resolutions.
The black level calibration process occurs in two stages as shown in Figure 25 below:
Coarse Adjust Calibration - This is a mixed signal loop which removes the coarse offset
by adjusting the offset DAC.
Fine Adjust Calibration - This is a digital loop which removes the remaining offset with
better noise tolerance, utilising ADC over-range to improve the dynamic range of the
system.
Input Black Level V1
PGA
Offset
DAC
Adjusted
ADC Output
ADC
Coarse Adjust
Calibration
Fine Adjust
Calibration
Mixed
Signal
LOOP
Digits
Digital
LOOP
Digits
TARGET BL
Figure 25 BLC Top-Level Circuitry
TARGET CODES
The user must specify a target black level for each channel through the registers TARGETINP*. If,
during the black-pixel period, the average ADC output code was, for example, 100 and the user
specified the target black level code to be 10, the BLC circuitry would determine 90 codes should be
subtracted from the ADC output. These 90 codes will then be subtracted from every image-pixel code
output from the ADC.
Note – changing the PGA gain affects the black-level through the device; the gain should therefore not
be changed during a BLC procedure. If the PGA gain changes, then the BLC routine should be rerun.
The automatic black level calibration feature operates with the assumption of a 12-bit ADC resolution.
The register settings for Target Codes (TARGETINP*) should be set differently depending on the ADC
42
Rev 4.7
WM8233
resolution being used. As TARGETINP* is an 8 bit register, the 4 MSBs of a data output code cannot
be changed.
16-bit ADC Resolution
For 16-bit resolution the target code entered into TARGETINP* will ignore the 4 MSBs and 4 LSBs of
the 16-bit data output. For example if the desired code out is 0000111111110001, the value entered
into TARGETINP* would be 11111111.
10-bit ADC Resolution
For 10-bit resolution the 4 MSBs of the 10-bit data output code will be ignored. The 2 LSBs of the
target code should be set to ‘00’. For example if the desired code out is 0000111111, the value
entered into TARGETINP* would be 11111100.
BLC SCENARIOS OF OPERATION
The BLC can be used in various ways to suit the application, for example calibration can be done
once per page or once per line. Three potential scenarios of operation are suggested below.
Note: The registers FRAME_START and SEQ_START when set high by the user will automatically be
set low by the device.
SCENARIO 1
In this scenario, Coarse Adjust Calibration is enabled for the 1st line; Fine Adjust Calibration is enabled
for every line, with the Fine Adjust Calibration result recalculated every line. This scenario is suitable
for dealing with large amounts of D.C. drift throughout a frame; but this is at a cost of potential line-byline variation in the Fine Adjust result (dependent on sensor noise and the PGA gain). Table 12 shows
which registers are required for this scenario with example settings.
SETUP
REGISTER
BPIX_AVAIL
CADUR
FRAME_START
FA_EVERYLINE
Value
50
2
1
1
Table 12 Example Register Settings for Scenario 1
Black Pixels
Image Pixels
Auto Fine Adjust clear
Use Fine Adjust Result here
Line 1
Fine Adjust cleared
Use Fine Adjust Result here
Line 2
Fine Adjust cleared
Use Fine Adjust Result here
Line 3
Fine Adjust cleared
Use Fine Adjust Result here
Line 4
Fine Adjust cleared
Use Fine Adjust Result here
Line 5
Fine Adjust cleared
Use Fine Adjust Result here
Line 6
Fine Adjust cleared
Use Fine Adjust Result here
Line 7
Fine Adjust cleared
Use Fine Adjust Result here
---
Fine Adjust cleared
Use Fine Adjust Result here
---
Fine Adjust cleared
Use Fine Adjust Result here
---
Fine Adjust cleared
Use Fine Adjust Result here
Line n
Figure 26 Scenario 1
Rev 4.7
43
WM8233
SCENARIO 2
In this scenario, Coarse Adjust and Fine Adjust Calibration is enabled for the 1st line, with the Fine
Adjust result updated on the 1st line only. This scenario is suitable for adjusting for black-level D.C.
drift on a frame-by-frame basis; there will be no line-by-line variation in the black-level from the BLC
circuitry. Table 13 shows which registers are required for this scenario with example settings.
SETUP
REGISTER
BPIX_AVAIL
CADUR
FRAME_START
Value
50
2
1
Table 13 Example Register Settings for Scenario 2
Black Pixels
Auto Fine Adjust clear
Image Pixels
Use Fine Adjust Result here
Line 1
Use Fine Adjust Result here
Line 2
Use Fine Adjust Result here
Line 3
Use Fine Adjust Result here
Line 4
Use Fine Adjust Result here
Line 5
Use Fine Adjust Result here
Line 6
Use Fine Adjust Result here
Line 7
Use Fine Adjust Result here
---
Use Fine Adjust Result here
---
Use Fine Adjust Result here
---
Use Fine Adjust Result here
Line n
Figure 27 Scenario 2
44
Rev 4.7
WM8233
SCENARIO 3
In this scenario, Coarse Adjust Calibration is enabled for the 1st line; Fine Adjust Calibration is enabled
for every line, with the Fine Adjust result accumulated throughout frame and used every line. This
scenario allows any variation in the black-level to be tracked throughout the frame by accumulating
the Fine Adjust result over multiple lines. This method does not deal with as large amounts of D.C.
drift throughout the frame as scenario 1, but it will produce less line-by-line variation. Table 14 shows
which registers are required for this scenario with example settings.
SETUP
REGISTER
BPIX_AVAIL
CADUR
FRAME_START
FA_EVERYLINE
FA_ACCUM
Value
50
2
1
1
1
Table 14 Example Register Settings for Scenario 3
Black Pixels
Image Pixels
Auto Fine Adjust clear
Use Fine Adjust Result here
Line 1
Fine Adjust not cleared
Use Fine Adjust Result here
Line 2
Fine Adjust not cleared
Use Fine Adjust Result here
Line 3
Fine Adjust not cleared
Use Fine Adjust Result here
Line 4
Fine Adjust not cleared
Use Fine Adjust Result here
Line 5
Fine Adjust not cleared
Use Fine Adjust Result here
Line 6
Fine Adjust not cleared
Use Fine Adjust Result here
Line 7
Fine Adjust not cleared
Use Fine Adjust Result here
---
Fine Adjust not cleared
Use Fine Adjust Result here
---
Fine Adjust not cleared
Use Fine Adjust Result here
---
Fine Adjust not cleared
Use Fine Adjust Result here
Line n
Figure 28 Scenario 3
Rev 4.7
45
WM8233
AUTOMATIC GAIN CONTROL (AGC)
The Automatic Gain Control (AGC) function is to adjust the gain to an appropriate level for a range of
input signal levels. The AGC function is enabled by AGC_EN register set to 1. The gain control
process has three stages as shown in Figure 29 below:
SP First rising edge of
PEAK_DET after
I
SPI
AGE_EN=0
AGC_EN
Status
of AGC
Disable
Peak detection for analogue gain
N line = AGC_APD[2:0]
1line
Peak
(1)
0
AGAIN
AGAIN
DGAIN
DGAIN
Applied calibrated gain
Disable
M line = AGC_DPD[2:0]
Gain caluculation
PEAK_DET
(internal)
PEAK
(read only)
Peak detection for digital gain
Peak
(2)
Peak
(N)
Cleared peak
value Peak
(1)
Peak
(2)
Peak
(M)
0
Again(N)
AGAIN
DGAIN(x1)
Dgain(M)
DGAIN
FLAG_AGC
(read only)
Figure 29 Automatic Gain Control
Analogue Gain Calibration
The analogue gain is kept to the previous setting for (AGAIN), and the digital gain is set to x1
(DGAIN=12’d2048) automatically. During the PEAK_DET=high period, peak detection is executed and
then calculates an appropriate analogue gain (Again(N)) while PEAK_DET=low period. This period
requires at least 200 pixels. The number of peak detection cycle is selectable by the AGC_APD
register. The minimum cycle is 0 (In this case the analogue gain calibration is not executed), and the
maximum cycle is 7 lines. The peak value is cleared when the analogue peak detection finished.
Digital Gain Calibration
The analogue gain is set to the calibrated value (Again(N)), and the digital gain is set to x1
(DGAIN=12’d2048) automatically. The peak detection and digital gain calibration functions are then
executed. The number of peak detection lines is selectable by the AGC_DPD register. The minimum
cycle is 0 (In this case the digital gain calibration is not executed), and the maximum cycle is 7 lines.
Applied Calibrated Analogue and Digital Gain
The analogue and digital gain are holding calibrated value until AGC_EN register set to 0.
Again(N) = AGC_TARGETINP* / peak(n) x AGAIN
Dgain(M) = (AGC_TARGETINP* – TARGETINP*) / (peak(M) – TARGETINP*)
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
ADDRESS
46
R73 (49h)
7:0
TARGETIN1[7:0]
0000_0000
target black level for IN1[7:0]
R74 (4Ah)
7:0
TARGETIN2[7:0]
0000_0000
target black level for IN2[7:0]
R76 (4Ch)
7:0
TARGETIN3[7:0]
0000_0000
target black level for IN3[7:0]
R77 (4Dh)
7:0
TARGETIN4[7:0]
0000_0000
target black level for IN4[7:0]
R79 (4Fh)
7:0
TARGETIN5[7:0]
0000_0000
target black level for IN5[7:0]
R80 (50h)
7:0
TARGETIN6[7:0]
0000_0000
target black level for IN6[7:0]
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
7:4
AGCAVE[3:0]
0000
DESCRIPTION
ADDRESS
R87 (57h)
averaging factor before peak detection
0000 = no average, 0001 = 2, 0010 = 4, 0011 = 8 …, 1010
= 1024 (1011 = 1100 = 1101 = 1110 = 1111 = reserved)
2
AGC_ERRFLAG
0
1
AGC_ENDFLAG
0
AGC error flag
0 = no error detected, 1 = AGC finish with error
AGC end flag
0 = not end or not run, 1 = AGC sequence was done
AGC enable
0
AGC_EN
0
6:4
AGC_DPD[2:0]
000
the number of peak detection iterations to calculate digital
gain
2:0
AGC_APD[2:0]
000
the number of peak detection iterations to calculate
analogue gain
7:0
AGC_TARGETIN1
0000_0000
LSB of AGC target level for IN1
00
MSB of AGC target level for IN1
0000_0000
LSB of AGC target level for IN2
00
MSB of AGC target level for IN2
0000_0000
LSB of AGC target level for IN3
00
MSB of AGC target level for IN3
0000_0000
LSB of AGC target level for IN4
00
MSB of AGC target level for IN4
0000_0000
LSB of AGC target level for IN5
00
MSB of AGC target level for IN5
0000_0000
LSB of AGC target level for IN6
00
MSB of AGC target level for IN6
0 = disable, 1 = enable
R88 (58h)
R91 (5Bh)
[7:0]
R92 (5Ch)
1:0
AGC_TARGETIN1
[9:8]
R93 (5Dh)
7:0
AGC_TARGETIN2
[7:0]
R94 (5Eh)
1:0
AGC_TARGETIN2
R97 (61h)
7:0
AGC_TARGETIN3
[9:8]
[7:0]
R98 (62h)
1:0
AGC_TARGETIN3
[9:8]
R99 (63h)
7:0
AGC_TARGETIN4
[7:0]
R100 (64h)
1:0
AGC_TARGETIN4
[9:8]
R103 (67h)
7:0
AGC_TARGETIN5
[7:0]
R104 (68h)
1:0
AGC_TARGETIN5
[9:8]
R105 (69h)
7:0
AGC_TARGETIN6
[7:0]
R106 (6Ah)
1:0
AGC_TARGETIN6
[9:8]
R191 (BFh)
7:0
PEAKDET_RISE
0000_0000
R192 (C0h)
6:0
PEAKDET_RISE
000_0000
7:0
PEAKDET_FALL
0000_0000
6:0
PEAKDET_FALL
[14:8]
LSB of PEAKDET_FALL[14:0]
peak detection start pixel count
[7:0]
R194 (C2h)
MSB of PEAKDET_RISE[14:0]
peak detection start pixel count
[14:8]
R193 (C1h)
LSB of PEAKDET_RISE[14:0]
peak detection start pixel count
[7:0]
000_0000
MSB of PEAKDET_FALL[14:0]
peak detection start pixel count
LINE-BY-LINE OPERATION
Certain linear sensors give colour output on a line-by-line basis. i.e. a full line of red pixels followed by
a line of green pixels followed by a line of blue pixels.
The WM8233 can accommodate this type of input by setting the LINEBYLINE register bit high. The
offset and gain values that are applied to every input channel can be selected, by internal
Rev 4.7
47
WM8233
multiplexers, to come from IN4, IN5 or IN6 offset and gain registers. This allows the gain and offset
values for each of the input colours to be setup individually at the start of a scan.
When register bit ACYC=0 the gain and offset multiplexers are controlled via the INTM[1:0] register
bits. When INTM=00 the IN2 offset and gain control registers are used to control every input channel,
INTM=01 selects the IN4 offset and gain registers and INTM=10 selects the IN6 offset and gain
registers to control every input channel.
When register bit ACYC=1, ‘auto-cycling’ is enabled, and the input channel switches to the next offset
and gain registers in the sequence by TGSYNC. The sequence is IN2 IN4 IN6 IN2… offset
and gain registers applied to every input channel.
INTM=00
INTM=01
INTM=10
INTM=11
AGAININ2, DGAININ2, DACIN2
AGAININ4, DGAININ4, DACIN4
AGAININ6, DGAININ6, DACIN6
Reserved
ACYC=0
ACYC=1
INTM Mode (depends on INTM register)
Auto Cycling mode (IN2 -> IN4 -> IN6)
LINEBYLINE
INTM Mode
Normal Operation
LINEBYLINE 0x23[0]
INTM 0x23[3:2]
0
Normal Operation
1
00
01
00
0
01
11
Must be set to 0
ACYC 0x23[1]
TGSYNC
IN1
AGAININ1, DGAININ1, DACIN1
IN2
AGAININ2, DGAININ2, DACIN2
IN3
AGAININ3, DGAININ3, DACIN3
AGAININ1, DGAININ1, DACIN1
IN4
AGAININ4, DGAININ4, DACIN4
IN5
AGAININ5, DGAININ5, DACIN5
AGAININ5, DGAININ5, DACIN5
IN6
AGAININ6, DGAININ6, DACIN6
AGAININ6, DGAININ6, DACIN6
AGAININ2, DGAININ2, DACIN2
AGAININ4,
DGAININ4,
DACIN4
AGAININ2,
DGAININ2,
DACIN2
AGAININ4,
DGAININ4,
DACIN4
AGAININ6,
DGAININ6,
DACIN6
AGAININ3, DGAININ3, DACIN3
AGAININ4, DGAININ4, DACIN4
Figure 30 Line-by-Line Operation (ACYC=0, INTM mode)
ACYC=0
ACYC=1
INTM Mode (depends on INTM register)
Auto Cycling mode (IN2 -> IN4 -> IN6)
LINEBYLINE
Auto Cycling Mode
Normal Operation
LINEBYLINE 0x23[0]
ACYC 0x23[1]
0
Normal Operation
1
0
0
1
TGSYNC
IN1
AGAININ1, DGAININ1, DACIN1
IN2
AGAININ2, DGAININ2, DACIN2
IN3
AGAININ3, DGAININ3, DACIN3
AGAININ1, DGAININ1, DACIN1
IN4
AGAININ4, DGAININ4, DACIN4
IN5
AGAININ5, DGAININ5, DACIN5
AGAININ5, DGAININ5, DACIN5
IN6
AGAININ6, DGAININ6, DACIN6
AGAININ6, DGAININ6, DACIN6
AGAININ2, DGAININ2, DACIN2
AG2,
DG2,
DA2
AGAININ4,
DGAININ4,
DACIN4
AGAININ6,
DGAININ6,
DACIN6
AGAININ2,
DGAININ2,
DACIN2
AGAININ4,
DGAININ4,
DACIN4
AGAININ6,
DGAININ6,
DACIN6
AGAININ2,
DGAININ2,
DACIN2
AGAININ4,
DGAININ4,
DACIN4
AGAININ6,
DGAININ6,
DACIN6
AG2,
DG2,
DA2
AGAININ3, DGAININ3, DACIN3
AGAININ4, DGAININ4, DACIN4
Figure 31 Line-by-Line Operation (ACYC=1, Auto-cycling mode)
REGISTER
BIT
LABEL
DEFAULT
3:2
INTM[1:0]
00
DESCRIPTION
ADDRESS
R35 (23h)
Cycle mode
control
When LINEBYLINE=1,
controls the GAIN and DAC mux selector when ACYC=0
00 = IN2
01 = IN4
10 = IN6
11 = reserved
1
ACYC
0
when LINEBYLINE=1, determines the function of the MUX control
0 = decided by INTM register
1= auto-cycling enabled
0
LINEBYLINE
0
select line by line operation
0=normal operation
1=Line by Line operation
48
Rev 4.7
WM8233
TEST PATTERN GENERATOR
WM8233 has test pattern generator which can be used for interface verification between AFE data
output and back-end devices without sensor signal input. This function can be presented in several
different patterns by PGPAT[1:0] and PGMARCH registers as shown below. The PGLEVEL,
PGWIDTH1 and PGWIDTH2 are the parameter to define the pattern level and width. The PGLEVEL
register has 16bit length, PGWIDTH1 and PGWIDTH2 has 8bit length.
Note that test pattern generator is required TGSYNC input. (i.e. this can be used under TG slave
mode operation only.)
d=PGLEVEL
A=PGWIDTH1
B=PGWIDTH2
PGEN (register)
TGSYNC (input)
PGPAT=00
(Fixed Pattern)
0
PGPAT=01
(Vertical RAMP)
0
d
0
nd
md
PGPAT=10
(Horizontal RAMP)
0
A
PGPAT=11
(Patch)
2d
d
0
A
65535
0
d
0
d
0
Return to 0 at 65535
0
A
d
0
d
0
0
0
0
BA
B
A
B
A
Figure 32 Test Pattern Output Data Formats
A
A
A
A
A
0
d
d
d
2d
3d
4d
5d
6d
7d
B
0
A
d
d
d
B
A
B
A
d
d
A
d
A
d
A
A
d
d
A
A
d
A
A
d
A
A
d
d
d
A
B
B
A
B
A
d
A
A
A
A
~0
~d ~2d ~3d ~4d ~5d ~6d ~7d
B
A
A
A
d
A
B
PGINV=1
A
0
d
~0
~d
~2d
~3d
~4d
~5d
~6d
A
A
A
A
A
A
A
A
A
A
A
A
(Patch)
d
A
TGSYNC
B
A
d
0
d
2d
3d
4d
5d
6d
(Horizontal RAMP)
TGSYNC
d
PGINV=0
(Vertical RAMP)
TGSYNC
A
A
A
A
A
A
A
PGPAT=11
PGPAT=10
PGPAT=01
A
d=PGLEVEL
A=PGWIDTH1
B=PGWIDTH2
A
~d
~0
~d
~d
~0
~d
~d
~d
Figure 33 Test Pattern Output image
Rev 4.7
49
WM8233
PGEN (register)
TGSYNC (input)
PGMARCH=1
(Marching mode)
d[15:0]
0
{d[14:0], {d[13:0], {d[12:0],
d[15]} d[15:14]} d[15:13]}
{d[1:0], {d[0],
d[15:0]
d[15:2]} d[15:1]}
{d[14:0],
d[15]}
0
1 bit shift per TGSYNC
Figure 34 Test Pattern Output Data Formats (Marching mode)
REGISTER
BIT
LABEL
DEFAULT
7
PGMARCH
0
DESCRIPTION
ADDRESS
R20 (14h) PG
config
pattern generator marching mode enable
0 = controlled by PGPAT
1 = marching pattern
6:5
PGPAT[1:0]
00
select pattern generator output
00 = fixed value
01 = vertical ramp
10 = horizontal ramp
11 = patch
4
PGINV
0
invert pattern generator output
0 = normal
1 = invert
3
SEL_PGZ
0
select output of pattern generator (IN5, IN6)
0 = normal ouput
1 = output generated digital pattern instead of ADC outputs
2
SEL_PGY
0
select output of pattern generator (IN3,IN4)
0 = normal ouput
1 = output generated digital pattern instead of ADC outputs
1
SEL_PGX
0
select output of pattern generator (IN1, IN2)
0 = normal ouput
1 = output generated digital pattern instead of ADC outputs
0
PGEN
0
enable pattern generator
0 = disable
1 = enable
REGISTER
BIT
LABEL
DEFAULT
R21 (15h)
PGCODE
LSB
7:0
PGLEVEL[7:0]
0000_0000
REGISTER
BIT
LABEL
DEFAULT
R22 (16h)
PGCODE
MSB
7:0
PGLEVEL[7:0]
0000_0000
REGISTER
BIT
LABEL
DEFAULT
7:0
PGWIDTH1[7:0]
0000_0000
DESCRIPTION
ADDRESS
parameter of pattern generator
DESCRIPTION
ADDRESS
parameter of pattern generator
DESCRIPTION
ADDRESS
R23 (17h) PG
width 1
50
parameter of pattern generator
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
7:0
PGWIDTH2[7:0]
0000_0000
DESCRIPTION
ADDRESS
R24 (18h) PG
width 2
parameter of pattern generator
REGISTER SETTING PROCEDURE
OVERALL
Figure 35 shows the overall procedure for WM8233 register setting. Every register can be configured
without MCLK and TGSYNC input, but the following Note1~3 must be followed before starting normal
operation.
POWER ON
Present External clock
MCLK (*1), TGSYNC (*2)
PLL/DLL
Configuration(*3)
Sampling
configuration
Clamp
configuration(*4)
VRLC
configuration
Offset DAC
configuration
PGA
configuration
TG Clock/Pulse
configuration
Data output
configuration
System Reset (*3)
NORMAL OPERATION
Figure 35 Overall Procedure
Notes:
1. MCLK must be present before System Reset. Also, System Reset must be done when MCLK is
interrupted during normal operation.
2. TGSYNC input is required in TG slave mode. Also, this must be present before normal operation.
3. System Reset must be done after PLL/DLL configuration.
Rev 4.7
51
WM8233
PLL/DLL CONFIGURATION
PLL and DLL registers must be configured depending on the MCLK frequency and data output format.
See “PLL DLL Setup” section for details of configuring PLL/DLL registers. The device must be reset
after PLL/DLL configuration as shown in Figure 36.
PLL/DLL configuration
PLL configuration
0x1C[6:4]
PLL_EXDIV_SEL
LDO configuration
(if required)
DLL configuration
0x80[5:4] DLGAIN
0x81[5:4] LVDLGAIN
0x1B0[0] USER_KEY
0x1B4[4:0] LDO2_VSEL
System reset
Figure 36 PLL/DLL Configuration
System reset
Power down
(Sleep mode)
Back to
Normal operation
0x03[1] PDMD=1
0x03[0] PD=1
0x03[1] PDMD=0
0x03[0] PD=0
Figure 37 System Reset
SAMPLING CONFIGURATION
Sampling configuration is the setting for input signal polarity and sampling timing. See “CDS/Non-CDS
Processing” section for details of configuring this register.
Non-CDS mode (S/H mode): RSMP configuration is not required.
CDS mode: RSMP and VSMP configurations are required.
Sampling configuration
Input signal polarity
configuration
0x04[6]
PGAFS
Sampling mode
selection
0x04[0]
CDS=1
0x04[0]
CDS=0
VSMP
configuration
Non-CDS
mode 0x84 VSMP_RISE
0x85 VSMP_FALL
CDS mode
RSMP, VSMP
configuration
0x82,0x83 RSMP_RISE, RSMP_FALL
0x84,0x85 VRMP_RISE, VSMP_FALL
Figure 38 Sampling Configuration
52
Rev 4.7
WM8233
CLAMP CONFIGURATION
Clamp configuration is the setting for clamp modes and clamp timing configuration in line clamp mode.
See “Reset Level Clamping (RLC)” section and “CDS/Non-CDS Processing” section for details of
configuring this register.
TG enabled: This must be enabled when AGC function is used.
Line clamp configuration: Line clamp operation is enabled during CLAMP_RISE ~ CLAMP_FALL
period. Also, the source follower should be set to prevent clamp voltage drop in line clamp mode.
Pixel clamp (Bit clamp) mode: The pixel clamping is enabled during RSMP = high period. This mode
can be used in CDS operation only.
Clamp configuration
Clamp mode
selection
0x04[1]
CLPMD=1
0x04[1]
CLPMD=0
Bit clamp
Line clamp
TG enabled (*1)
TG mode
selection
Pixel clamp mode (*3)
Slave mode
0xA0[1] TGMD=0
Master mode
0xA0[1] TGMD=1
Line length
configuration
0xA1,0xA2 LLENGTH
TG
enabled
0xA0[0] TG_EN
Line clamp configuration
Clamp timing
configuration
0xB9,0xBA CLAMP_RISE
0xBB,0xBC CLAMP_FALL
Source follower
configuration (*2)
0x05[1] SF_INP
0x05[0] SF_VRLC
Figure 39 Clamp Configuration
Notes:
1. This must be set when Line clamp is used.
2. SF_INP and SF_VRLC must be set both when source follower enabled
3. Pixel clamp can be used in CDS operation only.
Rev 4.7
53
WM8233
VRLC CONFIGURATION
VRLC configuration is the setting for VRLC voltage, which is used for input signal clamp voltage at line
clamp operation. The VRLC voltage is also used as the reference level of non-CDS (S/H) operation.
See “Reset Level Clamping (RLC)” section and “CDS/Non-CDS Processing” section for details of
configuring this register.
VRLC configuration
0x06[7]
VRLCEN=1
VRLC
configuration
0x06[7]
VRLCEN=0
VRLC output range
configuration
0x04[7] VRLC_TOP_SEL
VRLC output voltage
configuration
0x06[4:0] VRLC_VSEL
VRLC disabled
(External VRLC operation)
Figure 40 VRLC Configuration
OFFSET DAC CONFIGURATION
The offset DAC is used for black level offset compensation. WM8233 has BLC function to calibrate
black level. In this mode, the offset DAC will be configured automatically. When this function is not
needed, the offset DAC can be configured manually. See “Overall Signal Flow Summary” section for
details of offset DAC configuration, and see “BLC Scenarios of Operation” for details of BLC sequence.
Offset DAC configuration
No
Offset DAC
configuration
Using BLC function
Yes
0x24~0x2C DACIN*
BLC
configuration
Figure 41 Offset DAC Configuration
BLC Configuration
TG enabled: This must be enabled when AGC function is used.
BLC start pixel configuration: This is start pixel configuration for BLC.
BLC period configuration: BLC will operate while this period from BLC start pixel.
BLC target level configuration: This is configuration for the target level of black pixel.
Coarse adjust configuration:
CADUR: This is the coarse adjust iteration setting during BLC period.
CA_EVERYLINE: When this register set, coarse adjust will operate on every line.
Fine adjust configuration: This is configuration for Coarse adjust iteration.
FA_EN: When this register set, fine adjust will operate during BLC period.
FA_EVERYLINE: When this register set, fine adjust will operate on every line.
54
Rev 4.7
WM8233
BLC configuration
TG enabled (*1)
Slave mode
0xA0[1] TGMD=0
TG mode
selection
Master mode
0xA0[1] TGMD=1
Line length
configuration
0xA1,0xA2 LLENGTH
TG
enabled
0xA0[0] TG_EN
BLC start pixel
configuration
BLC period
configuration
0xBD,0xBE OB_START
0x53,0x54 BPIX_AVAIL
Coarse adjust
configuration
Fine adjust
configuration
0x51[2:0] CADUR
0x51[3] CA_EVERYLINE
BLC target level
configuration
0x49,4A,4C,4D,4F,50
TARGETINn*
0x51[4] FA_EN
0x51[6] FA_EVERYLINE
Set the frame start
indicator (*2)
0x52[0] FRAME_START
TGSYNC
Start the frame
sequence
Figure 42 BLC Configuration
Notes:
1. This must be set when BLC is used.
2. With this register set, frame sequence will be started after TGSYNC is recognized. Therefore this
should be set within the last line of previous frame.
PGA CONFIGURATION
The WM8233 provides an Automatic Gain Control (AGC) function. The output code is calibrated to
target level by this automatic gain control function. See “Automatic Gain Control (AGC)” section for
details of AGC sequence. Also, see the following instruction to configure AGC related registers. The
analogue PGA (APGA) and digital PGA (DPGA) can be configured manually when AGC is not
required. See “Offset Adjust and Programmable Gain” section for details of PGA configuration.
PGA configuration
Manual PGA configuration
No
Using AGC function
Yes
APGA
configuration
0x2E,2F,31,32,34,35
AGAININ*
DPGA
configuration
0x38~0x41,0x3E~0x41,
0x44~0x47 DGAININ*
AGC
configuration
Figure 43 PGA Configuration
Rev 4.7
55
WM8233
AGC CONFIGURATION
Figure 44 shows the procedure for AGC Configuration.
TG enabled: This must be enabled when AGC function is used.
AGC averaging factor configuration: This is averaging factor for peak level detection.
AGC APD/DPD configuration: This is line iteration setting for peak level detection.
AGC target level configuration: The output code will be calibrated to this target level after APGA
and DPGA calibration. APGA and DPGA keep calibrated gain value while AGC is enabled.
(AGC_EN=1)
Peak detection period configuration: This is the setting for peak detection period.
AGC configuration
TG enabled (*1)
Slave mode
0xA0[1] TGMD=0
TG mode
selection
Master mode
0xA0[1] TGMD=1
Line length
configuration
0xA1,0xA2 LLENGTH
TG
enabled
0xA0[0] TG_EN
AGC averaging factor
configuration
AGC APD
configuration
0x57[7:4] AGCAVE
AGC DPD
configuration
0x58[2:0] AGC_APD
AGC target level
configuration
0x58[6:4] AGC_DPD
Peak detection period
configuration
0x5B~0x5E,0x61~0x64,
0x67~0x6A
AGC_TARGETIN*
0xBF,0xC0 PEAKDET_RISE
0xC1,0xC2 PEAKDET_FALL
AGC enabled (*2)
0x57[0] AGC_EN=1
TGSYNC
Start AGC operation
Figure 44 AGC Configuration
Notes:
1. This must be set when AGC is used.
2. With this register set, AGC sequence will be started after TGSYNC is recognized.
56
Rev 4.7
WM8233
TG CLOCK CONFIGURATION
Figure 45 shows the procedure for TG Clock Timing and Mask Configuration. CLK1~CLK6 can be
configured as clock type output. See “Sensor Timing Generation” section for details of TG function.
TG enabled: This must be enabled when TG mask function is used.
Mask period configuration: TG clock will be masked while mask signal is high. The rising and
falling timing is configured by M*_RISE/FALL register. See “TG Mask Timing” section for details of this
function.
Toggle point configuration: Pulse toggle timing is configured by toggle point setting (TP0~TP31).
TP* register consists of toggle point setting bit (TP value bit) and enable bit. The enable bit must be
set when TP is used. Unused TP can be disabled, but it must be followed Note-2 as described below.
T1 and T2 polarity configuration: T1 and T2 are internal signal to set the TG signal polarity during
mask period. See “TG Mask Timing” section for details of this function.
TG Clock configuration
CLK1~6 rise/fall timing
configuration
Using TG Mask
function
0x87~0x92
CLK*_RISE/FALL
No
Yes
TG enabled (*1)
Slave mode
0xA0[1] TGMD=0
TG mode
selection
Master mode
0xA0[1] TGMD=1
Line length
configuration
0xA1,0xA2 LLENGTH
TG
enabled
0xA0[0] TG_EN
Mask configuration
Mask period
configuration
0xC3~0xCE
M*_RISE/FALL
Using T1,T2
function
Toggle setting for
M1 and M2 period
No
Yes
Toggle point
Configuration (*2)
T1 and T2 polarity
configuration
0xCF~0x10E TP0~TP31
0x10F~0x116 POL*_T*
TG output enabled
CLK pin
enabled
TG signal output
enabled
0xA5~0xA6 OE_CK*=1
0xA9~0xAA EN_CK*=1
Figure 45 TG Clock Configuration
Notes:
1. This must be set when the TG-MASK function is used.
2. When configure Toggle point (TP), it must be used from TP0 in ascending order. Also, TP pixel
counter value must be set as TP0<TP1<TP2 …..
Rev 4.7
57
WM8233
TG PULSE CONFIGURATION
Figure 46 shows the procedure for TG Pulse Configuration. CLK2~CLK11 can be configured as pulse
type output. See “Sensor Timing Generation” section for details of TG function.
TG enabled: This must be enabled when TG pulse function is used.
Toggle point configuration: Pulse toggle timing is configured by toggle point setting (TP0~TP31).
TP* register consists of toggle point setting bit (TP pixel counter value bit) and enable bit. The enable
bit must be set when TP is used. Unused TP can be disabled, but this must be followed Note-1 as
described below.
PO0~PO7 configuration: PO0~PO7 are internal pulse for CLK pulse output. Pulse toggle timing is
configured by polarity setting register (0x117~0x136 POL*_PO*).
CLK2~6 pulse out configuration: CLK2~CLK6 can select output signal type, clock type or pulse type
by SEL_CK* register bit. This register must be set when pulse output is required.
PO assignment: Internal PO* pulse will be assigned to CLK2~CLK11 pin with this register.
TG Pulse configuration
TG enabled
Slave mode
0xA0[1] TGMD=0
TG mode
selection
Master mode
0xA0[1] TGMD=1
Line length
configuration
0xA1,0xA2 LLENGTH
TG
enabled
0xA0[0] TG_EN
Pulse configuration
Toggle point
Configuration (*1)
0xCF~0x10E
TP*, GEN_TP0, EN_TP*
PO0~PO7
configuration
0x117~0x136 POL*_PO*
CLK2~6 pulse out
Configuration
0xAB~0xAD SEL_CK*=1
PO assignment
0xAB~0xAF SEL_PCK*
TG output enabled
CLK pin
enabled
TG signal output
enabled
0xA5~0xA6 OE_CK*=1
0xA9~0xAA EN_CK*=1
Figure 46 TG Pulse Configuration
Notes:
1. When configure Toggle point (TP), it must be used from TP0 in ascending order. Also, TP pixel
counter value must be set as TP0<TP1<TP2
58
Rev 4.7
WM8233
DATA OUTPUT CONFIGURATION
Figure 47 shows the procedure for Data Output Configuration. WM8233 provides 10-bit CMOS output
and various LVDS output formats. See “Output Data Format” section for details of LVDS and CMOS
output format.
DATA output configuration
Output mode
Selection
CMOS output
configuration
0x07[5]
CMOSMODE=1
0x07[5]
CMOSMODE=0
LVDS output
configuration
PLL/DLL
Configuration (*1)
Data output enabled
Output pin
enabled
Data output
enabled
0x07[7] OE_OP=1
0x07[6] OUTPD=0
Figure 47 Data Output Configuration
Notes: 1. For details, see “PLL/DLL Configuration” section.
CMOS Output Configuration
Figure 48 shows the procedure for CMOS Output Configuration. Output drivability must be set when
CMOS output is selected. In CMOS output mode, flag signal will be output from DCLKN/OC[2] pin.
CMOS output configuration
Output drivability
configuration (*1)
No
Use
flag signal
0x0D[2:0] OP_DRV
Yes
Output flag configuration
TG enabled (*2)
Slave mode
0xA0[1] TGMD=0
TG mode
selection
Master mode
0xA0[1] TGMD=1
Line length
configuration
0xA1,0xA2 LLENGTH
TG
enabled
0xA0[0] TG_EN
PO* pulse
Flag signal
Selection
0xB4[3:0]
SEL_FLAG
Flag output
(PO* period)
Flagpix
Flag output timing
configuration
Flag output
(1 pixel period)
0xA3,0xA4 FLAGPIX
Figure 48 CMOS Output Configuration
Rev 4.7
59
WM8233
Notes:
1. OP_DRV is valid when 0x0D[3] DRV_CTRL set to 0.When DRV_CTRL set to 1, OP_DRV is
invalid, and drivability of output pin can be configured individually by 0x0E~0x13 OP*_DRV and
OC*_DRV.
2. This must be set when flag is used.
LVDS Output Configuration
Figure 49 shows the procedure for LVDS Output Configuration.
LVDS format configuration: LVDS format can be configured by this register. See “Output Data
Format” section for details of each format.
Data output order configuration: Data output order can be set by this register. See “LVDS Data
Output Order” section for details of output order.
LVDS amplitude configuration: This is LVDS signal amplitude configuration. The LVDS amplitude is
configured using the LVDS_AMP register field. Selections in the range 50mV to 200mV are supported.
Note that the default code (110) should not be used.
LVDS VCM level configuration: This is LVDS common mode voltage configuration.
LVDS DCLK pattern configuration: This is DCLK output pattern configuration.
Output flag configuration: Flag type can be selected from start flag or cannel ID. See “Trigger Data”
and “Channel ID” section for details of output flag. When this is not used, flag data (S~S4) will be
always 0.
60
Rev 4.7
WM8233
LVDS output configuration
Output signal configuration
LVDS format
configuration
Data output order
configuration
0x07[2:0] LVDSMODE
0x07[3] LVDSORDER
LVDS VCM level
configuration
LVDS DCLK pattern
configuration
0x08[2:0] LVDS_VCM
LVDS amplitude
configuration
0x08[5:3] LVDS_AMP
0x09[6:0] LVCKPAT
Use
flag signal
No
Yes
Output flag configuration
Flag type
Selection
0x0A~0x0C
FLAG_S*
Channel ID
Channel ID output
Start flag
TG enabled (*1)
Slave mode
0xA0[1] TGMD=0
TG mode
selection
Master mode
0xA0[1] TGMD=1
Line length
configuration
0xA1,0xA2 LLENGTH
TG
enabled
0xA0[0] TG_EN
PO* pulse
Flag signal
Selection
0xB4[3:0]
SEL_FLAG
Flag output
(PO* period)
Flagpix
Flag output timing
configuration
Flag output
(1 pixel period)
0xA3,0xA4 FLAGPIX
Figure 49 LVDS Output Configuration
Notes:
1. This must be set when start flag is used.
Rev 4.7
61
WM8233
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the WM8233. Not all registers are
used and any registers not listed should be set to zero.
REG
NAME
R0 (0h)
Software Reset/Chip ID 1
7
6
5
4
3
2
R1 (1h)
Chip ID 2
R2 (2h)
Chip Rev
0
0
0
0
R3 (3h)
Setup Reg 1
0
0
0
ADC3PD
ADC2PD
ADC1PD
R4 (4h)
Setup Reg 2
VVRLC_TOP_SEL
PGAFS
ADCFS
0
0
0
R5 (5h)
Setup Reg 3
0
0
0
SF_BYPLS
R6 (6h)
VRLC control
VRLCEN
R7 (7h)
Output control
OE_OP
OUTPD
R8 (8h)
LVDS control
0
LVDS_POL
R9 (9h)
LVDS clock pattern
0
R10 (Ah)
Flag control 1
1
0
SW_RESET_CHIP_ID[7:0]
33h
CHIP_ID[7:0]
82h
CHIP_REV[3:0]
PDMD
PT_SF[1:0]
VRLC_ISEL[1:0]
CMOSMODE
00h
PD
LVDSORDER
LVDS_AMP[2:0]
CLPMD
CDS
00h
SF_VRLC
1Ch
8Ah
LVDSMODE[2:0]
40h
LVDS_VCM[2:0]
35h
LVCKPAT[6:0]
63h
FLAG_S1[3:0]
R11 (Bh)
Flag control 2
R12 (Ch)
Flag control 3
0
0
0
0
R13 (Dh)
CMOS drivability control 1
0
0
0
0
R14 (Eh)
CMOS drivability control 2
0
R15 (Fh)
CMOS drivability control 3
0
R16 (10h) CMOS drivability control 4
00h
SF_INP
VRLC_VSEL[4:0]
OUTSYNC
DEFAULT
FLAG_S3[3:0]
FLAG_S0[3:0]
10h
FLAG_S2[3:0]
00h
FLAG_S4[3:0]
00h
DRV_CTRL
OP_DRV[2:0]
00h
OP1_DRV[2:0]
0
OP0_DRV[2:0]
00h
OP3_DRV[2:0]
0
OP2_DRV[2:0]
00h
0
OP5_DRV[2:0]
0
OP4_DRV[2:0]
00h
R17 (11h) CMOS drivability control 5
0
OP7_DRV[2:0]
0
OP6_DRV[2:0]
00h
R18 (12h) CMOS drivability control 6
0
OP9_DRV[2:0]
0
OP8_DRV[2:0]
00h
R19 (13h) CMOS drivability control 7
0
OC2_DRV[2:0]
0
OC1_DRV[2:0]
R20 (14h) PG config
PGMARCH
PGPAT[1:0]
PGINV
SEL_PGZ
SEL_PGY
SEL_PGX
00h
PGEN
00h
R21 (15h) PGCODE LSB
PGLEVEL[7:0]
00h
R22 (16h) PGCODE MSB
PGLEVEL[15:8]
00h
R23 (17h) PG width 1
PGWIDTH1[7:0]
00h
R24 (18h) PG width 2
PGWIDTH2[7:0]
00h
R25 (19h) Clock monitor
0
0
0
0
0
MONCLK[2:0]
00h
R26 (1Ah) PLL control 1
0
0
0
0
0
PLL_LPF_RST PLL_CP_PD PLL_VCO_PD
00h
R27 (1Bh) PLL control 2
0
PLL_LPF_SEL
0
0
R28 (1Ch) PLL divider control 1
0
R29 (1Dh) PLL divider control 2
0
0
R35 (23h) Cycle mode control
0
0
PLL_PFD_CTRL[1:0]
PLL_EXDIV_SEL[2:0]
PLL_FBDIV_SEL[3:0]
PLL_POSTDIV2_SEL[1:0]
0
PLL_CP_GAIN[1:0]
13h
PLL_POSTDIV1_SEL[3:0]
0
INTM[1:0]
ACYC
09h
13h
LINBYLINE
00h
R37 (25h) DAC IN1
DACIN1[7:0]
80h
R38 (26h) DAC IN2
DACIN2[7:0]
80h
R40 (28h) DAC IN3
DACIN3[7:0]
80h
R41 (29h) DAC IN4
DACIN4[7:0]
80h
R43 (2Bh) DAC IN5
DACIN5[7:0]
80h
R44 (2Ch) DAC IN6
DACIN6[7:0]
80h
R46 (2Eh) AGAIN IN1
0
0
0
AGAININ1[4:0]
01h
R47 (2Fh) AGAIN IN2
0
0
0
AGAININ2[4:0]
01h
R49 (31h) AGAIN IN3
0
0
0
AGAININ3[4:0]
01h
R50 (32h) AGAIN IN4
0
0
0
AGAININ4[4:0]
01h
R52 (34h) AGAIN IN5
0
0
0
AGAININ5[4:0]
01h
R53 (35h) AGAIN IN6
0
0
0
R56 (38h) DGAIN IN1 LSB
R57 (39h) DGAIN IN1 MSB
62
DGAININ1[3:0]
AGAININ6[4:0]
0
DGAININ1[11:4]
0
01h
0
0
00h
80h
Rev 4.7
WM8233
REG
NAME
7
R58 (3Ah) DGAIN IN2 LSB
6
5
4
DGAININ2[3:0]
R59 (3Bh) DGAIN IN2 MSB
3
2
1
0
DEFAULT
0
0
0
0
00h
DGAININ2[11:4]
R62 (3Eh) DGAIN IN3 LSB
DGAININ3[3:0]
80h
0
R63 (3Fh) DGAIN IN3 MSB
0
0
0
0
0
0
DGAININ3[11:4]
R64 (40h) DGAIN IN4 LSB
DGAININ4[3:0]
80h
0
R65 (41h) DGAIN IN4 MSB
DGAININ4[11:4]
R68 (44h) DGAIN IN5 LSB
DGAININ5[3:0]
0
0
0
0
0
0
DGAININ5[11:4]
R70 (46h) DGAIN IN6 LSB
DGAININ6[3:0]
00h
80h
0
R69 (45h) DGAIN IN5 MSB
00h
00h
80h
0
00h
R71 (47h) DGAIN IN6 MSB
DGAININ6[11:4]
80h
R73 (49h) BLC IN1 target
TARGETIN1[7:0]
00h
R74 (4Ah) BLC IN2 target
TARGETIN2[7:0]
00h
R76 (4Ch) BLC IN3 target
TARGETIN3[7:0]
00h
R77 (4Dh) BLC IN4 target
TARGETIN4[7:0]
00h
R79 (4Fh) BLC IN5 target
TARGETIN5[7:0]
00h
R80 (50h) BLC IN6 target
TARGETIN6[7:0]
00h
R81 (51h) BLC control 1
R82 (52h) BLC control 2
FRAME_SEQ FA_EVERYLINE FA_ACCUM
0
0
FA_EN
CA_EVERYLINE
0
0
0
R83 (53h) BLC control 3
R84 (54h) BLC control 4
0
0
0
0
0
0
0
0
AGCAVE[3:0]
0
AGC_DPD[2:0]
R91 (5Bh) AGC target IN1 LSB
R92 (5Ch) AGC target IN1 MSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AGC_APD[2:0]
00h
00h
00h
0
AGC_TARGETIN1[9:8]
0
0
0
0
0
0
0
0
0
0
0
0
0
AGC_TARGETIN2[9:8]
0
AGC_TARGETIN3[9:8]
0
AGC_TARGETIN4[9:8]
0
AGC_TARGETIN5[9:8]
0
AGC_TARGETIN6[9:8]
0
0
0
0
0
R128 (80h) DLL config 1
0
0
0
0
DLGAIN[1:0]
00h
00h
00h
00h
0
PEAK_IN1[9:8]
0
PEAK_IN2[9:8]
00h
00h
00h
00h
0
PEAK_IN4[9:8]
0
PEAK_IN5[9:8]
0
0
PEAK_IN6[9:8]
0
DLLRST
00h
00h
00h
00h
PEAK_IN6[7:0]
0
00h
00h
PEAK_IN5[7:0]
R124 (7Ch) AGC peak level IN6 MSB
00h
00h
PEAK_IN3[9:8]
0
00h
00h
0
0
00h
00h
PEAK_IN4[7:0]
R123 (7Bh) AGC peak level IN6 LSB
Rev 4.7
0
00h
AGC_EN
PEAK_IN3[7:0]
R121 (79h) AGC peak level IN5 LSB
R122 (7Ah) AGC peak level IN5 MSB
AGC_ERRFLAGAGC_ENDFLAG
PEAK_IN2[7:0]
R117 (75h) AGC peak level IN4 LSB
R118 (76h) AGC peak level IN4 MSB
00h
0
0
00h
LINE_DEL
PEAK_IN1[7:0]
R115 (73h) AGC peak level IN3 LSB
R116 (74h) AGC peak level IN3 MSB
0
AGC_TARGETIN6[7:0]
R111 (6Fh) AGC peak level IN2 LSB
R112 (70h) AGC peak level IN2 MSB
0
AGC_TARGETIN5[7:0]
R109 (6Dh) AGC peak level IN1 LSB
R110 (6Eh) AGC peak level IN1 MSB
0
00h
AGC_TARGETIN4[7:0]
R105 (69h) AGC target IN6 LSB
R106 (6Ah) AGC target IN6 MSB
BPIX_AVAIL[1:0]
AGC_TARGETIN3[7:0]
R103 (67h) AGC target IN5 LSB
R104 (68h) AGC target IN5 MSB
0
0
R99 (63h) AGC target IN4 LSB
R100 (64h) AGC target IN4 MSB
0
AGC_TARGETIN2[7:0]
R97 (61h) AGC target IN3 LSB
R98 (62h) AGC target IN3 MSB
0
AGC_TARGETIN1[7:0]
R93 (5Dh) AGC target IN2 LSB
R94 (5Eh) AGC target IN2 MSB
00h
LINE_DEL[7:0]
R87 (57h) AGC config 1
R88 (58h) AGC config 2
00h
SEQ_START FRAME_START
BPIX_AVAIL[7:0]
R85 (55h) BLC control 5
R86 (56h) BLC control 6
CADUR[2:0]
0
00h
00h
CKOSTB
AFECKSTB
00h
10h
63
WM8233
7
6
5
R129 (81h) DLL config 2
REG
NAME
0
0
LVDLGAIN[1:0]
R130 (82h) RSMP rise
0
0
RSMP_RISE[5:0]
1Ch
R131 (83h) RSMP fall
0
0
RSMP_FALL[5:0]
26h
R132 (84h) VSMP rise
0
0
VSMP_RISE[5:0]
37h
R133 (85h) VSMP fall
0
0
VSMP_FALL[5:0]
08h
R134 (86h) TGCKO rise
0
0
TCLKO_RISE[5:0]
37h
R135 (87h) CLK1 rise
0
0
CLK1_RISE[5:0]
0Ah
R136 (88h) CLK1 fall
0
0
CLK1_FALL[5:0]
19h
R137 (89h) CLK2 rise
0
0
CLK2_RISE[5:0]
19h
R138 (8Ah) CLK2fall
0
0
CLK2_FALL[5:0]
28h
R139 (8Bh) CLK3 rise
0
0
CLK3_RISE[5:0]
28h
R140 (8Ch) CLK3 fall
0
0
CLK3_FALL[5:0]
0Ah
R141 (8Dh) CLK4 rise
0
0
CLK4_RISE[5:0]
00h
R142 (8Eh) CLK4 fall
0
0
CLK4_FALL[5:0]
00h
R143 (8Fh) CLK5 rise
0
0
CLK5_RISE[5:0]
0Ah
R144 (90h) CLK5 fall
0
0
CLK5_FALL[5:0]
28h
R145 (91h) CLK6 rise
0
0
CLK6_RISE[5:0]
0Ah
R146 (92h) CLK6 fall
0
0
CLK6_FALL[5:0]
R160 (A0h) TG config 1
4
OFFSET[3:0]
2
1
0
0
LVDLLRST
LVDLLSTB
CYCMD
R161 (A1h) TG config 2
R162 (A2h) TG config 3
3
0
POLSYNC
0
00h
28h
TGMD
TG_EN
LLENGTH[7:0]
00h
00h
LLENGTH[14:8]
R163 (A3h) TG config 4
DEFAULT
00h
FLAGPIX[7:0]
00h
R164 (A4h) TG config 5
0
R165 (A5h) TG config 6
OE_CLK8
OE_CLK7
OE_CLK6
OE_CLK5
OE_CLK4
OE_CLK3
OE_CLK2
OE_CLK1
FFh
R166 (A6h) TG config 7
0
0
0
0
0
OE_CLK11
OE_CLK10
OE_CLK9
07h
R167 (A7h) TG config 8
INV_CLK8
INV_CLK7
INV_CLK6
INV_CLK5
INV_CLK4
INV_CLK3
INV_CLK2
INV_CLK1
00h
R168 (A8h) TG config 9
0
0
0
0
0
INV_CLK11
INV_CLK10
INV_CLK9
00h
FLAGPIX[14:8]
00h
R169 (A9h) TG config 10
EN_CLK8
EN_CLK7
EN_CLK6
EN_CLK5
EN_CLK4
EN_CLK3
EN_CLK2
EN_CLK1
00h
R170 (AAh) TG config 11
0
0
0
0
0
EN_CLK11
EN_CLK10
EN_CLK9
00h
R171 (ABh) TG config 12
SEL_CLK3
SEL_PCK3[2:0]
SEL_CLK2
SEL_PCK2[2:0]
00h
R172 (ACh) TG config 13
SEL_CLK5
SEL_PCK5[2:0]
SEL_CLK4
SEL_PCK4[2:0]
00h
R173 (ADh) TG config 14
0
SEL_PCK7[2:0]
SEL_CLK6
SEL_PCK6[2:0]
00h
R174 (AEh) TG config 15
0
SEL_PCK9[2:0]
0
SEL_PCK8[2:0]
00h
R175 (AFh) TG config 16
0
SEL_PCK11[2:0]
0
SEL_PCK10[2:0]
00h
R176 (B0h) TG config 17
DEL_PCK5[1:0]
DEL_PCK4[1:0]
DEL_PCK3[1:0]
DEL_PCK2[1:0]
00h
R177 (B1h) TG config 18
DEL_PCK9[1:0]
DEL_PCK8[1:0]
DEL_PCK7[1:0]
DEL_PCK6[1:0]
00h
R178 (B2h) TG config 19
0
0
0
0
DEL_PCK11[1:0]
DEL_PCK10[1:0]
00h
R179 (B3h) TG config 20
0
0
0
INV_M3
R180 (B4h) TG config 21
0
0
0
0
R181 (B5h) TG config 22
0
CYCPAT_PO1[2:0]
0
CYCPAT_PO0[2:0]
00h
R182 (B6h) TG config 23
0
CYCPAT_PO3[2:0]
0
CYCPAT_PO2[2:0]
00h
R183 (B7h) TG config 24
0
CYCPAT_PO5[2:0]
0
CYCPAT_PO4[2:0]
00h
R184 (B8h) TG config 25
0
CYCPAT_PO7[2:0]
0
CYCPAT_PO6[2:0]
00h
R185 (B9h) Clamp enable rise LSB
R186 (BAh) Clamp enable rise MSB
0
R189 (BDh) OB start LSB
R190 (BEh) OB start MSB
64
CLAMP_RISE[14:8]
CLAMP_FALL[7:0]
0
CLAMP_FALL[14:8]
OB_START[7:0]
0
INV_M1
INV_T2
SEL_FLAG[3:0]
CLAMP_RISE[7:0]
R187 (BBh) Clamp enable fall LSB
R188 (BCh) Clamp enable fall MSB
INV_M2
OB_START[14:8]
INV_T1
00h
00h
00h
00h
00h
00h
00h
00h
Rev 4.7
WM8233
REG
NAME
7
R191 (BFh) Peak_det rise LSB
R192 (C0h) Peak_det rise MSB
0
0
0
0
0
0
EN_TP1
EN_TP3
EN_TP4
EN_TP5
EN_TP6
EN_TP8
EN_TP10
EN_TP11
EN_TP12
EN_TP13
R239 (EFh) Toggle point 16 LSB
Rev 4.7
TP11[14:8]
TP12[14:8]
TP13[14:8]
TP14[7:0]
EN_TP14
R237 (EDh) Toggle point 15 LSB
R238 (EEh) Toggle point 15 MSB
TP10[14:8]
TP13[7:0]
R235 (EBh) Toggle point 14 LSB
R236 (ECh) Toggle point 14 MSB
TP9[14:8]
TP12[7:0]
R233 (E9h) Toggle point 13 LSB
R234 (EAh) Toggle point 13 MSB
TP8[14:8]
TP11[7:0]
R231 (E7h) Toggle point 12 LSB
R232 (E8h) Toggle point 12 MSB
TP7[14:8]
TP10[7:0]
R229 (E5h) Toggle point 11 LSB
R230 (E6h) Toggle point 11 MSB
TP6[14:8]
TP9[7:0]
EN_TP9
R227 (E3h) Toggle point 10 LSB
R228 (E4h) Toggle point 10 MSB
TP5[14:8]
TP8[7:0]
R225 (E1h) Toggle point 9 LSB
R226 (E2h) Toggle point 9 MSB
TP4[14:8]
TP7[7:0]
EN_TP7
R223 (DFh) Toggle point 8 LSB
R224 (E0h) Toggle point 8 MSB
TP3[14:8]
TP6[7:0]
R221 (DDh) Toggle point 7 LSB
R222 (DEh) Toggle point 7 MSB
TP2[14:8]
TP5[7:0]
R219 (DBh) Toggle point 6 LSB
R220 (DCh) Toggle point 6 MSB
TP1[14:8]
TP4[7:0]
R217 (D9h) Toggle point 5 LSB
R218 (DAh) Toggle point 5 MSB
TP0[14:8]
TP3[7:0]
R215 (D7h) Toggle point 4 LSB
R216 (D8h) Toggle point 4 MSB
M3_FALL[14:8]
TP2[7:0]
EN_TP2
R213 (D5h) Toggle point 3 LSB
R214 (D6h) Toggle point 3 MSB
M3_RISE[14:8]
TP1[7:0]
R211 (D3h) Toggle point 2 LSB
R212 (D4h) Toggle point 2 MSB
M2_FALL[14:8]
TP0[7:0]
GEN_TP0
R209 (D1h) Toggle point 1 LSB
R210 (D2h) Toggle point 1 MSB
M2_RISE[14:8]
M3_FALL[7:0]
R207 (CFh) Toggle point 0 LSB
R208 (D0h) Toggle point 0 MSB
M1_FALL[14:8]
M3_RISE[7:0]
R205 (CDh) Mask pulse 3 fall LSB
R206 (CEh) Mask pulse 3 fall MSB
M1_RISE[14:8]
M2_FALL[7:0]
R203 (CBh) Mask pulse 3 rise LSB
R204 (CCh) Mask pulse 3 rise MSB
PEAKDET_FALL[14:8]
M2_RISE[7:0]
R201 (C9h) Mask pulse 2 fall LSB
R202 (CAh) Mask pulse 2 fall MSB
PEAKDET_RISE[14:8]
M1_FALL[7:0]
0
R199 (C7h) Mask pulse 2 rise LSB
R200 (C8h) Mask pulse 2 rise MSB
3
M1_RISE[7:0]
R197 (C5h) Mask pulse 1 fall LSB
R198 (C6h) Mask pulse 1 fall MSB
4
PEAKDET_FALL[7:0]
0
R195 (C3h) Mask pulse 1 rise LSB
R196 (C4h) Mask pulse 1 rise MSB
5
PEAKDET_RISE[7:0]
R193 (C1h) Peak_det fall LSB
R194 (C2h) Peak_det fall MSB
6
TP14[14:8]
TP15[7:0]
EN_TP15
TP15[14:8]
TP16[7:0]
2
1
0
DEFAULT
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
65
WM8233
REG
NAME
R240 (F0h) Toggle point 16 MSB
7
6
5
EN_TP17
EN_TP18
EN_TP20
EN_TP22
00h
00h
00h
00h
TP23[14:8]
00h
TP24[7:0]
EN_TP24
00h
TP24[14:8]
00h
TP25[7:0]
EN_TP25
00h
TP25[14:8]
00h
TP26[7:0]
EN_TP26
00h
TP26[14:8]
00h
TP27[7:0]
EN_TP27
00h
TP27[14:8]
00h
TP28[7:0]
EN_TP28
00h
TP28[14:8]
00h
TP29[7:0]
EN_TP29
00h
TP29[14:8]
R267 (10Bh) Toggle point 30 LSB
R268 (10Ch) Toggle point 30 MSB
00h
TP23[7:0]
EN_TP23
R265 (109h) Toggle point 29 LSB
R266 (10Ah) Toggle point 29 MSB
00h
TP22[14:8]
R263 (107h) Toggle point 28 LSB
R264 (108h) Toggle point 28 MSB
00h
TP22[7:0]
R261 (105h) Toggle point 27 LSB
R262 (106h) Toggle point 27 MSB
00h
TP21[14:8]
R259 (103h) Toggle point 26 LSB
R260 (104h) Toggle point 26 MSB
00h
TP21[7:0]
EN_TP21
R257 (101h) Toggle point 25 LSB
R258 (102h) Toggle point 25 MSB
00h
TP20[14:8]
R255 (FFh) Toggle point 24 LSB
R256 (100h) Toggle point 24 MSB
00h
TP19[14:8]
R253 (FDh) Toggle point 23 LSB
R254 (FEh) Toggle point 23 MSB
00h
TP20[7:0]
R251 (FBh) Toggle point 22 LSB
R252 (FCh) Toggle point 22 MSB
00h
TP19[7:0]
EN_TP19
00h
TP30[7:0]
EN_TP30
00h
TP30[14:8]
R269 (10Dh) Toggle point 31 LSB
DEFAULT
00h
TP18[14:8]
R249 (F9h) Toggle point 21 LSB
R250 (FAh) Toggle point 21 MSB
0
TP17[14:8]
R247 (F7h) Toggle point 20 LSB
R248 (F8h) Toggle point 20 MSB
1
TP18[7:0]
R245 (F5h) Toggle point 19 LSB
R246 (F6h) Toggle point 19 MSB
2
TP17[7:0]
R243 (F3h) Toggle point 18 LSB
R244 (F4h) Toggle point 18 MSB
3
TP16[14:8]
R241 (F1h) Toggle point 17 LSB
R242 (F2h) Toggle point 17 MSB
4
EN_TP16
00h
TP31[7:0]
00h
R270 (10Eh) Toggle point 31 MSB
EN_TP31
R271 (10Fh) Polarity setting of T1 1
POL7_T1
POL6_T1
POL5_T1
POL4_T1
POL3_T1
POL2_T1
R272 (110h) Polarity setting of T1 2
POL15_T1
POL14_T1
POL13_T1
POL12_T1
POL11_T1
POL10_T1
R273 (111h) Polarity setting of T1 3
POL23_T1
POL22_T1
POL21_T1
POL20_T1
POL19_T1
POL18_T1
R274 (112h) Polarity setting of T1 4
POL31_T1
POL30_T1
POL29_T1
POL28_T1
POL27_T1
POL26_T1
R275 (113h) Polarity setting of T2 1
POL7_T2
POL6_T2
POL5_T2
POL4_T2
POL3_T2
POL2_T2
R276 (114h) Polarity setting of T2 2
POL15_T2
POL14_T2
POL13_T2
POL12_T2
POL11_T2
R277 (115h) Polarity setting of T2 3
POL23_T2
POL22_T2
POL21_T2
POL20_T2
R278 (116h) Polarity setting of T2 4
POL31_T2
POL30_T2
POL29_T2
POL28_T2
R279 (117h) Polarity setting of P0 1
POL7_PO0
POL6_PO0
POL5_PO0
R280 (118h) Polarity setting of P0 2
POL15_PO0
POL14_PO0
TP31[14:8]
00h
POL1_T1
POL0_T1
FFh
POL9_T1
POL8_T1
FFh
POL17_T1
POL16_T1
FFh
POL25_T1
POL24_T1
FFh
POL1_T2
POL0_T2
FFh
POL10_T2
POL9_T2
POL8_T2
FFh
POL19_T2
POL18_T2
POL17_T2
POL16_T2
FFh
POL27_T2
POL26_T2
POL25_T2
POL24_T2
FFh
POL4_PO0
POL3_PO0
POL2_PO0
POL1_PO0
POL0_PO0
00h
POL13_PO0
POL12_PO0
POL11_PO0
POL10_PO0
POL9_PO0
POL8_PO0
00h
R281 (119h) Polarity setting of P0 3
POL23_PO0
POL22_PO0
POL21_PO0
POL20_PO0
POL19_PO0
POL18_PO0
POL17_PO0
POL16_PO0
00h
R282 (11Ah) Polarity setting of P0 4
POL31_PO0
POL30_PO0
POL29_PO0
POL28_PO0
POL27_PO0
POL26_PO0
POL25_PO0
POL24_PO0
00h
R283 (11Bh) Polarity setting of P1 1
POL7_PO1
POL6_PO1
POL5_PO1
POL4_PO1
POL3_PO1
POL2_PO1
POL1_PO1
POL0_PO1
00h
R284 (11Ch) Polarity setting of P1 2
POL15_PO1
POL14_PO1
POL13_PO1
POL12_PO1
POL11_PO1
POL10_PO1
POL9_PO1
POL8_PO1
00h
R285 (11Dh) Polarity setting of P1 3
POL23_PO1
POL22_PO1
POL21_PO1
POL20_PO1
POL19_PO1
POL18_PO1
POL17_PO1
POL16_PO1
00h
R286 (11Eh) Polarity setting of P1 4
POL31_PO1
POL30_PO1
POL29_PO1
POL28_PO1
POL27_PO1
POL26_PO1
POL25_PO1
POL24_PO1
00h
R287 (11Fh) Polarity setting of P2 1
POL7_PO2
POL6_PO2
POL5_PO2
POL4_PO2
POL3_PO2
POL2_PO2
POL1_PO2
POL0_PO2
00h
R288 (120h) Polarity setting of P2 2
POL15_PO2
POL14_PO2
POL13_PO2
POL12_PO2
POL11_PO2
POL10_PO2
POL9_PO2
POL8_PO2
00h
66
Rev 4.7
WM8233
7
6
5
4
3
2
1
0
DEFAULT
R289 (121h) Polarity setting of P2 3
REG
NAME
POL23_PO2
POL22_PO2
POL21_PO2
POL20_PO2
POL19_PO2
POL18_PO2
POL17_PO2
POL16_PO2
00h
R290 (122h) Polarity setting of P2 4
POL31_PO2
POL30_PO2
POL29_PO2
POL28_PO2
POL27_PO2
POL26_PO2
POL25_PO2
POL24_PO2
00h
R291 (123h) Polarity setting of P3 1
POL7_PO3
POL6_PO3
POL5_PO3
POL4_PO3
POL3_PO3
POL2_PO3
POL1_PO3
POL0_PO3
00h
R292 (124h) Polarity setting of P3 2
POL15_PO3
POL14_PO3
POL13_PO3
POL12_PO3
POL11_PO3
POL10_PO3
POL9_PO3
POL8_PO3
00h
R293 (125h) Polarity setting of P3 3
POL23_PO3
POL22_PO3
POL21_PO3
POL20_PO3
POL19_PO3
POL18_PO3
POL17_PO3
POL16_PO3
00h
R294 (126h) Polarity setting of P3 4
POL31_PO3
POL30_PO3
POL29_PO3
POL28_PO3
POL27_PO3
POL26_PO3
POL25_PO3
POL24_PO3
00h
R295 (127h) Polarity setting of P4 1
POL7_PO4
POL6_PO4
POL5_PO4
POL4_PO4
POL3_PO4
POL2_PO4
POL1_PO4
POL0_PO4
00h
R296 (128h) Polarity setting of P4 2
POL15_PO4
POL14_PO4
POL13_PO4
POL12_PO4
POL11_PO4
POL10_PO4
POL9_PO4
POL8_PO4
00h
R297 (129h) Polarity setting of P4 3
POL23_PO4
POL22_PO4
POL21_PO4
POL20_PO4
POL19_PO4
POL18_PO4
POL17_PO4
POL16_PO4
00h
R298 (12Ah) Polarity setting of P4 4
POL31_PO4
POL30_PO4
POL29_PO4
POL28_PO4
POL27_PO4
POL26_PO4
POL25_PO4
POL24_PO4
00h
R299 (12Bh) Polarity setting of P5 1
POL7_PO5
POL6_PO5
POL5_PO5
POL4_PO5
POL3_PO5
POL2_PO5
POL1_PO5
POL0_PO5
00h
R300 (12Ch) Polarity setting of P5 2
POL15_PO5
POL14_PO5
POL13_PO5
POL12_PO5
POL11_PO5
POL10_PO5
POL9_PO5
POL8_PO5
00h
R301 (12Dh) Polarity setting of P5 3
POL23_PO5
POL22_PO5
POL21_PO5
POL20_PO5
POL19_PO5
POL18_PO5
POL17_PO5
POL16_PO5
00h
R302 (12Eh) Polarity setting of P5 4
POL31_PO5
POL30_PO5
POL29_PO5
POL28_PO5
POL27_PO5
POL26_PO5
POL25_PO5
POL24_PO5
00h
R303 (12Fh) Polarity setting of P6 1
POL7_PO6
POL6_PO6
POL5_PO6
POL4_PO6
POL3_PO6
POL2_PO6
POL1_PO6
POL0_PO6
00h
R304 (130h) Polarity setting of P6 2
POL15_PO6
POL14_PO6
POL13_PO6
POL12_PO6
POL11_PO6
POL10_PO6
POL9_PO6
POL8_PO6
00h
R305 (131h) Polarity setting of P6 3
POL23_PO6
POL22_PO6
POL21_PO6
POL20_PO6
POL19_PO6
POL18_PO6
POL17_PO6
POL16_PO6
00h
R306 (132h) Polarity setting of P6 4
POL31_PO6
POL30_PO6
POL29_PO6
POL28_PO6
POL27_PO6
POL26_PO6
POL25_PO6
POL24_PO6
00h
R307 (133h) Polarity setting of P7 1
POL7_PO7
POL6_PO7
POL5_PO7
POL4_PO7
POL3_PO7
POL2_PO7
POL1_PO7
POL0_PO7
00h
R308 (134h) Polarity setting of P7 2
POL15_PO7
POL14_PO7
POL13_PO7
POL12_PO7
POL11_PO7
POL10_PO7
POL9_PO7
POL8_PO7
00h
R309 (135h) Polarity setting of P7 3
POL23_PO7
POL22_PO7
POL21_PO7
POL20_PO7
POL19_PO7
POL18_PO7
POL17_PO7
POL16_PO7
00h
R310 (136h) Polarity setting of P7 4
POL31_PO7
POL30_PO7
POL29_PO7
POL28_PO7
POL27_PO7
POL26_PO7
POL25_PO7
POL24_PO7
00h
0
0
0
0
USER_KEY
00h
0
USER_KEY2
EXTENDED PAGE REGISTERS
R432 (1B0h) User access control
0
0
0
R436 (1B4h) LDO2 control
0
0
0
R448 (1C0h) USER_KEY2
0
0
0
0
0
0
R459 (1CBh) Comp control
0
0
0
0
0
0
LDO2 VSEL
10h
PT_COMP[1:0]
00h
01h
Notes:
1.
To change the LDO2 control, the USER_KEY bit must be set to ‘1’.
2.
If it’s not required to change the LDO2 voltage, these registers must be set as default.
3.
To change the Comp control, the USER_KEY2 bit must be set to ‘1’.
4.
If it’s not required to change this register, must be set as default.
REGISTER BITS BY ADDRESS
REGISTER
BIT
LABEL
7:0
SW_RESET
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R0 (00h)
Software
_CHIP_ID[7:0]
0011_0011 A write issues a software reset, and returns all control
registers to their default values.
A read returns lower bits of the device ID
Reset
/Chip ID 1
Register 00h Software Reset/Chip ID 1
REGISTER
BIT
LABEL
7:0
CHIP_ID[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R1 (01h)
1000_0010 A read returns upper bits of the device ID
Chip ID 2
Rev 4.7
67
WM8233
Register 01h Chip ID 2
REGISTER
BIT
LABEL
DEFAULT
3:0
CHIP_REV[3:0]
0000
BIT
LABEL
DEFAULT
4
ADC3PD
0
DESCRIPTION
REFER TO
ADDRESS
R2 (02h)
A read returns the device revision number
Chip Rev
Register 02h Chip Rev
REGISTER
DESCRIPTION
REFER TO
ADDRESS
R3 (03h)
ADC powerdown control for channels 5&6
(related PGA and digits goes power down)
Setup Reg 1
0 = normal operation
1 = power down
3
ADC2PD
0
ADC powerdown control for channels 3&4
(related PGA and digits goes power down)
0 = normal operation
1 = power down
2
ADC1PD
0
ADC powerdown control for channels 1&2
(related PGA and digits goes power down)
0 = normal operation
1 = power down
1
PDMD
0
power down mode
0 : standby
1 : sleep
0
PD
0
power down
0 : normal operation
1 : power down
Register 03h Setup Reg 1
REGISTER
BIT
LABEL
DEFAULT
VRLC
0
DESCRIPTION
REFER TO
ADDRESS
R4 (04h)
7
Setup Reg 2
selects output range of VRLCDAC
0 = AVDD
_TOP_SEL
1 = 1.6V
6
PGAFS
0
control PGA input polarity
0 = negative
1 = positive
5
ADCFS
0
control ADC full scale range
0 = 1.2V
1 = 1.8V
1
CLPMD
0
select clamp mode
0 = line clamp
1 = bit clamp
0
CDS
0
CDS mode control
0 = Non-CDS (S/H) mode
1 = CDS mode
Register 04h Setup Reg 2
68
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
4
SF_BYPLS
1
DESCRIPTION
REFER TO
ADDRESS
R5 (05h)
bypass level shift of VRLC source follower
0 = use level shifter
Setup Reg 3
1 = bypass level shifter
3:2
PT_SF[1:0]
11
source follower power trim
00 = 1mA
01 = 2mA
10 = 3mA
11 = 4mA
1
SF_INP
0
control source follower on signal inputs INP*
0 = disabled
1 = enabled
0
SF_VRLC
0
control source follower on VRLC
0 = disabled
1 = enabled
Register 05h Setup Reg 3
REGISTER
BIT
LABEL
DEFAULT
7
VRLCEN
1
DESCRIPTION
REFER TO
ADDRESS
R6 (06h)
enable for VRLC DAC
0 = disabled
VRLC control
1 = enabled
6:5
VRLC_ISEL
00
selects output current capability
00 = Up to 2mA
[1:0]
01 = Up to 3mA
10 = Up to 4mA
11 = reserved (Up to 2mA)
4:0
VRLC_VSEL
0_1010
VRLC output voltage setting
[4:0]
when VRLC_TOP_SEL=0 (AVDD)
3.3/AVDD * ( 0.2 + 0.09xVRLC_VSEL[4:0])
when VRLC_TOP_SEL=1 (1.6V)
1.6 - 0.048*(31-VRLC_VSEL[4:0])
Register 06h VRLC control
REGISTER
BIT
LABEL
DEFAULT
7
OE_OP
0
DESCRIPTION
REFER TO
ADDRESS
R7 (07h)
output enable of dataout (CMOS/LVDS)
when HIZCTRL=0
output control
0= Hi-Z
1= enable dataout
when HIZCTRL=1
OE_OP state is neglected and enable dataout
6
OUTPD
1
control data output
0 = enable data output
1 = mask data output (data out=0)
5
CMOSMODE
0
enable CMOS output mode
0 = LVDS output mode based on LVDSMODE[2:0]
1 = CMOS output mode
4
Rev 4.7
OUTSYNC
0
enable syncronous output mode
69
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0 = continuous
1 = syncronized dataout with LineStart signal
3
LVDSORDER
0
control LVDS data output order
0 = descending order
1 = ascending order
2:0
LVDSMODE
000
select LVDS dataoutput format
000 = 10bit 5pair + clk
[2:0]
001 = 10bit 3pair + clk
011 = 12bit 4pair + clk
101 = 16bit 5pair + clk
110 = 16bit 3pair + clk
Others = reserved
Register 07h output control
REGISTER
BIT
LABEL
DEFAULT
6
LVDS_POL
0
DESCRIPTION
REFER TO
ADDRESS
R8 (08h)
invert LVDS outputs polarity
0 = normal
LVDS control
1 = inverted
5:3
LVDS_AMP
110
LVDS amplitude select
000 = 50mV
[2:0]
001 = 100mV
010 = 150mV
011 = 200mV
All other codes are Reserved.
Note that the default code (110) should not be used.
2:0
LVDS_VCM
101
LVDS common mode select
000 = 0.70V
[2:0]
001 = 0.80V
010 = 0.90V
011 = 1.00V
100 = 1.15V
101 = 1.25V
110 = 1.35V
111 = 1.45V
Register 08h LVDS control
REGISTER
BIT
LABEL
DEFAULT
6:0
LVCKPAT
110_0011
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
R9 (09h)
LVDS clock
pattern
LVDS clock pattern
(output MSB first)
[6:0]
Register 09h LVDS clock pattern
REGISTER
BIT
LABEL
DEFAULT
7:4
FLAG_S1
0001
ADDRESS
R10 (0Ah)
flag control 1
[3:0]
output dataflag as S1
(valid only LVDS mode)
0000 = always low
70
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0001 = start flag
0010 = reserved
0011 = reserved
0100 = reserved
0101 = channel ID[0]
0110 = channel ID[1]
0111 = channel ID[2]
1000 = channel ID[3]
1001 = reserved
1010 = reserved
1011 = reserved
1100 = reserved
1101 = reserved
1110 = reserved
1111 = always high
3:0
FLAG_S0
0000
output dataflag as S0
(valid only LVDS mode)
[3:0]
0000 = always low
0001 = start flag
0010 = reserved
0011 = reserved
0100 = reserved
0101 = channel ID[0]
0110 = channel ID[1]
0111 = channel ID[2]
1000 = channel ID[3]
1001 = reserved
1010 = reserved
1011 = reserved
1100 = reserved
1101 = reserved
1110 = reserved
1111 = always high
Register 0Ah flag control 1
REGISTER
BIT
LABEL
DEFAULT
7:4
FLAG_S3
0000
DESCRIPTION
REFER TO
ADDRESS
R11 (0Bh)
flag control 2
[3:0]
output dataflag as S3
(valid only LVDS mode)
0000 = always low
0001 = start flag
0010 = reserved
0011 = reserved
0100 = reserved
0101 = channel ID[0]
0110 = channel ID[1]
0111 = channel ID[2]
1000 = channel ID[3]
1001 = reserved
1010 = reserved
1011 = reserved
1100 = reserved
Rev 4.7
71
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
1101 = reserved
1110 = reserved
1111 = always high
3:0
FLAG_S2
0000
output dataflag as S2
(valid only LVDS mode)
[3:0]
0000 = always low
0001 = start flag
0010 = reserved
0011 = reserved
0100 = reserved
0101 = channel ID[0]
0110 = channel ID[1]
0111 = channel ID[2]
1000 = channel ID[3]
1001 = reserved
1010 = reserved
1011 = reserved
1100 = reserved
1101 = reserved
1110 = reserved
1111 = always high
Register 0Bh flag control 2
REGISTER
BIT
LABEL
DEFAULT
3:0
FLAG_S4
0000
DESCRIPTION
REFER TO
ADDRESS
R12 (0Ch)
flag control 3
output dataflag as S4
(valid only LVDS mode)
[3:0]
0000 = always low
0001 = start flag
0010 = reserved
0011 = reserved
0100 = reserved
0101 = channel ID[0]
0110 = channel ID[1]
0111 = channel ID[2]
1000 = channel ID[3]
1001 = reserved
1010 = reserved
1011 = reserved
1100 = reserved
1101 = reserved
1110 = reserved
1111 = always high
Register 0Ch flag control 3
REGISTER
BIT
LABEL
DEFAULT
3
DRV_CTRL
0
DESCRIPTION
REFER TO
ADDRESS
R13 (0Dh)
CMOS
drivability
72
CMOS output drivability control mode
0 = OP_DRV controls drivability of all output pins OP*
1 = OP_DRV is invalid, and OP*_DRV control drivability of
output pin OP*
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
2:0
OP_DRV[2:0]
000
DESCRIPTION
REFER TO
ADDRESS
control 1
CMOS output drivability control when DRV_CTRL=0
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 0Dh CMOS drivability control 1
REGISTER
BIT
LABEL
DEFAULT
6:4
OP1_DRV[2:0]
000
DESCRIPTION
REFER TO
ADDRESS
R14 (0Eh)
CMOS output (OP2) drivability
CMOS
000: Hi-Z
drivability
001: 1mA
control 2
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
2:0
OP0_DRV[2:0]
000
CMOS output (OP1) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 0Eh CMOS drivability control 2
REGISTER
BIT
LABEL
DEFAULT
6:4
OP3_DRV[2:0]
000
DESCRIPTION
REFER TO
ADDRESS
R15 (0Fh)
CMOS output (OP4) drivability
CMOS
000: Hi-Z
drivability
001: 1mA
control 3
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
2:0
OP2_DRV[2:0]
000
CMOS output (OP3) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 0Fh CMOS drivability control 3
Rev 4.7
73
WM8233
REGISTER
BIT
LABEL
DEFAULT
6:4
OP5_DRV[2:0]
000
DESCRIPTION
REFER TO
ADDRESS
R16 (10h)
CMOS output (OP6) drivability
CMOS
000: Hi-Z
drivability
001: 1mA
control 4
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
2:0
OP4_DRV[2:0]
000
CMOS output (OP5) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 10h CMOS drivability control 4
REGISTER
BIT
LABEL
DEFAULT
6:4
OP7_DRV[2:0]
000
DESCRIPTION
REFER TO
ADDRESS
R17 (11h)
CMOS output (OP8) drivability
CMOS
000: Hi-Z
drivability
001: 1mA
control 5
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
2:0
OP6_DRV[2:0]
000
CMOS output (OP7) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 11h CMOS drivability control 5
REGISTER
BIT
LABEL
DEFAULT
6:4
OP9_DRV[2:0]
000
DESCRIPTION
REFER TO
ADDRESS
R18 (12h)
CMOS output (OP10) drivability
CMOS
000: Hi-Z
drivability
001: 1mA
control 6
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
2:0
74
OP8_DRV[2:0]
000
CMOS output (OP9) drivability
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 12h CMOS drivability control 6
REGISTER
BIT
LABEL
DEFAULT
6:4
OC2_DRV[2:0]
000
ADDRESS
R19 (13h)
CMOS output (OC2) drivability
CMOS
000: Hi-Z
drivability
001: 1mA
control 7
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
2:0
OC1_DRV[2:0]
000
CMOS output (OC1) drivability
000: Hi-Z
001: 1mA
010: 2mA
011: 3mA
100: 4mA
101: 5mA
110/111: 6mA
Register 13h CMOS drivability control 7
REGISTER
BIT
LABEL
DEFAULT
7
PGMARCH
0
DESCRIPTION
REFER TO
ADDRESS
R20 (14h)
pattern generator marching mode enable
0 = controlled by PGPAT
PG config
1 = marching pattern
6:5
PGPAT[1:0]
00
select pattern generator output
00 = fixed value
01 = vertical ramp
10 = horizontal ramp
11 = patch
4
PGINV
0
invert pattern generator output
0 = normal
1 = invert
3
SEL_PGZ
0
select output of pattern generator (IN5,6)
0 = normal ouput
1 = output generated digital pattern instead of ADC outputs
2
SEL_PGY
0
select output of pattern generator (IN3,4)
0 = normal ouput
1 = output generated digital pattern instead of ADC outputs
1
SEL_PGX
0
select output of pattern generator (IN1,2)
0 = normal ouput
Rev 4.7
75
WM8233
REGISTER
BIT
LABEL
DEFAULT
0
PGEN
0
DESCRIPTION
REFER TO
ADDRESS
1 = output generated digital pattern instead of ADC outputs
enable pattern generator
0 = disable
1 = enable
Register 14h PG config
REGISTER
BIT
LABEL
7:0
PGLEVEL[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R21 (15h)
0000_0000 parameter of pattern generator
PGCODE
LSB
Register 15h PGCODE LSB
REGISTER
BIT
LABEL
7:0
PGLEVEL[15:8]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R22 (16h)
0000_0000 parameter of pattern generator
PGCODE
MSB
Register 16h PGCODE MSB
REGISTER
BIT
LABEL
7:0
PGWIDTH1[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R23 (17h)
0000_0000 parameter of pattern generator
PG width 1
Register 17h PG width 1
REGISTER
BIT
LABEL
7:0
PGWIDTH2[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R24 (18h)
0000_0000 parameter of pattern generator
PG width 2
Register 18h PG width 2
REGISTER
BIT
LABEL
DEFAULT
2:0
MONCLK[2:0]
000
DESCRIPTION
REFER TO
ADDRESS
R25 (19h)
select monitor output
0xx = Low (monitor disabled)
clock monitor
100 = RSMP
101 = VSMP
110 = ACLK
111 = OCLK
Register 19h clock monitor
REGISTER
BIT
LABEL
DEFAULT
2
PLL_LPF_RST
0
DESCRIPTION
REFER TO
ADDRESS
R26 (1Ah)
76
Reset Loop Filter.
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0 = normal
PLL control 1
1 = reset
1
PLL_CP_PD
0
power down Charge Pump.
0 = normal
1 = power down
0
PLL_VCO_PD
0
power down VCO
0 = normal
1 = power down
Register 1Ah PLL control 1
REGISTER
BIT
LABEL
DEFAULT
6
PLL_LPF_SEL
0
DESCRIPTION
REFER TO
ADDRESS
R27 (1Bh)
Control Loop Filter to improve the performance.
Note: these settings are applicable for the specific
conditions.
PLL control 2
0 = normal filter
1 = larger resistor to improve PLL cutoff freq (for SSC)
3:2
PLL_PFD_CTRL
10
Control reset delay to improve PFD sensitivity.
00 = 1ns delay
[1:0]
01 = 2.2ns delay
10 = 3.4ns delay (default)
11 = 5.8ns delay
1:0
PLL_CP_GAIN
01
Control Charge Pump current.
00 = 0.5uA
[1:0]
01 = 1uA (default)
10 = 2uA
11 = 4uA
Register 1Bh PLL control 2
REGISTER
BIT
LABEL
DEFAULT
6:4
PLL_EXDIV
_SEL[2:0]
001
DESCRIPTION
REFER TO
ADDRESS
R28 (1Ch)
PLL divider
control 1
Select EX DIV ratio.
Need to set according to input frequency. See details in
“PLL DLL Setup”
000 = 1
001 = 2
010 = 4
011 = 8
100 = 16
101 to 111 = reserved.
3:0
PLL_FBDIV
_SEL[3:0]
0011
Select FB DIV ratio. (ReadOnly)
0000 = 1
0001 = 2
0010 = 3
0011 = 4
0100 = 6
0101 = 8
0110 = 9
0111 = 12
1000 = 18
1001 to 1111 = reserved.
Rev 4.7
77
WM8233
Register 1Ch PLL divider control 1
REGISTER
BIT
LABEL
DEFAULT
5:4
PLL_POSTDIV2
01
DESCRIPTION
REFER TO
ADDRESS
R29 (1Dh)
PLL divider
control 2
3:0
PLL_POSTDIV1
Select POST DIV2 ratio.
(Read Only)
_SEL[1:0]
0011
00 = 1
01 = 2
10 = 4
11 = 6
Select POST DIV1 ratio. (Read Only)
0000 = 1
0001 = 2
0010 = 3
0011 = 4
0100 = 6
0101 = 8
0110 = 9
0111 = 12
1000 = 18
1001 to 1111 = reserved.
_SEL[3:0]
Register 1Dh PLL divider control 2
REGISTER
BIT
LABEL
DEFAULT
3:2
INTM[1:0]
00
DESCRIPTION
REFER TO
ADDRESS
R35 (23h)
Cycle mode
control
When LINEBYLINE=1,
controls the GAIN and DAC mux selector when ACYC=0
1
ACYC
0
00 = IN2
01 = IN4
10 = IN6
11 = reserved
when LINEBYLINE=1, determines the function of the MUX
control
0 = decided by INTM register
1= auto-cycling enabled
0
LINEBYLINE
0
select line by line operation
0=normal operation
1=Line by Line operation
Register 23h cycle mode control
REGISTER
BIT
LABEL
7:0
DACIN1[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R37 (25h)
DAC IN1
1000_0000 DACIN1 offset value
250 * (DACIN1[7:0] -127.5) / 127.5 [mV]
Register 25h DAC IN1
REGISTER
BIT
LABEL
7:0
DACIN2[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R38 (26h)
DAC IN2
1000_0000 DACIN2offset value
250 * (DACIN2[7:0] -127.5) / 127.5 [mV]
Register 26h DAC IN2
78
Rev 4.7
WM8233
REGISTER
BIT
LABEL
7:0
DACIN3[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R40 (28h)
DAC IN3
1000_0000 DACIN3offset value
250 * (DACIN3[7:0] -127.5) / 127.5 [mV]
Register 28h DAC IN3
REGISTER
BIT
LABEL
7:0
DACIN4[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R41 (29h)
DAC IN4
1000_0000 DACIN4 offset value
250 * (DACIN4[7:0] -127.5) / 127.5 [mV]
Register 29h DAC IN4
REGISTER
BIT
LABEL
7:0
DACIN5[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R43 (2Bh)
DAC IN5
1000_0000 DACIN5offset value
250 * (DACIN5[7:0] -127.5) / 127.5 [mV]
Register 2Bh DAC IN5
REGISTER
BIT
LABEL
7:0
DACIN6[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R44 (2Ch)
DAC IN6
1000_0000 DACIN6offset value
250 * (DACIN6[7:0] -127.5) / 127.5 [mV]
Register 2Ch DAC IN6
REGISTER
BIT
LABEL
DEFAULT
4:0
AGAININ1[4:0]
0_0001
DESCRIPTION
REFER TO
ADDRESS
R46 (2Eh)
PGA IN1 gain code
gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
AGAIN IN1
Register 2Eh AGAIN IN1
REGISTER
BIT
LABEL
DEFAULT
4:0
AGAININ2[4:0]
0_0001
DESCRIPTION
REFER TO
ADDRESS
R47 (2Fh)
PGA IN2 gain code
gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
AGAIN IN2
Register 2Fh AGAIN IN2
REGISTER
BIT
LABEL
DEFAULT
4:0
AGAININ3[4:0]
0_0001
DESCRIPTION
REFER TO
ADDRESS
R49 (31h)
PGA IN3 gain code
gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
AGAIN IN3
Register 31h AGAIN IN3
REGISTER
BIT
LABEL
DEFAULT
4:0
AGAININ4[4:0]
0_0001
DESCRIPTION
REFER TO
ADDRESS
R50 (32h)
Rev 4.7
PGA IN4 gain code
79
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
AGAIN IN4
Register 32h AGAIN IN4
REGISTER
BIT
LABEL
DEFAULT
4:0
AGAININ5[4:0]
0_0001
DESCRIPTION
REFER TO
ADDRESS
R52 (34h)
PGA IN5 gain code
gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
AGAIN IN5
Register 34h AGAIN IN5
REGISTER
BIT
LABEL
DEFAULT
4:0
AGAININ6[4:0]
0_0001
DESCRIPTION
REFER TO
ADDRESS
R53 (35h)
PGA IN6 gain code
gain(V/V) = 0.6 + 0.3*AGAIN*[4:0]
AGAIN IN6
Register 35h AGAIN IN6
REGISTER
BIT
LABEL
DEFAULT
7:4
DGAININ1[3:0]
0000
DESCRIPTION
REFER TO
ADDRESS
R56 (38h)
lower bits of digital gain IN1
1111_1111_1111 = 1.99[V/V]
DGAIN IN1
...
LSB
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 38h DGAIN IN1 LSB
REGISTER
BIT
LABEL
7:0
DGAININ1
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R57 (39h)
DGAIN IN1
[11:4]
1000_0000 upper bits of digital gain IN1
1111_1111_1111 = 1.99[V/V]
...
MSB
1000_0000_0000= 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 39h DGAIN IN1 MSB
REGISTER
BIT
LABEL
DEFAULT
7:4
DGAININ2
0000
DESCRIPTION
REFER TO
ADDRESS
R58 (3Ah)
DGAIN IN2
LSB
[3:0]
lower bits of digital gain IN2
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
80
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 3Ah DGAIN IN2 LSB
REGISTER
BIT
LABEL
7:0
DGAININ2
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R59 (3Bh)
DGAIN IN2
[11:4]
1000_0000 upper bits of digital gain IN2
1111_1111_1111 = 1.99[V/V]
...
MSB
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 3Bh DGAIN IN2 MSB
REGISTER
BIT
LABEL
DEFAULT
7:4
DGAININ3
0000
DESCRIPTION
REFER TO
ADDRESS
R62 (3Eh)
DGAIN IN3
lower bits of digital gain IN3
1111_1111_1111 = 1.99[V/V]
[3:0]
...
LSB
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000= 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 3Eh DGAIN IN3 LSB
REGISTER
BIT
LABEL
7:0
DGAININ3
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R63 (3Fh)
DGAIN IN3
MSB
[11:4]
1000_0000 upper bits of digital gain IN3
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000= 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 3Fh DGAIN IN3 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
Rev 4.7
81
WM8233
REGISTER
BIT
LABEL
DEFAULT
7:4
DGAININ4
0000
DESCRIPTION
REFER TO
ADDRESS
R64 (40h)
DGAIN IN4
LSB
lower bits of digital gain IN4
1111_1111_1111 = 1.99[V/V]
[3:0]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 40h DGAIN IN4 LSB
REGISTER
BIT
LABEL
7:0
DGAININ4
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R65 (41h)
DGAIN IN4
MSB
[11:4]
1000_0000 upper bits of digital gain IN4
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 41h DGAIN IN4 MSB
REGISTER
BIT
LABEL
DEFAULT
7:4
DGAININ5
0000
DESCRIPTION
REFER TO
ADDRESS
R68 (44h)
DGAIN IN5
lower bits of digital gain IN5
1111_1111_1111 = 1.99[V/V]
[3:0]
...
LSB
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 44h DGAIN IN5 LSB
REGISTER
BIT
LABEL
7:0
DGAININ5
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R69 (45h)
DGAIN IN5
MSB
[11:4]
1000_0000 upper bits of digital gain IN5
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 45h DGAIN IN5 MSB
82
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
7:4
DGAININ6
0000
DESCRIPTION
REFER TO
ADDRESS
R70 (46h)
DGAIN IN6
lower bits of digital gain IN6
1111_1111_1111 = 1.99[V/V]
[3:0]
...
LSB
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000= reserved
Register 46h DGAIN IN6 LSB
REGISTER
BIT
LABEL
7:0
DGAININ6
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R71 (47h)
DGAIN IN6
MSB
[11:4]
1000_0000 upper bits of digital gain IN6
1111_1111_1111 = 1.99[V/V]
...
1000_0000_0000 = 1.0[V/V]
...
0100_0000_0000 = 0.5[V/V]
0011_1111_1111 = reserved
…
0000_0000_0000 = reserved
Register 47h DGAIN IN6 MSB
REGISTER
BIT
LABEL
7:0
TARGETIN1
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R73 (49h)
BLC IN1
0000_0000 target black level for IN1
[7:0]
target
Register 49h BLC IN1 target
REGISTER
BIT
LABEL
7:0
TARGETIN2
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R74 (4Ah)
BLC IN2
0000_0000 target black level for IN2
[7:0]
target
Register 4Ah BLC IN2 target
REGISTER
BIT
LABEL
7:0
TARGETIN3
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R76 (4Ch)
BLC IN3
0000_0000 target black level for IN3
[7:0]
target
Register 4Ch BLC IN3 target
Rev 4.7
83
WM8233
REGISTER
BIT
LABEL
7:0
TARGETIN4
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R77 (4Dh)
BLC IN4
0000_0000 target black level for IN4
[7:0]
target
Register 4Dh BLC IN4 target
REGISTER
BIT
LABEL
7:0
TARGETIN5
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R79 (4Fh)
BLC IN5
0000_0000 target black level for IN5
[7:0]
target
Register 4Fh BLC IN5 target
REGISTER
BIT
LABEL
7:0
TARGETIN6
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R80 (50h)
BLC IN6
0000_0000 target black level for IN6
[7:0]
target
Register 50h BLC IN6 target
REGISTER
BIT
LABEL
DEFAULT
7
FRAME_SEQ
0
DESCRIPTION
REFER TO
ADDRESS
R81 (51h)
control frame sequence mode
0 = line by line
BLC control 1
1 = frame sequence mode
6
FA_EVERYLINE
0
control fine adjustment
0 = Fine adjust only used on the 1st line of a frame
1 = Fine adjust used on every line of a frame
5
FA_ACCUM
0
makes the fine adjust calibration accumulate a result over
multiple lines
0 = not accumulate
1 = accumulate
4
FA_EN
0
enables the fine adjust operation
0 = disable
1 = enable
3
CA_EVERYLINE
0
control coarse ajustment
0 = Coarse adjust only used on the 1st line of a frame
1 = Coarse adjust used on every line of a frame
2:0
CADUR[2:0]
000
controls the number of coarse adjust iterations to be
perfomed
000 = disable
001 = 1time
010 = 2time
011 = 3time
…
111 = 7time
Register 51h BLC control 1
84
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
1
SEQ_START
0
register flag to indicate that the next start-of-line indicator is
the first line of the first frame in a frame-sequence. This
register is automatically set to zero at the end of the BLC
operation on the first line
REFER TO
ADDRESS
R82 (52h)
BLC control 2
0 = no effect
1 = first frame of frame-sequence mode
0
FRAME_START
0
Register flag to indicate that the next start-of-line indicator is
the first line in a frame. This register is automatically set to
zero at the end of the BLC operation on the first line
0 = no effect
1 = start of line
Register 52h BLC control 2
REGISTER
BIT
LABEL
7:0
BPIX_AVAIL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R83 (53h)
BLC control 3
[7:0]
0000_0000 LSBs of the number of black-pixels available over which to
perform the coarse and/or fine adjust calibration
00_0000_0000 = no pixel available
11_1111_1111 = 1023 pixels
Register 53h BLC control 3
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
1:0
BPIX_AVAIL
00
MSBs of the number of black-pixels available over which to
perform the coarse and/or fine adjust calibration
REFER TO
ADDRESS
R84 (54h)
BLC control 4
[9:8]
00_0000_0000 = no pixel available
11_1111_1111 = 1023 pixels
Register 54h BLC control 4
REGISTER
BIT
LABEL
7:0
LINE_DEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R85 (55h)
BLC control 5
[7:0]
0000_0000 LSBs of the number of lines from the start of a frame to
delay the start of BLC operation
0_0000_0000 = no delay
1_1111_1111 = 511 line
Register 55h BLC control 5
REGISTER
BIT
LABEL
DEFAULT
0
LINE_DEL
0
DESCRIPTION
REFER TO
ADDRESS
R86 (56h)
BLC control 6
MSBs of the number of lines from the start of aframe to
delay the start of BLC operation
0_0000_0000 = no delay
1_1111_1111 = 511 line
Register 56h BLC control 6
REGISTER
BIT
LABEL
DEFAULT
7:4
AGCAVE[3:0]
0000
DESCRIPTION
REFER TO
ADDRESS
R87 (57h)
Rev 4.7
averaging factor before peak detection
85
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0000 = no average
AGC config 1
0001 = 2
0010 = 4
0011 = 8
…
1010 = 1024
1011 = reserved
1100 = reserved
1101 = reserved
1110 = reserved
1111 = reserved
2
AGC_ERRFLAG
0
AGC error flag
0 = no error detected
1 = AGC finish with error
1
AGC_ENDFLAG
0
AGC end flag
0 = not end or not run
1 = AGC sequence was done
0
AGC_EN
0
AGC enable
0 = disable
1 = enable
Register 57h AGC config 1
REGISTER
BIT
LABEL
DEFAULT
6:4
AGC_DPD[2:0]
000
DESCRIPTION
REFER TO
ADDRESS
R88 (58h)
AGC config 2
the number of peak detection iterations to calculate digital
gain
000 = no digital gain adjustment
001 = 1line
010 = 2line
…
111 = 7line
2:0
AGC_APD[2:0]
000
the number of peak detection iterations to calculate
analogue gain
000 = no analogue gain adjustment
001 = 1line
010 = 2line
…
111 = 7line
Register 58h AGC config 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
AGC_
0000_0000 LSBs of AGC target level for IN1
REFER TO
ADDRESS
R91 (5Bh)
7:0
AGC target
TARGETIN1
IN1 LSB
[7:0]
Register 5Bh AGC target IN1 LSB
REGISTER
BIT
LABEL
DEFAULT
1:0
AGC_
00
DESCRIPTION
REFER TO
ADDRESS
R92 (5Ch)
86
LSBs of AGC target level for IN1
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
LABEL
DEFAULT
DESCRIPTION
REFER TO
AGC_
0000_0000 LSBs of AGC target level for IN2
ADDRESS
AGC target
TARGETIN1
IN1 MSB
[9:8]
Register 5Ch AGC target IN1 MSB
REGISTER
BIT
ADDRESS
R93 (5Dh)
7:0
AGC target
TARGETIN2
IN2 LSB
[7:0]
Register 5Dh AGC target IN2 LSB
REGISTER
BIT
LABEL
DEFAULT
1:0
AGC_
00
DESCRIPTION
REFER TO
ADDRESS
R94 (5Eh)
AGC target
TARGETIN2
IN2 MSB
[9:8]
MSBs of AGC target level for IN2
Register 5Eh AGC target IN2 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
AGC_
0000_0000 LSBs of AGC target level for IN3
REFER TO
ADDRESS
R97 (61h)
7:0
AGC target
TARGETIN3
IN3 LSB
[7:0]
Register 61h AGC target IN3 LSB
REGISTER
BIT
LABEL
DEFAULT
AGC_
00
DESCRIPTION
REFER TO
ADDRESS
R98 (62h)
1:0
AGC target
TARGETIN3
IN3 MSB
[9:8]
MSBs of AGC target level for IN3
Register 62h AGC target IN3 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
AGC_
0000_0000 LSBs of AGC target level for IN4
REFER TO
ADDRESS
R99 (63h)
7:0
AGC target
TARGETIN4
IN4 LSB
[7:0]
Register 63h AGC target IN4 LSB
REGISTER
BIT
LABEL
DEFAULT
AGC_
00
DESCRIPTION
REFER TO
ADDRESS
R100 (64h)
1:0
AGC target
TARGETIN4
IN4 MSB
[9:8]
MSBs of AGC target level for IN4
Register 64h AGC target IN4 MSB
Rev 4.7
87
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
AGC_
0000_0000 LSBs of AGC target level for IN5
REFER TO
ADDRESS
R103 (67h)
7:0
AGC target
TARGETIN5
IN5 LSB
[7:0]
Register 67h AGC target IN5 LSB
REGISTER
BIT
LABEL
DEFAULT
AGC_
00
DESCRIPTION
REFER TO
ADDRESS
R104 (68h)
1:0
AGC target
TARGETIN5
IN5 MSB
[9:8]
MSBs of AGC target level for IN5
Register 68h AGC target IN5 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
AGC_
0000_0000 LSBs of AGC target level for IN6
REFER TO
ADDRESS
R105 (69h)
AGC target
TARGETIN6
IN6 LSB
[7:0]
Register 69h AGC target IN6 LSB
REGISTER
BIT
LABEL
DEFAULT
AGC_
00
DESCRIPTION
REFER TO
ADDRESS
R106 (6Ah)
1:0
AGC target
TARGETIN6
IN6 MSB
[9:8]
MSBs of AGC target level for IN6
Register 6Ah AGC target IN6 MSB
REGISTER
BIT
LABEL
7:0
PEAK_IN1
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R109 (6Dh)
AGC
0000_0000 LSBs of detected peak level of IN1 (Read Only)
[7:0]
peak level
IN1 LSB
Register 6Dh AGC peak level IN1 LSB
REGISTER
BIT
LABEL
DEFAULT
1:0
PEAK_IN1
00
DESCRIPTION
REFER TO
ADDRESS
R110 (6Eh)
AGC
MSBs of detected peak level of IN1 (Read Only)
[9:8]
peak level
IN1 MSB
Register 6Eh AGC peak level IN1 MSB
REGISTER
BIT
LABEL
7:0
PEAK_IN2
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R111 (6Fh)
88
0000_0000 LSBs of detected peak level of IN2 (Read Only)
Rev 4.7
WM8233
REGISTER
BIT
ADDRESS
AGC
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
[7:0]
peak level
IN2 LSB
Register 6Fh AGC peak level IN2 LSB
REGISTER
BIT
LABEL
DEFAULT
1:0
PEAK_IN2
00
ADDRESS
R112 (70h)
AGC
MSBs of detected peak level of IN2 (Read Only)
[9:8]
peak level
IN2 MSB
Register 70h AGC peak level IN2 MSB
REGISTER
BIT
LABEL
7:0
PEAK_IN3
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R115 (73h)
AGC
0000_0000 LSBs of detected peak level of IN3 (Read Only)
[7:0]
peak level
IN3 LSB
Register 73h AGC peak level IN3 LSB
REGISTER
BIT
LABEL
DEFAULT
1:0
PEAK_IN3
00
DESCRIPTION
REFER TO
ADDRESS
R116 (74h)
AGC
MSBs of detected peak level of IN3 (Read Only)
[9:8]
peak level
IN3 MSB
Register 74h AGC peak level IN3 MSB
REGISTER
BIT
LABEL
7:0
PEAK_IN4
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R117 (75h)
AGC
0000_0000 LSBs of detected peak level of IN4 (Read Only)
[7:0]
peak level
IN4 LSB
Register 75h AGC peak level IN4 LSB
REGISTER
BIT
LABEL
DEFAULT
1:0
PEAK_IN4
00
DESCRIPTION
REFER TO
ADDRESS
R118 (76h)
AGC
MSBs of detected peak level of IN4 (Read Only)
[9:8]
peak level
IN4 MSB
Register 76h AGC peak level IN4 MSB
Rev 4.7
89
WM8233
REGISTER
BIT
LABEL
7:0
PEAK_IN5
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R121 (79h)
AGC
0000_0000 LSBs of detected peak level of IN5 (Read Only)
[7:0]
peak level
IN5 LSB
Register 79h AGC peak level IN5 LSB
REGISTER
BIT
LABEL
DEFAULT
1:0
PEAK_IN5
00
DESCRIPTION
REFER TO
ADDRESS
R122 (7Ah)
AGC
MSBs of detected peak level of IN5 (Read Only)
[9:8]
peak level
IN5 MSB
Register 7Ah AGC peak level IN5 MSB
REGISTER
BIT
LABEL
7:0
PEAK_IN6
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R123 (7Bh)
AGC
0000_0000 LSBs of detected peak level of IN6 (Read Only)
[7:0]
peak level
IN6 LSB
Register 7Bh AGC peak level IN6 LSB
REGISTER
BIT
LABEL
DEFAULT
1:0
PEAK_IN6
00
DESCRIPTION
REFER TO
ADDRESS
R124 (7Ch)
AGC
MSBs of detected peak level of IN6 (Read Only)
[9:8]
peak level
IN6 MSB
Register 7Ch AGC peak level IN6 MSB
REGISTER
BIT
LABEL
DEFAULT
5:4
DLGAIN[1:0]
01
DESCRIPTION
REFER TO
ADDRESS
R128 (80h)
gain control of DLL delay line
Need to set according to input frequency. See details in
“PLL DLL Setup”
DLL config 1
2
DLLRST
0
reset DLL delay line
0 = normal
1= reset DLL
1
CKOSTB
0
standby TG clock output
0 = generate TG clock
1 = stop generation of TG clock
0
AFECKSTB
0
standby AFE clock (VSMP/RSMP/ADCK) output
0 = generate AFE clock
1 = stop generation of AFE clock
Register 80h DLL config 1
90
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
5:4
LVDLGAIN[1:0]
00
DESCRIPTION
REFER TO
ADDRESS
R129 (81h)
gain control of LVDS DLL delay line
Need to set according to input frequency. See details in
“PLL DLL Setup”
DLL config 2
1
LVDLLRST
0
reset LVDS DLL delay line
0 = normal
1 = reset LVDS DLL
0
LVDLLSTB
0
standby LVDS serializer clock generation
0 = generate LVDS serializer clock
1 = stop generation of LVDS serializer clock
Register 81h DLL config 2
REGISTER
BIT
LABEL
DEFAULT
5:0
RSMP_RISE
01_1100
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
R130 (82h)
RSMP rise
RSMP rise edge
00_0000 = tap0
[5:0]
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 82h RSMP rise
REGISTER
BIT
LABEL
DEFAULT
5:0
RSMP_FALL
10_0110
ADDRESS
R131 (83h)
RSMP fall
RSMP fall edge
00_0000 = tap0
[5:0]
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 83h RSMP fall
REGISTER
BIT
LABEL
DEFAULT
5:0
VSMP_RISE
11_0111
ADDRESS
R132 (84h)
VSMP rise
[5:0]
VSMP rise edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 84h VSMP rise
Rev 4.7
91
WM8233
REGISTER
BIT
LABEL
DEFAULT
5:0
VSMP_FALL
00_1000
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
R133 (85h)
VSMP fall
VSMP fall edge
00_0000 = tap0
[5:0]
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 85h VSMP fall
REGISTER
BIT
LABEL
DEFAULT
5:0
TCLKO_RISE
11_0111
ADDRESS
R134 (86h)
TGCKO rise
TCLKO rise edge
00_0000 = tap0
[5:0]
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 86h TGCKO rise
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK1_RISE[5:0]
00_1010
ADDRESS
R135 (87h)
CLK1 rise edge
00_0000 = tap0
CLK1 rise
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 87h CLK1 rise
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK1_FALL[5:0]
01_1001
ADDRESS
R136 (88h)
CLK1 fall
CLK1 fall edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
92
Rev 4.7
WM8233
Register 88h CLK1 fall
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK2_RISE[5:0]
01_1001
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
R137 (89h)
CLK2 rise edge
00_0000 = tap0
CLK2 rise
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 89h CLK2 rise
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK2_FALL[5:0]
10_1000
ADDRESS
R138 (8Ah)
CLK2 fall edge
00_0000 = tap0
CLK2fall
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 8Ah CLK2fall
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK3_RISE[5:0]
10_1000
ADDRESS
R139 (8Bh)
CLK3 rise edge
00_0000 = tap0
CLK3 rise
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 8Bh CLK3 rise
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK3_FALL[5:0]
00_1010
ADDRESS
R140 (8Ch)
CLK3 fall
CLK3 fall edge
00_0000 = tap0
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
Rev 4.7
93
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
11_1110 = reserved
11_1111 = reserved
Register 8Ch CLK3 fall
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK4_RISE[5:0]
00_0000
ADDRESS
R141 (8Dh)
CLK4 rise edge
00_0000 = tap0
CLK4 rise
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 8Dh CLK4 rise
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK4_FALL[5:0]
00_0000
ADDRESS
R142 (8Eh)
CLK4 fall edge
00_0000 = tap0
CLK4 fall
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 8Eh CLK4 fall
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK5_RISE[5:0]
00_1010
ADDRESS
R143 (8Fh)
CLK5 rise edge
00_0000 = tap0
CLK5 rise
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 8Fh CLK5 rise
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK5_FALL[5:0]
10_1000
ADDRESS
R144 (90h)
CLK5 fall
CLK5 fall edge
00_0000 = tap0
00_0001 = tap1
94
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 90h CLK5 fall
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK6_RISE[5:0]
00_1010
ADDRESS
R145 (91h)
CLK6 rise edge
00_0000 = tap0
CLK6 rise
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 91h CLK6 rise
REGISTER
BIT
LABEL
DEFAULT
5:0
CLK6_FALL[5:0]
10_1000
ADDRESS
R146 (92h)
CLK6 fall edge
00_0000 = tap0
CLK6 fall
00_0001 = tap1
…
11_1011 = tap59
11_1100 = reserved
11_1101 = reserved
11_1110 = reserved
11_1111 = reserved
Register 92h CLK6 fall
REGISTER
BIT
LABEL
DEFAULT
R160 (A0h)
7:4
OFFSET[3:0]
0000
TG config 1
3
CYCMD
0
ADDRESS
pixel counter offset (valid only in slave mode)
cycle mode enable
0 = normal (same operation at everyline)
1 = cycle mode
2
POLSYNC
0
polarity of tgync signal
0 = reset pixel counter at positive edge of tgsync
1 = reset pixel counter at negative edge of tgsync
1
TGMD
0
TG operation mode
0 = slave
1 = master
0
TG_EN
0
TG enable
0 = disable
1 = enable
Rev 4.7
95
WM8233
Register A0h TG config 1
REGISTER
BIT
LABEL
7:0
LLENGTH[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R161 (A1h)
TG config 2
0000_0000 LSBs of LLENGTH[14:0]
the number of pixels in a line (valid only in master mode)
Register A1h TG config 2
REGISTER
BIT
LABEL
DEFAULT
6:0
LLENGTH[14:8]
000_0000
DESCRIPTION
REFER TO
ADDRESS
R162 (A2h)
MSBs of LLENGTH
the number of pixels in a line (valid only in master mode)
TG config 3
Register A2h TG config 3
REGISTER
BIT
LABEL
7:0
FLAGPIX[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R163 (A3h)
TG config 4
0000_0000 LSBs of FLAGPIX[14:0]
flag pixel control
pulse flagpix is high
when pixel counter equals to flagpix[14:0]
Register A3h TG config 4
REGISTER
BIT
LABEL
DEFAULT
6:0
FLAGPIX[14:8]
000_0000
DESCRIPTION
REFER TO
ADDRESS
R164 (A4h)
MSBs of FLAGPIX[14:0]
flag pixel control
TG config 5
pulse flagpix is high
when pixel counter equals to flagpix[14:0]
Register A4h TG config 5
REGISTER
BIT
LABEL
DEFAULT
7
OE_CLK8
1
DESCRIPTION
REFER TO
ADDRESS
R165 (A5h)
output enable of "CLK8"
0 = Hi-Z
TG config 6
1 = output
6
OE_CLK7
1
output enable of "CLK7"
0 = Hi-Z
1 = output
5
OE_CLK6
1
output enable of "CLK6"
0 = Hi-Z
1 = output
4
OE_CLK5
1
output enable of "CLK5"
0 = Hi-Z
1 = output
3
OE_CLK4
1
output enable of "CLK4"
0 = Hi-Z
1 = output
2
OE_CLK3
1
output enable of "CLK3"
0 = Hi-Z
96
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
1
OE_CLK2
1
DESCRIPTION
REFER TO
ADDRESS
1 = output
output enable of "CLK2"
0 = Hi-Z
1 = output
0
OE_CLK1
1
output enable of "CLK1"
0 = Hi-Z
1 = output
Register A5h TG config 6
REGISTER
BIT
LABEL
DEFAULT
2
OE_CLK11
1
DESCRIPTION
REFER TO
ADDRESS
R166 (A6h)
output enable of "CLK11"
0 = Hi-Z
TG config 7
1 = output
1
OE_CLK10
1
output enable of "CLK10"
0 = Hi-Z
1 = output
0
OE_CLK9
1
output enable of "CLK9"
0 = Hi-Z
1 = output
Register A6h TG config 7
REGISTER
BIT
LABEL
DEFAULT
7
INV_CLK8
0
DESCRIPTION
REFER TO
ADDRESS
R167 (A7h)
invert signal output assigned to CLK8
0 = non-inverted
TG config 8
1 = inverted
6
INV_CLK7
0
invert signal output assigned to CLK7
0 = non-inverted
1 = inverted
5
INV_CLK6
0
invert signal output assigned to CLK6
0 = non-inverted
1 = inverted
4
INV_CLK5
0
invert signal output assigned to CLK5
0 = non-inverted
1 = inverted
3
INV_CLK4
0
invert signal output assigned to CLK4
0 = non-inverted
1 = inverted
2
INV_CLK3
0
invert signal output assigned to CLK3
0 = non-inverted
1 = inverted
1
INV_CLK2
0
invert signal output assigned to CLK2
0 = non-inverted
1 = inverted
0
INV_CLK1
0
invert signal output assigned to CLK1
0 = non-inverted
1 = inverted
Register A7h TG config 8
Rev 4.7
97
WM8233
REGISTER
BIT
LABEL
DEFAULT
2
INV_CLK11
0
DESCRIPTION
REFER TO
ADDRESS
R168 (A8h)
invert signal output assigned to CLK11
0 = non-inverted
TG config 9
1 = inverted
1
INV_CLK10
0
invert signal output assigned to CLK10
0 = non-inverted
1 = inverted
0
INV_CLK9
0
invert signal output assigned to CLK9
0 = non-inverted
1 = inverted
Register A8h TG config 9
REGISTER
BIT
LABEL
DEFAULT
7
EN_CLK8
0
DESCRIPTION
REFER TO
ADDRESS
R169 (A9h)
enable signal output CLK8
0 = disable
TG config 10
1 = enable
6
EN_CLK7
0
enable signal output CLK7
0 = disable
1 = enable
5
EN_CLK6
0
enable signal output CLK6
0 = disable
1 = enable
4
EN_CLK5
0
enable signal output CLK5
0 = disable
1 = enable
3
EN_CLK4
0
enable signal output CLK4
0 = disable
1 = enable
2
EN_CLK3
0
enable signal output CLK3
0 = disable
1 = enable
1
EN_CLK2
0
enable signal output CLK2
0 = disable
1 = enable
0
EN_CLK1
0
enable signal output CLK1
0 = disable
1 = enable
Register A9h TG config 10
REGISTER
BIT
LABEL
DEFAULT
2
EN_CLK11
0
DESCRIPTION
REFER TO
ADDRESS
R170 (AAh)
enable signal output CLK11
0 = disable
TG config 11
1 = enable
1
EN_CLK10
0
enable signal output CLK10
0 = disable
1 = enable
0
EN_CLK9
0
enable signal output CLK9
0 = disable
98
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
1 = enable
Register AAh TG config 11
REGISTER
BIT
LABEL
DEFAULT
7
SEL_CLK3
0
ADDRESS
R171 (ABh)
select signal for CLK3
0 = output clock
TG config 12
1 = output pulse (select by SEL_PCK3[2:0])
6:4
SEL_PCK3[2:0]
000
select pulse assigned to CLK3 (valid only when
SEL_CK3=1)
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
3
SEL_CLK2
0
select signal for CLK2
0 = output clock
1 = output pulse (select by SEL_PCK2[2:0])
2:0
SEL_PCK2[2:0]
000
select pulse assigned to CLK2 (valid only when
SEL_CK2=1)
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
Register ABh TG config 12
REGISTER
BIT
LABEL
DEFAULT
7
SEL_CLK5
0
DESCRIPTION
REFER TO
ADDRESS
R172 (ACh)
select signal for CLK5
0 = output clock
TG config 13
1 = output pulse (select by SEL_PCK5[2:0])
6:4
SEL_PCK5[2:0]
000
select pulse assigned to CLK5 (valid only when
SEL_CLK5=1)
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
3
SEL_CLK4
0
select signal for CLK4
0 = output clock
1 = output pulse (select by SEL_PCK4[2:0])
Rev 4.7
99
WM8233
REGISTER
BIT
LABEL
DEFAULT
2:0
SEL_PCK4[2:0]
000
DESCRIPTION
REFER TO
ADDRESS
select pulse assigned to CLK4 (valid only when
SEL_CLK4=1)
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
Register ACh TG config 13
REGISTER
BIT
LABEL
DEFAULT
6:4
SEL_PCK7[2:0]
000
DESCRIPTION
REFER TO
ADDRESS
R173 (ADh)
select pulse assigned to CLK7
000 = PO0
TG config 14
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
3
SEL_CLK6
0
select signal for CLK6
0 = output clock
1 = output pulse (select by SEL_PCK6[2:0])
2:0
SEL_PCK6[2:0]
000
select pulse assigned to CLK6 (valid only when
SEL_CLK6=1)
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
Register ADh TG config 14
REGISTER
BIT
LABEL
DEFAULT
6:4
SEL_PCK9[2:0]
000
DESCRIPTION
REFER TO
ADDRESS
R174 (AEh)
select pulse assigned to CLK9
000 = PO0
TG config 15
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
2:0
SEL_PCK8[2:0]
000
select pulse assigned to CLK8
000 = PO0
100
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
Register AEh TG config 15
REGISTER
BIT
LABEL
DEFAULT
6:4
SEL_PCK11[2:0
]
000
ADDRESS
R175 (AFh)
TG config 16
select pulse assigned to CLK11
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
2:0
SEL_PCK10[2:0
]
000
select pulse assigned to CLK10
000 = PO0
001 = PO1
010 = PO2
011 = PO3
100 = PO4
101 = PO5
110 = PO6
111 = PO7
Register AFh TG config 16
REGISTER
BIT
LABEL
DEFAULT
7:6
DEL_PCK5[1:0]
00
DESCRIPTION
REFER TO
ADDRESS
R176 (B0h)
control delay of pulse output assigned to CLK5
00 = 0nsec
TG config 17
01 = 1nsec
10 = 2nsec
11 = 3nsec
5:4
DEL_PCK4[1:0]
00
control delay of pulse output assigned to CLK4
00 = 0nsec
01 = 1nsec
10 = 2nsec
11 = 3nsec
3:2
DEL_PCK3[1:0]
00
control delay of pulse output assigned to CLK3
00 = 0nsec
01 = 1nsec
10 = 2nsec
11 = 3nsec
1:0
DEL_PCK2[1:0]
00
control delay of pulse output assigned to CLK2
00 = 0nsec
Rev 4.7
101
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
01 = 1nsec
10 = 2nsec
11 = 3nsec
Register B0h TG config 17
REGISTER
BIT
LABEL
DEFAULT
7:6
DEL_PCK9[1:0]
00
ADDRESS
R177 (B1h)
control delay of pulse output assigned to CLK9
00 = 0nsec
TG config 18
01 = 1nsec
10 = 2nsec
11 = 3nsec
5:4
DEL_PCK8[1:0]
00
control delay of pulse output assigned to CLK8
00 = 0nsec
01 = 1nsec
10 = 2nsec
11 = 3nsec
3:2
DEL_PCK7[1:0]
00
control delay of pulse output assigned to CLK7
00 = 0nsec
01 = 1nsec
10 = 2nsec
11 = 3nsec
1:0
DEL_PCK6[1:0]
00
control delay of pulse output assigned to CLK6
00 = 0nsec
01 = 1nsec
10 = 2nsec
11 = 3nsec
Register B1h TG config 18
REGISTER
BIT
LABEL
DEFAULT
3:2
DEL_PCK11
00
DESCRIPTION
REFER TO
ADDRESS
R178 (B2h)
TG config 19
control delay of pulse output assigned to CLK11
00 = 0nsec
[1:0]
01 = 1nsec
10 = 2nsec
11 = 3nsec
1:0
DEL_PCK10[
00
control delay of pulse output assigned to CLK10
00 = 0nsec
1:0]
01 = 1nsec
10 = 2nsec
11 = 3nsec
Register B2h TG config 19
REGISTER
BIT
LABEL
DEFAULT
4
INV_M3
0
DESCRIPTION
REFER TO
ADDRESS
R179 (B3h)
invert mask pulse "M3"
0 = non-inverted
TG config 20
1 = inverted
3
102
INV_M2
0
invert mask pulse "M2"
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0 = non-inverted
1 = inverted
2
INV_M1
0
invert mask pulse "M1"
0 = non-inverted
1 = inverted
1
INV_T2
0
invert toggle pulse "T2"
0 = non-inverted
1 = inverted
0
INV_T1
0
invert toggle pulse "T1"
0 = non-inverted
1 = inverted
Register B3h TG config 20
REGISTER
BIT
LABEL
DEFAULT
3:0
SEL_FLAG[3:0]
0000
DESCRIPTION
REFER TO
ADDRESS
R180 (B4h)
select signal to be output as datatrig
0xxx = flagpix
TG config 21
1000 = PO0
1001 = PO1
1010 = PO2
1011 = PO3
1100 = PO4
1101 = PO5
1110 = PO6
1111 = PO7
Register B4h TG config 21
REGISTER
BIT
LABEL
DEFAULT
6:4
CYCPAT_PO1
000
DESCRIPTION
REFER TO
ADDRESS
R181 (B5h)
TG config 22
PO1 cycle mode control
[0] = pulse enable at cycle-1
[2:0]
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
2:0
CYCPAT_PO0
000
PO0 cycle mode control
[0] = pulse enable at cycle-1
[2:0]
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
Register B5h TG config 22
REGISTER
BIT
LABEL
DEFAULT
6:4
CYCPAT_PO3
000
DESCRIPTION
REFER TO
ADDRESS
R182 (B6h)
TG config 23
PO3 cycle mode control
[0] = pulse enable at cycle-1
[2:0]
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
2:0
CYCPAT_PO2
[2:0]
000
PO2 cycle mode control
[0] = pulse enable at cycle-1
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
Rev 4.7
103
WM8233
Register B6h TG config 23
REGISTER
BIT
LABEL
DEFAULT
6:4
CYCPAT_PO5
000
DESCRIPTION
REFER TO
ADDRESS
R183 (B7h)
TG config 24
PO5 cycle mode control
[0] = pulse enable at cycle-1
[2:0]
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
2:0
CYCPAT_PO4
000
PO4 cycle mode control
[0] = pulse enable at cycle-1
[2:0]
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
Register B7h TG config 24
REGISTER
BIT
LABEL
DEFAULT
6:4
CYCPAT_PO7
000
DESCRIPTION
REFER TO
ADDRESS
R184 (B8h)
TG config 25
PO7 cycle mode control
[0] = pulse enable at cycle-1
[2:0]
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
2:0
CYCPAT_PO6
000
PO6 cycle mode control
[0] = pulse enable at cycle-1
[2:0]
[1] = pulse enable at cycle-2
[2] = pulse enable at cycle-3
Register B8h TG config 25
REGISTER
BIT
LABEL
7:0
CLAMP_RISE
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R185 (B9h)
clamp
enable
[7:0]
0000_0000 LSBs of CLAMP_RISE
clamp enable pulse rise pixel
rise LSB
Register B9h clamp enable rise LSB
REGISTER
BIT
LABEL
DEFAULT
6:0
CLAMP_RISE
000_0000
DESCRIPTION
REFER TO
ADDRESS
R186 (BAh)
clamp enable
MSBs of CLAMP_RISE
clamp enable pulse rise pixel
[14:8]
rise MSB
Register BAh clamp enable rise MSB
REGISTER
BIT
LABEL
7:0
CLAMP_FALL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R187 (BBh)
clamp
enable
[7:0]
0000_0000 LSBs of CLAMP_FALL
clamp enable pulse fall pixel
fall LSB
Register BBh clamp enable fall LSB
104
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
6:0
CLAMP_FALL
000_0000
DESCRIPTION
REFER TO
ADDRESS
R188 (BCh)
clamp enable
MSBs of CLAMP_FALL
clamp enable pulse fall pixel
[14:8]
fall MSB
Register BCh clamp enable fall MSB
REGISTER
BIT
LABEL
7:0
OB_START
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R189 (BDh)
OB start LSB
[7:0]
0000_0000 LSBs of OB_START
optical black calibration start pixel count
Register BDh OB start LSB
REGISTER
BIT
LABEL
DEFAULT
6:0
OB_START
000_0000
DESCRIPTION
REFER TO
ADDRESS
R190 (BEh)
OB start MSB
MSBs of OB_START
optical black calibration start pixel count
[14:8]
Register BEh OB start MSB
REGISTER
BIT
LABEL
7:0
peak_det
PEAKDET_RIS
E
rise LSB
[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R191 (BFh)
0000_0000 LSBs of PEAKDET_RISE[14:0]
peak detection start pixel count
Register BFh peak_det rise LSB
REGISTER
BIT
LABEL
DEFAULT
6:0
PEAKDET_RIS
E
000_0000
peak_det
rise MSB
[14:8]
DESCRIPTION
REFER TO
ADDRESS
R192 (C0h)
MSBs of PEAKDET_RISE[14:0]
peak detection start pixel count
Register C0h peak_det rise MSB
REGISTER
BIT
LABEL
7:0
peak_det
PEAKDET_FAL
L
fall LSB
[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R193 (C1h)
0000_0000 LSBs of PEAKDET_FALL[14:0]
peak detection end pixel count
Register C1h peak_det fall LSB
REGISTER
BIT
LABEL
DEFAULT
6:0
PEAKDET_FAL
L
000_0000
peak_det
fall MSB
[14:8]
DESCRIPTION
REFER TO
ADDRESS
R194 (C2h)
MSBs of PEAKDET_FALL[14:0]
peak detection end pixel count
Register C2h peak_det fall MSB
Rev 4.7
105
WM8233
REGISTER
BIT
LABEL
7:0
M1_RISE[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R195 (C3h)
Mask pulse 1
0000_0000 LSBs of M1_RISE[14:0]
mask pulse "M1" rise pixel count
rise LSB
Register C3h Mask pulse 1 rise LSB
REGISTER
BIT
LABEL
DEFAULT
6:0
M1_RISE[14:8]
000_0000
DESCRIPTION
REFER TO
ADDRESS
R196 (C4h)
MSBs of M1_RISE[14:0]
mask pulse "M1" rise pixel count
Mask pulse 1
rise MSB
Register C4h Mask pulse 1 rise MSB
REGISTER
BIT
LABEL
7:0
M1_FALL[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R197 (C5h)
Mask pulse 1
0000_0000 LSBs of M1_FALL[14:0]
mask pulse "M1" fall pixel count
fall LSB
Register C5h Mask pulse 1 fall LSB
REGISTER
BIT
LABEL
DEFAULT
6:0
M1_FALL[14:8]
000_0000
DESCRIPTION
REFER TO
ADDRESS
R198 (C6h)
MSBs of M1_FALL[14:0]
mask pulse "M1" fall pixel count
Mask pulse 1
fall MSB
Register C6h Mask pulse 1 fall MSB
REGISTER
BIT
LABEL
7:0
M2_RISE[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R199 (C7h)
Mask pulse
2
0000_0000 LSBs of M2_RISE[14:0]
mask pulse "M2" rise pixel count
rise LSB
Register C7h Mask pulse 2 rise LSB
REGISTER
BIT
LABEL
DEFAULT
6:0
M2_RISE[14:8]
000_0000
DESCRIPTION
REFER TO
ADDRESS
R200 (C8h)
MSBs of M2_RISE[14:0]
mask pulse "M2" rise pixel count
Mask pulse
2
rise MSB
Register C8h Mask pulse 2 rise MSB
REGISTER
BIT
LABEL
7:0
M2_FALL[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R201 (C9h)
106
0000_0000 LSBs of M2_FALL[14:0]
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
mask pulse "M2" fall pixel count
Mask pulse
2
fall LSB
Register C9h Mask pulse 2 fall LSB
REGISTER
BIT
LABEL
DEFAULT
6:0
M2_FALL[14:8]
000_0000
DESCRIPTION
REFER TO
ADDRESS
R202 (CAh)
MSBs of M2_FALL[14:0]
mask pulse "M2" fall pixel count
Mask pulse
2
fall MSB
Register CAh Mask pulse 2 fall MSB
REGISTER
BIT
LABEL
7:0
M3_RISE[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R203 (CBh)
Mask pulse
3
0000_0000 LSBs of M3_RISE
mask pulse "M3" rise pixel count
rise LSB
Register CBh Mask pulse 3 rise LSB
REGISTER
BIT
LABEL
DEFAULT
6:0
M3_RISE[14:8]
000_0000
DESCRIPTION
REFER TO
ADDRESS
R204 (CCh)
MSBs of M3_RISE
mask pulse "M3" rise pixel count
Mask pulse 3
rise MSB
Register CCh Mask pulse 3 rise MSB
REGISTER
BIT
LABEL
7:0
M3_FALL[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R205 (CDh)
Mask pulse 3
0000_0000 LSBs of M3_FALL
mask pulse "M3" fall pixel count
fall LSB
Register CDh Mask pulse 3 fall LSB
REGISTER
BIT
LABEL
DEFAULT
6:0
M3_FALL[14:8]
000_0000
DESCRIPTION
REFER TO
ADDRESS
R206 (CEh)
MSBs of M3_FALL
mask pulse "M3" fall pixel count
Mask pulse 3
fall MSB
Register CEh Mask pulse 3 fall MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
TP0[7:0]
0000_0000 pixel count of toggle point "TP0"
REFER TO
ADDRESS
R207 (CFh)
Toggle point
Rev 4.7
107
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
0 LSB
Register CFh Toggle point 0 LSB
REGISTER
BIT
LABEL
DEFAULT
7
GEN_TP0
0
ADDRESS
R208 (D0h)
global enable of toggle point
0 = disable all toggle point
Toggle point
0 MSB
1 = enable toggle point "TP0"
6:0
TP0[14:8]
000_0000
pixel count of toggle point "TP0
Register D0h Toggle point 0 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
TP1[7:0]
0000_0000 pixel count of toggle point "TP1"
REFER TO
ADDRESS
R209 (D1h)
Toggle point
1 LSB
Register D1h Toggle point 1 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP1
0
DESCRIPTION
REFER TO
ADDRESS
R210 (D2h)
enable toggle point "TP1"
0 = disable "TP1" and all subsequent toggle point
Toggle point
1 MSB
1 = enable toggle point "TP1"
6:0
TP1[14:8]
000_0000
pixel count of toggle point "TP1"
Register D2h Toggle point 1 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
TP2[7:0]
0000_0000 pixel count of toggle point "TP2"
REFER TO
ADDRESS
R211 (D3h)
Toggle point
2 LSB
Register D3h Toggle point 2 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP2
0
DESCRIPTION
REFER TO
ADDRESS
R212 (D4h)
enable toggle point "TP2"
0 = disable "TP2" and all subsequent toggle point
Toggle point
2 MSB
1 = enable toggle point "TP2"
6:0
TP2[14:8]
000_0000
pixel count of toggle point "TP2"
Register D4h Toggle point 2 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
TP3[7:0]
0000_0000 pixel count of toggle point "TP3"
REFER TO
ADDRESS
R213 (D5h)
Toggle point
3 LSB
108
Rev 4.7
WM8233
Register D5h Toggle point 3 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP3
0
DESCRIPTION
REFER TO
ADDRESS
R214 (D6h)
enable toggle point "TP3"
0 = disable "TP3" and all subsequent toggle point
Toggle point
3 MSB
1 = enable toggle point "TP3"
6:0
TP3[14:8]
000_0000
pixel count of toggle point "TP3"
Register D6h Toggle point 3 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
TP4[7:0]
0000_0000 pixel count of toggle point "TP4"
REFER TO
ADDRESS
R215 (D7h)
Toggle point
4 LSB
Register D7h Toggle point 4 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP4
0
DESCRIPTION
REFER TO
ADDRESS
R216 (D8h)
enable toggle point "TP4"
0 = disable "TP4" and all subsequent toggle point
Toggle point
4 MSB
1 = enable toggle point "TP4"
6:0
TP4[14:8]
000_0000
pixel count of toggle point "TP4"
Register D8h Toggle point 4 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
TP5[7:0]
0000_0000 pixel count of toggle point "TP5"
REFER TO
ADDRESS
R217 (D9h)
Toggle point
5 LSB
Register D9h Toggle point 5 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP5
0
DESCRIPTION
REFER TO
ADDRESS
R218 (DAh)
enable toggle point "TP5"
0 = disable "TP5" and all subsequent toggle point
Toggle point
5 MSB
1 = enable toggle point "TP5"
6:0
TP5[14:8]
000_0000
pixel count of toggle point "TP5"
Register DAh Toggle point 5 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
TP6[7:0]
0000_0000 pixel count of toggle point "TP1"
REFER TO
ADDRESS
R219 (DBh)
Toggle point
6 LSB
Register DBh Toggle point 6 LSB
Rev 4.7
109
WM8233
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP6
0
DESCRIPTION
REFER TO
ADDRESS
R220 (DCh)
enable toggle point "TP6"
0 = disable "TP6" and all subsequent toggle point
Toggle point
6 MSB
1 = enable toggle point "TP6"
6:0
TP6[14:8]
000_0000
pixel count of toggle point "TP6"
Register DCh Toggle point 6 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
TP7[7:0]
0000_0000 pixel count of toggle point "TP7"
REFER TO
ADDRESS
R221 (DDh)
Toggle point
7 LSB
Register DDh Toggle point 7 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP7
0
DESCRIPTION
REFER TO
ADDRESS
R222 (DEh)
enable toggle point "TP7"
0 = disable "TP7" and all subsequent toggle point
Toggle point
7 MSB
1 = enable toggle point "TP7"
6:0
TP7[14:8]
000_0000
pixel count of toggle point "TP7"
Register DEh Toggle point 7 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
TP8[7:0]
0000_0000 pixel count of toggle point "TP8"
REFER TO
ADDRESS
R223 (DFh)
Toggle point
8 LSB
Register DFh Toggle point 8 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP8
0
DESCRIPTION
REFER TO
ADDRESS
R224 (E0h)
enable toggle point "TP8"
0 = disable "TP8" and all subsequent toggle point
Toggle point
8 MSB
1 = enable toggle point "TP8"
6:0
TP8[14:8]
000_0000
pixel count of toggle point "TP8"
Register E0h Toggle point 8 MSB
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
7:0
TP9[7:0]
0000_0000 pixel count of toggle point "TP9"
REFER TO
ADDRESS
R225 (E1h)
Toggle point
9 LSB
Register E1h Toggle point 9 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP9
0
DESCRIPTION
REFER TO
ADDRESS
R226 (E2h)
110
enable toggle point "TP9"
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0 = disable "TP9" and all subsequent toggle point
Toggle point
9 MSB
1 = enable toggle point "TP9"
6:0
TP9[14:8]
000_0000
pixel count of toggle point "TP9"
Register E2h Toggle point 9 MSB
REGISTER
BIT
LABEL
7:0
TP10[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R227 (E3h)
0000_0000 pixel count of toggle point "TP10"
Toggle point
10 LSB
Register E3h Toggle point 10 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP10
0
DESCRIPTION
REFER TO
ADDRESS
R228 (E4h)
enable toggle point "TP10"
0 = disable "TP10" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP10"
10 MSB
6:0
TP10[14:8]
000_0000
pixel count of toggle point "TP10"
Register E4h Toggle point 10 MSB
REGISTER
BIT
LABEL
7:0
TP11[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R229 (E5h)
0000_0000 pixel count of toggle point "TP11"
Toggle point
11 LSB
Register E5h Toggle point 11 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP11
0
DESCRIPTION
REFER TO
ADDRESS
R230 (E6h)
enable toggle point "TP11"
0 = disable "TP11" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP11"
11 MSB
6:0
TP11[14:8]
000_0000
pixel count of toggle point "TP11"
Register E6h Toggle point 11 MSB
REGISTER
BIT
LABEL
7:0
TP12[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R231 (E7h)
0000_0000 pixel count of toggle point "TP12"
Toggle point
12 LSB
Register E7h Toggle point 12 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP12
0
DESCRIPTION
REFER TO
ADDRESS
R232 (E8h)
Rev 4.7
enable toggle point "TP12"
111
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0 = disable "TP12" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP12"
12 MSB
6:0
TP12[14:8]
000_0000
pixel count of toggle point "TP12"
Register E8h Toggle point 12 MSB
REGISTER
BIT
LABEL
7:0
TP13[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R233 (E9h)
0000_0000 pixel count of toggle point "TP13"
Toggle point
13 LSB
Register E9h Toggle point 13 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP13
0
DESCRIPTION
REFER TO
ADDRESS
R234 (EAh)
enable toggle point "TP13"
0 = disable "TP13" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP13"
13 MSB
6:0
TP13[14:8]
000_0000
pixel count of toggle point "TP13"
Register EAh Toggle point 13 MSB
REGISTER
BIT
LABEL
7:0
TP14[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R235 (EBh)
0000_0000 pixel count of toggle point "TP14"
Toggle point
14 LSB
Register EBh Toggle point 14 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP14
0
DESCRIPTION
REFER TO
ADDRESS
R236 (ECh)
enable toggle point "TP14"
0 = disable "TP14" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP14"
14 MSB
6:0
TP14[14:8]
000_0000
pixel count of toggle point "TP14"
Register ECh Toggle point 14 MSB
REGISTER
BIT
LABEL
7:0
TP15[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R237 (EDh)
0000_0000 pixel count of toggle point "TP15"
Toggle point
15 LSB
Register EDh Toggle point 15 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP15
0
DESCRIPTION
REFER TO
ADDRESS
R238 (EEh)
112
enable toggle point "TP15"
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0 = disable "TP15" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP15"
15 MSB
6:0
TP15[14:8]
000_0000
pixel count of toggle point "TP15"
Register EEh Toggle point 15 MSB
REGISTER
BIT
LABEL
7:0
TP16[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R239 (EFh)
0000_0000 pixel count of toggle point "TP16"
Toggle point
16 LSB
Register EFh Toggle point 16 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP16
0
DESCRIPTION
REFER TO
ADDRESS
R240 (F0h)
enable toggle point "TP16"
0 = disable "TP16" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP16"
16 MSB
6:0
TP16[14:8]
000_0000
pixel count of toggle point "TP16"
Register F0h Toggle point 16 MSB
REGISTER
BIT
LABEL
7:0
TP17[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R241 (F1h)
0000_0000 pixel count of toggle point "TP17"
Toggle point
17 LSB
Register F1h Toggle point 17 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP17
0
DESCRIPTION
REFER TO
ADDRESS
R242 (F2h)
enable toggle point "TP17"
0 = disable "TP17" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP17"
17 MSB
6:0
TP17[14:8]
000_0000
pixel count of toggle point "TP17"
Register F2h Toggle point 17 MSB
REGISTER
BIT
LABEL
7:0
TP18[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R243 (F3h)
0000_0000 pixel count of toggle point "TP18"
Toggle point
18 LSB
Register F3h Toggle point 18 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP18
0
DESCRIPTION
REFER TO
ADDRESS
R244 (F4h)
Rev 4.7
enable toggle point "TP18"
113
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0 = disable "TP18" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP18"
18 MSB
6:0
TP18[14:8]
000_0000
pixel count of toggle point "TP18"
Register F4h Toggle point 18 MSB
REGISTER
BIT
LABEL
7:0
TP19[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R245 (F5h)
0000_0000 pixel count of toggle point "TP19"
Toggle point
19 LSB
Register F5h Toggle point 19 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP19
0
DESCRIPTION
REFER TO
ADDRESS
R246 (F6h)
enable toggle point "TP19"
0 = disable "TP19" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP19"
19 MSB
6:0
TP19[14:8]
000_0000
pixel count of toggle point "TP19"
Register F6h Toggle point 19 MSB
REGISTER
BIT
LABEL
7:0
TP20[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R247 (F7h)
0000_0000 pixel count of toggle point "TP20"
Toggle point
20 LSB
Register F7h Toggle point 20 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP20
0
DESCRIPTION
REFER TO
ADDRESS
R248 (F8h)
enable toggle point "TP20"
0 = disable "TP20" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP20"
20 MSB
6:0
TP20[14:8]
000_0000
pixel count of toggle point "TP20"
Register F8h Toggle point 20 MSB
REGISTER
BIT
LABEL
7:0
TP21[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R249 (F9h)
0000_0000 pixel count of toggle point "TP21"
Toggle point
21 LSB
Register F9h Toggle point 21 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP21
0
DESCRIPTION
REFER TO
ADDRESS
R250 (FAh)
114
enable toggle point "TP21"
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0 = disable "TP21" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP21"
21 MSB
6:0
TP21[14:8]
000_0000
pixel count of toggle point "TP21"
Register FAh Toggle point 21 MSB
REGISTER
BIT
LABEL
7:0
TP22[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R251 (FBh)
0000_0000 pixel count of toggle point "TP22"
Toggle point
22 LSB
Register FBh Toggle point 22 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP22
0
DESCRIPTION
REFER TO
ADDRESS
R252 (FCh)
enable toggle point "TP22"
0 = disable "TP22" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP22"
22 MSB
6:0
TP22[14:8]
000_0000
pixel count of toggle point "TP22"
Register FCh Toggle point 22 MSB
REGISTER
BIT
LABEL
7:0
TP23[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R253 (FDh)
0000_0000 pixel count of toggle point "TP23"
Toggle point
23 LSB
Register FDh Toggle point 23 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP23
0
DESCRIPTION
REFER TO
ADDRESS
R254 (FEh)
enable toggle point "TP23"
0 = disable "TP23" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP23"
23 MSB
6:0
TP23[14:8]
000_0000
pixel count of toggle point "TP23"
Register FEh Toggle point 23 MSB
REGISTER
BIT
LABEL
7:0
TP24[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R255 (FFh)
0000_0000 pixel count of toggle point "TP24"
Toggle point
24 LSB
Register FFh Toggle point 24 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP24
0
DESCRIPTION
REFER TO
ADDRESS
R256 (0100h)
Toggle point
24 MSB
Rev 4.7
enable toggle point "TP24"
0 = disable "TP24" and all subsequent toggle point
1 = enable toggle point "TP24"
115
WM8233
REGISTER
BIT
LABEL
DEFAULT
6:0
TP24[14:8]
000_0000
DESCRIPTION
REFER TO
ADDRESS
pixel count of toggle point "TP24"
Register 0100h Toggle point 24 MSB
REGISTER
BIT
LABEL
7:0
TP25[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R257 (0101h)
0000_0000 pixel count of toggle point "TP25"
Toggle point
25 LSB
Register 0101h Toggle point 25 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP25
0
DESCRIPTION
REFER TO
ADDRESS
R258 (0102h)
enable toggle point "TP25"
0 = disable "TP25" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP25"
25 MSB
6:0
TP25[14:8]
000_0000
pixel count of toggle point "TP25"
Register 0102h Toggle point 25 MSB
REGISTER
BIT
LABEL
7:0
TP26[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R259 (0103h)
0000_0000 pixel count of toggle point "TP26"
Toggle point
26 LSB
Register 0103h Toggle point 26 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP26
0
DESCRIPTION
REFER TO
ADDRESS
R260 (0104h)
enable toggle point "TP26"
0 = disable "TP26" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP26"
26 MSB
6:0
TP26[14:8]
000_0000
pixel count of toggle point "TP26"
Register 0104h Toggle point 26 MSB
REGISTER
BIT
LABEL
7:0
TP27[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R261 (0105h)
0000_0000 pixel count of toggle point "TP27"
Toggle point
27 LSB
Register 0105h Toggle point 27 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP27
0
DESCRIPTION
REFER TO
ADDRESS
R262 (0106h)
Toggle point
27 MSB
116
enable toggle point "TP27"
0 = disable "TP27" and all subsequent toggle point
1 = enable toggle point "TP27"
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
6:0
TP27[14:8]
000_0000
DESCRIPTION
REFER TO
ADDRESS
pixel count of toggle point "TP27"
Register 0106h Toggle point 27 MSB
REGISTER
BIT
LABEL
7:0
TP28[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R263 (0107h)
0000_0000 pixel count of toggle point "TP28"
Toggle point
28 LSB
Register 0107h Toggle point 28 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP28
0
DESCRIPTION
REFER TO
ADDRESS
R264 (0108h)
enable toggle point "TP28"
0 = disable "TP28" and all subsequent toggle point
Toggle point
1 = enable toggle point "TP28"
28 MSB
6:0
TP28[14:8]
000_0000
pixel count of toggle point "TP28"
Register 0108h Toggle point 28 MSB
REGISTER
BIT
LABEL
7:0
TP29[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R265 (0109h)
0000_0000 pixel count of toggle point "TP29"
Toggle point
29 LSB
Register 0109h Toggle point 29 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP29
0
DESCRIPTION
REFER TO
ADDRESS
R266
(010Ah)
0 = disable "TP29" and all subsequent toggle point
Toggle point
29 MSB
enable toggle point "TP29"
1 = enable toggle point "TP29"
6:0
TP29[14:8]
000_0000
pixel count of toggle point "TP29"
Register 010Ah Toggle point 29 MSB
REGISTER
BIT
LABEL
7:0
TP30[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R267
(010Bh)
0000_0000 pixel count of toggle point "TP30"
Toggle point
30 LSB
Register 010Bh Toggle point 30 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP30
0
DESCRIPTION
REFER TO
ADDRESS
R268
(010Ch)
Rev 4.7
enable toggle point "TP30"
0 = disable "TP30" and all subsequent toggle point
117
WM8233
REGISTER
BIT
LABEL
DEFAULT
6:0
TP30[14:8]
000_0000
DESCRIPTION
REFER TO
ADDRESS
1 = enable toggle point "TP30"
Toggle point
30 MSB
pixel count of toggle point "TP30"
Register 010Ch Toggle point 30 MSB
REGISTER
BIT
LABEL
7:0
TP31[7:0]
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R269
(010Dh)
0000_0000 pixel count of toggle point "TP31"
Toggle point
31 LSB
Register 010Dh Toggle point 31 LSB
REGISTER
BIT
LABEL
DEFAULT
7
EN_TP31
0
DESCRIPTION
REFER TO
ADDRESS
R270
(010Eh)
0 = disable "TP31"
Toggle point
31 MSB
enable toggle point "TP31"
1 = enable toggle point "TP31"
6:0
TP31[14:8]
000_0000
pixel count of toggle point "TP31"
Register 010Eh Toggle point 31 MSB
REGISTER
BIT
LABEL
DEFAULT
7
POL7_T1
1
DESCRIPTION
REFER TO
ADDRESS
R271
(010Fh)
Polarity
setting
logic level of T1 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7
6
POL6_T1
1
of T1 1
logic level of T1 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6
5
POL5_T1
1
logic level of T1 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5
4
POL4_T1
1
logic level of T1 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4
3
POL3_T1
1
logic level of T1 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3
2
POL2_T1
1
logic level of T1 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2
1
POL1_T1
1
logic level of T1 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1
0
POL0_T1
1
logic level of T1 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 010Fh Polarity setting of T1 1
118
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
7
POL15_T1
1
DESCRIPTION
REFER TO
ADDRESS
R272 (0110h)
of T1 2
logic level of T1 pulse at toggle point TP15
0 = low at TP15
Polarity
setting
1 = high at TP15
6
POL14_T1
1
logic level of T1 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14
5
POL13_T1
1
logic level of T1 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13
4
POL12_T1
1
logic level of T1 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12
3
POL11_T1
1
logic level of T1 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11
2
POL10_T1
1
logic level of T1 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10
1
POL9_T1
1
logic level of T1 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9
0
POL8_T1
1
logic level of T1 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0110h Polarity setting of T1 2
REGISTER
BIT
LABEL
DEFAULT
7
POL23_T1
1
DESCRIPTION
REFER TO
ADDRESS
R273 (0111h)
of T1 3
logic level of T1 pulse at toggle point TP23
0 = low at TP23
Polarity
setting
1 = high at TP23
6
POL22_T1
1
logic level of T1 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22
5
POL21_T1
1
logic level of T1 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21
4
POL20_T1
1
logic level of T1 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20
3
POL19_T1
1
logic level of T1 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19
2
POL18_T1
1
logic level of T1 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18
1
POL17_T1
1
logic level of T1 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17
0
POL16_T1
1
logic level of T1 pulse at toggle point TP16
0 = low at TP16
Rev 4.7
119
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP16
Register 0111h Polarity setting of T1 3
REGISTER
BIT
LABEL
DEFAULT
7
POL31_T1
1
ADDRESS
R274 (0112h)
of T1 4
logic level of T1 pulse at toggle point TP31
0 = low at TP31
Polarity
setting
1 = high at TP31
6
POL30_T1
1
logic level of T1 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30
5
POL29_T1
1
logic level of T1 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29
4
POL28_T1
1
logic level of T1 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28
3
POL27_T1
1
logic level of T1 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27
2
POL26_T1
1
logic level of T1 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26
1
POL25_T1
1
logic level of T1 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25
0
POL24_T1
1
logic level of T1 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0112h Polarity setting of T1 4
REGISTER
BIT
LABEL
DEFAULT
7
POL7_T2
1
DESCRIPTION
REFER TO
ADDRESS
R275 (0113h)
of T2 1
logic level of T2 pulse at toggle point TP7
0 = low at TP7
Polarity
setting
1 = high at TP7
6
POL6_T2
1
logic level of T2 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6
5
POL5_T2
1
logic level of T2 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5
4
POL4_T2
1
logic level of T2 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4
3
POL3_T2
1
logic level of T2 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3
2
POL2_T2
1
logic level of T2 pulse at toggle point TP2
0 = low at TP2
120
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
1
POL1_T2
1
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP2
logic level of T2 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1
0
POL0_T2
1
logic level of T2 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 0113h Polarity setting of T2 1
REGISTER
BIT
LABEL
DEFAULT
7
POL15_T2
1
DESCRIPTION
REFER TO
ADDRESS
R276 (0114h)
of T2 2
logic level of T2 pulse at toggle point TP15
0 = low at TP15
Polarity
setting
1 = high at TP15
6
POL14_T2
1
logic level of T2 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14
5
POL13_T2
1
logic level of T2 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13
4
POL12_T2
1
logic level of T2 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12
3
POL11_T2
1
logic level of T2 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11
2
POL10_T2
1
logic level of T2 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10
1
POL9_T2
1
logic level of T2 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9
0
POL8_T2
1
logic level of T2 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0114h Polarity setting of T2 2
REGISTER
BIT
LABEL
DEFAULT
7
POL23_T2
1
DESCRIPTION
REFER TO
ADDRESS
R277 (0115h)
of T2 3
logic level of T2 pulse at toggle point TP23
0 = low at TP23
Polarity
setting
1 = high at TP23
6
POL22_T2
1
logic level of T2 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22
5
POL21_T2
1
logic level of T2 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21
4
POL20_T2
1
logic level of T2 pulse at toggle point TP20
0 = low at TP20
Rev 4.7
121
WM8233
REGISTER
BIT
LABEL
DEFAULT
3
POL19_T2
1
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP20
logic level of T2 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19
2
POL18_T2
1
logic level of T2 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18
1
POL17_T2
1
logic level of T2 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17
0
POL16_T2
1
logic level of T2 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0115h Polarity setting of T2 3
REGISTER
BIT
LABEL
DEFAULT
7
POL31_T2
1
DESCRIPTION
REFER TO
ADDRESS
R278 (0116h)
of T2 4
logic level of T2 pulse at toggle point TP31
0 = low at TP31
Polarity
setting
1 = high at TP31
6
POL30_T2
1
logic level of T2 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30
5
POL29_T2
1
logic level of T2 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29
4
POL28_T2
1
logic level of T2 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28
3
POL27_T2
1
logic level of T2 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27
2
POL26_T2
1
logic level of T2 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26
1
POL25_T2
1
logic level of T2 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25
0
POL24_T2
1
logic level of T2 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0116h Polarity setting of T2 4
REGISTER
BIT
LABEL
DEFAULT
7
POL7_PO0
0
DESCRIPTION
REFER TO
ADDRESS
R279 (0117h)
of P0 1
logic level of PO0 pulse at toggle point TP7
0 = low at TP7
Polarity
setting
1 = high at TP7
6
POL6_PO0
0
logic level of PO0 pulse at toggle point TP6
0 = low at TP6
122
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
5
POL5_PO0
0
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP6
logic level of PO0 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5
4
POL4_PO0
0
logic level of PO0 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4
3
POL3_PO0
0
logic level of PO0 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3
2
POL2_PO0
0
logic level of PO0 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2
1
POL1_PO0
0
logic level of PO0 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1
0
POL0_PO0
0
logic level of PO0 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 0117h Polarity setting of P0 1
REGISTER
BIT
LABEL
DEFAULT
7
POL15_PO0
0
DESCRIPTION
REFER TO
ADDRESS
R280 (0118h)
of P0 2
logic level of PO0 pulse at toggle point TP15
0 = low at TP15
Polarity
setting
1 = high at TP15
6
POL14_PO0
0
logic level of PO0 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14
5
POL13_PO0
0
logic level of PO0 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13
4
POL12_PO0
0
logic level of PO0 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12
3
POL11_PO0
0
logic level of PO0 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11
2
POL10_PO0
0
logic level of PO0 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10
1
POL9_PO0
0
logic level of PO0 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9
0
POL8_PO0
0
logic level of PO0 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0118h Polarity setting of P0 2
Rev 4.7
123
WM8233
REGISTER
BIT
LABEL
DEFAULT
7
POL23_PO0
0
DESCRIPTION
REFER TO
ADDRESS
R281 (0119h)
of P0 3
logic level of PO0 pulse at toggle point TP23
0 = low at TP23
Polarity
setting
1 = high at TP23
6
POL22_PO0
0
logic level of PO0 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22
5
POL21_PO0
0
logic level of PO0 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21
4
POL20_PO0
0
logic level of PO0 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20
3
POL19_PO0
0
logic level of PO0 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19
2
POL18_PO0
0
logic level of PO0 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18
1
POL17_PO0
0
logic level of PO0 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17
0
POL16_PO0
0
logic level of PO0 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0119h Polarity setting of P0 3
REGISTER
BIT
LABEL
DEFAULT
7
POL31_PO0
0
DESCRIPTION
REFER TO
ADDRESS
R282
(011Ah)
Polarity
setting
logic level of PO0 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31
6
POL30_PO0
0
of P0 4
logic level of PO0 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30
5
POL29_PO0
0
logic level of PO0 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29
4
POL28_PO0
0
logic level of PO0 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28
3
POL27_PO0
0
logic level of PO0 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27
2
POL26_PO0
0
logic level of PO0 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26
1
POL25_PO0
0
logic level of PO0 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25
0
POL24_PO0
0
logic level of PO0 pulse at toggle point TP24
0 = low at TP24
124
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP24
Register 011Ah Polarity setting of P0 4
REGISTER
BIT
LABEL
DEFAULT
7
POL7_PO1
0
ADDRESS
R283
(011Bh)
Polarity
setting
logic level of PO1 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7
6
POL6_PO1
0
of P1 1
logic level of PO1 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6
5
POL5_PO1
0
logic level of PO1 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5
4
POL4_PO1
0
logic level of PO1 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4
3
POL3_PO1
0
logic level of PO1 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3
2
POL2_PO1
0
logic level of PO1 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2
1
POL1_PO1
0
logic level of PO1 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1
0
POL0_PO1
0
logic level of PO1 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 011Bh Polarity setting of P1 1
REGISTER
BIT
LABEL
DEFAULT
7
POL15_PO1
0
DESCRIPTION
REFER TO
ADDRESS
R284
(011Ch)
Polarity
setting
logic level of PO1 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15
6
POL14_PO1
0
of P1 2
logic level of PO1 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14
5
POL13_PO1
0
logic level of PO1 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13
4
POL12_PO1
0
logic level of PO1 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12
3
POL11_PO1
0
logic level of PO1 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11
2
POL10_PO1
0
logic level of PO1 pulse at toggle point TP10
0 = low at TP10
Rev 4.7
125
WM8233
REGISTER
BIT
LABEL
DEFAULT
1
POL9_PO1
0
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP10
logic level of PO1 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9
0
POL8_PO1
0
logic level of PO1 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 011Ch Polarity setting of P1 2
REGISTER
BIT
LABEL
DEFAULT
7
POL23_PO1
0
DESCRIPTION
REFER TO
ADDRESS
R285
(011Dh)
Polarity
setting
logic level of PO1 pulse at toggle point TP23
0 = low at TP23
1 = high at TP23
6
POL22_PO1
0
of P1 3
logic level of PO1 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22
5
POL21_PO1
0
logic level of PO1 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21
4
POL20_PO1
0
logic level of PO1 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20
3
POL19_PO1
0
logic level of PO1 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19
2
POL18_PO1
0
logic level of PO1 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18
1
POL17_PO1
0
logic level of PO1 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17
0
POL16_PO1
0
logic level of PO1 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 011Dh Polarity setting of P1 3
REGISTER
BIT
LABEL
DEFAULT
7
POL31_PO1
0
DESCRIPTION
REFER TO
ADDRESS
R286
(011Eh)
Polarity
setting
logic level of PO1 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31
6
POL30_PO1
0
of P1 4
logic level of PO1 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30
5
POL29_PO1
0
logic level of PO1 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29
4
POL28_PO1
0
logic level of PO1 pulse at toggle point TP28
0 = low at TP28
126
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
3
POL27_PO1
0
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP28
logic level of PO1 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27
2
POL26_PO1
0
logic level of PO1 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26
1
POL25_PO1
0
logic level of PO1 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25
0
POL24_PO1
0
logic level of PO1 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 011Eh Polarity setting of P1 4
REGISTER
BIT
LABEL
DEFAULT
7
POL7_PO2
0
DESCRIPTION
REFER TO
ADDRESS
R287
(011Fh)
Polarity
setting
logic level of PO2 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7
6
POL6_PO2
0
of P2 1
logic level of PO2 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6
5
POL5_PO2
0
logic level of PO2 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5
4
POL4_PO2
0
logic level of PO2 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4
3
POL3_PO2
0
logic level of PO2 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3
2
POL2_PO2
0
logic level of PO2 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2
1
POL1_PO2
0
logic level of PO2 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1
0
POL0_PO2
0
logic level of PO2 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 011Fh Polarity setting of P2 1
REGISTER
BIT
LABEL
DEFAULT
7
POL15_PO2
0
DESCRIPTION
REFER TO
ADDRESS
R288 (0120h)
of P2 2
logic level of PO2 pulse at toggle point TP15
0 = low at TP15
Polarity
setting
1 = high at TP15
6
POL14_PO2
0
logic level of PO2 pulse at toggle point TP14
0 = low at TP14
Rev 4.7
127
WM8233
REGISTER
BIT
LABEL
DEFAULT
5
POL13_PO2
0
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP14
logic level of PO2 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13
4
POL12_PO2
0
logic level of PO2 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12
3
POL11_PO2
0
logic level of PO2 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11
2
POL10_PO2
0
logic level of PO2 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10
1
POL9_PO2
0
logic level of PO2 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9
0
POL8_PO2
0
logic level of PO2 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0120h Polarity setting of P2 2
REGISTER
BIT
LABEL
DEFAULT
7
POL23_PO2
0
DESCRIPTION
REFER TO
ADDRESS
R289 (0121h)
of P2 3
logic level of PO2 pulse at toggle point TP23
0 = low at TP23
Polarity
setting
1 = high at TP23
6
POL22_PO2
0
logic level of PO2 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22
5
POL21_PO2
0
logic level of PO2 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21
4
POL20_PO2
0
logic level of PO2 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20
3
POL19_PO2
0
logic level of PO2 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19
2
POL18_PO2
0
logic level of PO2 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18
1
POL17_PO2
0
logic level of PO2 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17
0
POL16_PO2
0
logic level of PO2 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0121h Polarity setting of P2 3
128
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
7
POL31_PO2
0
DESCRIPTION
REFER TO
ADDRESS
R290 (0122h)
of P2 4
logic level of PO2 pulse at toggle point TP31
0 = low at TP31
Polarity
setting
1 = high at TP31
6
POL30_PO2
0
logic level of PO2 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30
5
POL29_PO2
0
logic level of PO2 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29
4
POL28_PO2
0
logic level of PO2 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28
3
POL27_PO2
0
logic level of PO2 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27
2
POL26_PO2
0
logic level of PO2 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26
1
POL25_PO2
0
logic level of PO2 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25
0
POL24_PO2
0
logic level of PO2 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0122h Polarity setting of P2 4
REGISTER
BIT
LABEL
DEFAULT
7
POL7_PO3
0
DESCRIPTION
REFER TO
ADDRESS
R291 (0123h)
of P3 1
logic level of PO3 pulse at toggle point TP7
0 = low at TP7
Polarity
setting
1 = high at TP7
6
POL6_PO3
0
logic level of PO3 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6
5
POL5_PO3
0
logic level of PO3 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5
4
POL4_PO3
0
logic level of PO3 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4
3
POL3_PO3
0
logic level of PO3 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3
2
POL2_PO3
0
logic level of PO3 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2
1
POL1_PO3
0
logic level of PO3 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1
0
POL0_PO3
0
logic level of PO3 pulse at toggle point TP0
0 = low at TP0
Rev 4.7
129
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP0
Register 0123h Polarity setting of P3 1
REGISTER
BIT
LABEL
DEFAULT
7
POL15_PO3
0
ADDRESS
R292 (0124h)
of P3 2
logic level of PO3 pulse at toggle point TP15
0 = low at TP15
Polarity
setting
1 = high at TP15
6
POL14_PO3
0
logic level of PO3 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14
5
POL13_PO3
0
logic level of PO3 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13
4
POL12_PO3
0
logic level of PO3 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12
3
POL11_PO3
0
logic level of PO3 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11
2
POL10_PO3
0
logic level of PO3 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10
1
POL9_PO3
0
logic level of PO3 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9
0
POL8_PO3
0
logic level of PO3 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0124h Polarity setting of P3 2
REGISTER
BIT
LABEL
DEFAULT
7
POL23_PO3
0
DESCRIPTION
REFER TO
ADDRESS
R293 (0125h)
of P3 3
logic level of PO3 pulse at toggle point TP23
0 = low at TP23
Polarity
setting
1 = high at TP23
6
POL22_PO3
0
logic level of PO3 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22
5
POL21_PO3
0
logic level of PO3 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21
4
POL20_PO3
0
logic level of PO3 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20
3
POL19_PO3
0
logic level of PO3 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19
2
POL18_PO3
0
logic level of PO3 pulse at toggle point TP18
0 = low at TP18
130
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
1
POL17_PO3
0
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP18
logic level of PO3 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17
0
POL16_PO3
0
logic level of PO3 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0125h Polarity setting of P3 3
REGISTER
BIT
LABEL
DEFAULT
7
POL31_PO3
0
DESCRIPTION
REFER TO
ADDRESS
R294 (0126h)
of P3 4
logic level of PO3 pulse at toggle point TP31
0 = low at TP31
Polarity
setting
1 = high at TP31
6
POL30_PO3
0
logic level of PO3 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30
5
POL29_PO3
0
logic level of PO3 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29
4
POL28_PO3
0
logic level of PO3 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28
3
POL27_PO3
0
logic level of PO3 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27
2
POL26_PO3
0
logic level of PO3 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26
1
POL25_PO3
0
logic level of PO3 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25
0
POL24_PO3
0
logic level of PO3 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0126h Polarity setting of P3 4
REGISTER
BIT
LABEL
DEFAULT
7
POL7_PO4
0
DESCRIPTION
REFER TO
ADDRESS
R295 (0127h)
of P4 1
logic level of PO4 pulse at toggle point TP7
0 = low at TP7
Polarity
setting
1 = high at TP7
6
POL6_PO4
0
logic level of PO4 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6
5
POL5_PO4
0
logic level of PO4 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5
4
POL4_PO4
0
logic level of PO4 pulse at toggle point TP4
0 = low at TP4
Rev 4.7
131
WM8233
REGISTER
BIT
LABEL
DEFAULT
3
POL3_PO4
0
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP4
logic level of PO4 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3
2
POL2_PO4
0
logic level of PO4 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2
1
POL1_PO4
0
logic level of PO4 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1
0
POL0_PO4
0
logic level of PO4 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 0127h Polarity setting of P4 1
REGISTER
BIT
LABEL
DEFAULT
7
POL15_PO4
0
DESCRIPTION
REFER TO
ADDRESS
R296 (0128h)
of P4 2
logic level of PO4 pulse at toggle point TP15
0 = low at TP15
Polarity
setting
1 = high at TP15
6
POL14_PO4
0
logic level of PO4 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14
5
POL13_PO4
0
logic level of PO4 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13
4
POL12_PO4
0
logic level of PO4 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12
3
POL11_PO4
0
logic level of PO4 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11
2
POL10_PO4
0
logic level of PO4 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10
1
POL9_PO4
0
logic level of PO4 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9
0
POL8_PO4
0
logic level of PO4 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0128h Polarity setting of P4 2
REGISTER
BIT
LABEL
DEFAULT
7
POL23_PO4
0
DESCRIPTION
REFER TO
ADDRESS
R297 (0129h)
of P4 3
logic level of PO4 pulse at toggle point TP23
0 = low at TP23
Polarity
setting
1 = high at TP23
6
POL22_PO4
0
logic level of PO4 pulse at toggle point TP22
0 = low at TP22
132
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
5
POL21_PO4
0
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP22
logic level of PO4 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21
4
POL20_PO4
0
logic level of PO4 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20
3
POL19_PO4
0
logic level of PO4 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19
2
POL18_PO4
0
logic level of PO4 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18
1
POL17_PO4
0
logic level of PO4 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17
0
POL16_PO4
0
logic level of PO4 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0129h Polarity setting of P4 3
REGISTER
BIT
LABEL
DEFAULT
7
POL31_PO4
0
DESCRIPTION
REFER TO
ADDRESS
R298
(012Ah)
Polarity
setting
logic level of PO4 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31
6
POL30_PO4
0
of P4 4
logic level of PO4 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30
5
POL29_PO4
0
logic level of PO4 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29
4
POL28_PO4
0
logic level of PO4 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28
3
POL27_PO4
0
logic level of PO4 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27
2
POL26_PO4
0
logic level of PO4 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26
1
POL25_PO4
0
logic level of PO4 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25
0
POL24_PO4
0
logic level of PO4 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 012Ah Polarity setting of P4 4
Rev 4.7
133
WM8233
REGISTER
BIT
LABEL
DEFAULT
7
POL7_PO5
0
DESCRIPTION
REFER TO
ADDRESS
R299
(012Bh)
Polarity
setting
logic level of PO5 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7
6
POL6_PO5
0
of P5 1
logic level of PO5 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6
5
POL5_PO5
0
logic level of PO5 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5
4
POL4_PO5
0
logic level of PO5 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4
3
POL3_PO5
0
logic level of PO5 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3
2
POL2_PO5
0
logic level of PO5 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2
1
POL1_PO5
0
logic level of PO5 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1
0
POL0_PO5
0
logic level of PO5 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 012Bh Polarity setting of P5 1
REGISTER
BIT
LABEL
DEFAULT
7
POL15_PO5
0
DESCRIPTION
REFER TO
ADDRESS
R300
(012Ch)
Polarity
setting
logic level of PO5 pulse at toggle point TP15
0 = low at TP15
1 = high at TP15
6
POL14_PO5
0
of P5 2
logic level of PO5 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14
5
POL13_PO5
0
logic level of PO5 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13
4
POL12_PO5
0
logic level of PO5 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12
3
POL11_PO5
0
logic level of PO5 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11
2
POL10_PO5
0
logic level of PO5 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10
1
POL9_PO5
0
logic level of PO5 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9
0
POL8_PO5
0
logic level of PO5 pulse at toggle point TP8
0 = low at TP8
134
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP8
Register 012Ch Polarity setting of P5 2
REGISTER
BIT
LABEL
DEFAULT
7
POL23_PO5
0
ADDRESS
R301
(012Dh)
Polarity
setting
logic level of PO5 pulse at toggle point TP23
0 = low at TP23
1 = high at TP23
6
POL22_PO5
0
of P5 3
logic level of PO5 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22
5
POL21_PO5
0
logic level of PO5 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21
4
POL20_PO5
0
logic level of PO5 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20
3
POL19_PO5
0
logic level of PO5 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19
2
POL18_PO5
0
logic level of PO5 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18
1
POL17_PO5
0
logic level of PO5 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17
0
POL16_PO5
0
logic level of PO5 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 012Dh Polarity setting of P5 3
REGISTER
BIT
LABEL
DEFAULT
7
POL31_PO5
0
DESCRIPTION
REFER TO
ADDRESS
R302
(012Eh)
Polarity
setting
logic level of PO5 pulse at toggle point TP31
0 = low at TP31
1 = high at TP31
6
POL30_PO5
0
of P5 4
logic level of PO5 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30
5
POL29_PO5
0
logic level of PO5 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29
4
POL28_PO5
0
logic level of PO5 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28
3
POL27_PO5
0
logic level of PO5 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27
2
POL26_PO5
0
logic level of PO5 pulse at toggle point TP26
0 = low at TP26
Rev 4.7
135
WM8233
REGISTER
BIT
LABEL
DEFAULT
1
POL25_PO5
0
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP26
logic level of PO5 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25
0
POL24_PO5
0
logic level of PO5 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 012Eh Polarity setting of P5 4
REGISTER
BIT
LABEL
DEFAULT
7
POL7_PO6
0
DESCRIPTION
REFER TO
ADDRESS
R303
(012Fh)
Polarity
setting
logic level of PO6 pulse at toggle point TP7
0 = low at TP7
1 = high at TP7
6
POL6_PO6
0
of P6 1
logic level of PO6 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6
5
POL5_PO6
0
logic level of PO6 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5
4
POL4_PO6
0
logic level of PO6 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4
3
POL3_PO6
0
logic level of PO6 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3
2
POL2_PO6
0
logic level of PO6 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2
1
POL1_PO6
0
logic level of PO6 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1
0
POL0_PO6
0
logic level of PO6 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 012Fh Polarity setting of P6 1
REGISTER
BIT
LABEL
DEFAULT
7
POL15_PO6
0
DESCRIPTION
REFER TO
ADDRESS
R304 (0130h)
of P6 2
logic level of PO6 pulse at toggle point TP15
0 = low at TP15
Polarity
setting
1 = high at TP15
6
POL14_PO6
0
logic level of PO6 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14
5
POL13_PO6
0
logic level of PO6 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13
4
POL12_PO6
0
logic level of PO6 pulse at toggle point TP12
0 = low at TP12
136
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
3
POL11_PO6
0
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP12
logic level of PO6 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11
2
POL10_PO6
0
logic level of PO6 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10
1
POL9_PO6
0
logic level of PO6 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9
0
POL8_PO6
0
logic level of PO6 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0130h Polarity setting of P6 2
REGISTER
BIT
LABEL
DEFAULT
7
POL23_PO6
0
DESCRIPTION
REFER TO
ADDRESS
R305 (0131h)
of P6 3
logic level of PO6 pulse at toggle point TP23
0 = low at TP23
Polarity
setting
1 = high at TP23
6
POL22_PO6
0
logic level of PO6 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22
5
POL21_PO6
0
logic level of PO6 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21
4
POL20_PO6
0
logic level of PO6 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20
3
POL19_PO6
0
logic level of PO6 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19
2
POL18_PO6
0
logic level of PO6 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18
1
POL17_PO6
0
logic level of PO6 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17
0
POL16_PO6
0
logic level of PO6 pulse at toggle point TP16
0 = low at TP16
1 = high at TP16
Register 0131h Polarity setting of P6 3
REGISTER
BIT
LABEL
DEFAULT
7
POL31_PO6
0
DESCRIPTION
REFER TO
ADDRESS
R306 (0132h)
of P6 4
logic level of PO6 pulse at toggle point TP31
0 = low at TP31
Polarity
setting
1 = high at TP31
6
POL30_PO6
0
logic level of PO6 pulse at toggle point TP30
0 = low at TP30
Rev 4.7
137
WM8233
REGISTER
BIT
LABEL
DEFAULT
5
POL29_PO6
0
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP30
logic level of PO6 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29
4
POL28_PO6
0
logic level of PO6 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28
3
POL27_PO6
0
logic level of PO6 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27
2
POL26_PO6
0
logic level of PO6 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26
1
POL25_PO6
0
logic level of PO6 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25
0
POL24_PO6
0
logic level of PO6 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0132h Polarity setting of P6 4
REGISTER
BIT
LABEL
DEFAULT
7
POL7_PO7
0
DESCRIPTION
REFER TO
ADDRESS
R307 (0133h)
of P7 1
logic level of PO7 pulse at toggle point TP7
0 = low at TP7
Polarity
setting
1 = high at TP7
6
POL6_PO7
0
logic level of PO7 pulse at toggle point TP6
0 = low at TP6
1 = high at TP6
5
POL5_PO7
0
logic level of PO7 pulse at toggle point TP5
0 = low at TP5
1 = high at TP5
4
POL4_PO7
0
logic level of PO7 pulse at toggle point TP4
0 = low at TP4
1 = high at TP4
3
POL3_PO7
0
logic level of PO7 pulse at toggle point TP3
0 = low at TP3
1 = high at TP3
2
POL2_PO7
0
logic level of PO7 pulse at toggle point TP2
0 = low at TP2
1 = high at TP2
1
POL1_PO7
0
logic level of PO7 pulse at toggle point TP1
0 = low at TP1
1 = high at TP1
0
POL0_PO7
0
logic level of PO7 pulse at toggle point TP0
0 = low at TP0
1 = high at TP0
Register 0133h Polarity setting of P7 1
138
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
7
POL15_PO7
0
DESCRIPTION
REFER TO
ADDRESS
R308 (0134h)
of P7 2
logic level of PO7 pulse at toggle point TP15
0 = low at TP15
Polarity
setting
1 = high at TP15
6
POL14_PO7
0
logic level of PO7 pulse at toggle point TP14
0 = low at TP14
1 = high at TP14
5
POL13_PO7
0
logic level of PO7 pulse at toggle point TP13
0 = low at TP13
1 = high at TP13
4
POL12_PO7
0
logic level of PO7 pulse at toggle point TP12
0 = low at TP12
1 = high at TP12
3
POL11_PO7
0
logic level of PO7 pulse at toggle point TP11
0 = low at TP11
1 = high at TP11
2
POL10_PO7
0
logic level of PO7 pulse at toggle point TP10
0 = low at TP10
1 = high at TP10
1
POL9_PO7
0
logic level of PO7 pulse at toggle point TP9
0 = low at TP9
1 = high at TP9
0
POL8_PO7
0
logic level of PO7 pulse at toggle point TP8
0 = low at TP8
1 = high at TP8
Register 0134h Polarity setting of P7 2
REGISTER
BIT
LABEL
DEFAULT
7
POL23_PO7
0
DESCRIPTION
REFER TO
ADDRESS
R309 (0135h)
of P7 3
logic level of PO7 pulse at toggle point TP23
0 = low at TP23
Polarity
setting
1 = high at TP23
6
POL22_PO7
0
logic level of PO7 pulse at toggle point TP22
0 = low at TP22
1 = high at TP22
5
POL21_PO7
0
logic level of PO7 pulse at toggle point TP21
0 = low at TP21
1 = high at TP21
4
POL20_PO7
0
logic level of PO7 pulse at toggle point TP20
0 = low at TP20
1 = high at TP20
3
POL19_PO7
0
logic level of PO7 pulse at toggle point TP19
0 = low at TP19
1 = high at TP19
2
POL18_PO7
0
logic level of PO7 pulse at toggle point TP18
0 = low at TP18
1 = high at TP18
1
POL17_PO7
0
logic level of PO7 pulse at toggle point TP17
0 = low at TP17
1 = high at TP17
0
POL16_PO7
0
logic level of PO7 pulse at toggle point TP16
0 = low at TP16
Rev 4.7
139
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
1 = high at TP16
Register 0135h Polarity setting of P7 3
REGISTER
BIT
LABEL
DEFAULT
7
POL31_PO7
0
ADDRESS
R310 (0136h)
of P7 4
logic level of PO7 pulse at toggle point TP31
0 = low at TP31
Polarity
setting
1 = high at TP31
6
POL30_PO7
0
logic level of PO7 pulse at toggle point TP30
0 = low at TP30
1 = high at TP30
5
POL29_PO7
0
logic level of PO7 pulse at toggle point TP29
0 = low at TP29
1 = high at TP29
4
POL28_PO7
0
logic level of PO7 pulse at toggle point TP28
0 = low at TP28
1 = high at TP28
3
POL27_PO7
0
logic level of PO7 pulse at toggle point TP27
0 = low at TP27
1 = high at TP27
2
POL26_PO7
0
logic level of PO7 pulse at toggle point TP26
0 = low at TP26
1 = high at TP26
1
POL25_PO7
0
logic level of PO7 pulse at toggle point TP25
0 = low at TP25
1 = high at TP25
0
POL24_PO7
0
logic level of PO7 pulse at toggle point TP24
0 = low at TP24
1 = high at TP24
Register 0136h Polarity setting of P7 4
REGISTER
BIT
LABEL
DEFAULT
0
USER_KEY
0
DESCRIPTION
REFER TO
ADDRESS
R432 (1B0h)
0 = User access disabled
1 = User access enabled
User access
control
Register 01B0h User access control
REGISTER
BIT
LABEL
DEFAULT
4:0
LDO2 VSEL
1_0000
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
R436 (1B4h)
1_0000 = 1.8V
1_0010 = 2.0V
LDO2 control
Register 01B4h LDO2 control
REGISTER
BIT
LABEL
DEFAULT
0
User_KEY2
0
ADDRESS
R448 (1C0h)
User access
140
0 = User access2 disabled
1 = User access2 enabled
Rev 4.7
WM8233
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
control2
Register 1C0h User access control2
REGISTER
BIT
LABEL
DEFAULT
1:0
PT_COMP
01
ADDRESS
R459 (1CBh)
01 = Standard operation
11 = High performance operation
Comp control
Other = Inhibit.
Register 1CBh Comp control
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
AVDD1 AVDD2
DBVDD
LDO1VDD
LDO2VDD
55
50
C1
22
C2
33
C3
9
C4
AGND1
AGND2
AVDD1
AGND3
56
49
46
AVDD2
LDO1VDD
VREF1C 4
VREF2C 1
LDO2VDD
VREF3C 3
DBVDD
AGND
C9
C8
C5
2
LDO1VOUT
VRLC/VBIAS
LDO2VOUT
C11
31
AVDD1 AVDD2 DBVDDLDO1VDD LDO2VDD
11
C12
WM8233
AGND
47
48
51
52
53
54
13
Timing
Signals
34
8
7
Interface
Controls
C6
AGND
AGND
Video
Inputs
C7
C10
5
14
12
IN1
IN2
IN3
IN4
IN5
IN6
MCLK
D1P/OP[0]
D1N/OP[1]
D2P/OP[2]
D2N/OP[3]
D3P/OP[4]
D3N/OP[5]
DCLKP/OC[1]
DCLKN/OP[2]
D4P/OP[6]
D4N/OP[7]
D5P/OP[8]
D5N/OP[9]
TGSYNC
SDI
SCK
SEN
DSLCT1
DSLCT2
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
C13
C14
AGND
28
27
26
25
24
23
20
19
18
17
16
15
35
36
37
38
39
40
41
42
43
44
45
C15
C16
C17
C18
AGND
LDO1VOUT
Output
Data
Bus
C19
LDO2VOUT
C20
AGND
Timing generator
Outputs
NOTES: 1. C1-20 should be fitted as close to device as possible.
2. AGND should be connected as close to device as possible.
Figure 50 External Components Diagram
Rev 4.7
141
WM8233
RECOMMENDED EXTERNAL COMPONENT DESCRIPTION
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1
0.1uF
De-coupling for AVDD1
C2
0.1uF
De-coupling for AVDD2
C3
0.1uF
De-coupling for DBVDD
C4
0.1uF
De-coupling for LDO1VDD
C5
0.1uF
De-coupling for LDO2VDD
C6
0.1uF
De-coupling for VREF1C
C7
0.1uF
De-coupling for VREF2C
C8
0.1uF
De-coupling for VREF3C
C9
0.01uF
High frequency decoupling between VREF1C and VREF3C
C10
10uF
Low frequency decoupling between VREF1C and VREF3C
C11
1uF
De-coupling for VRLC/VBIAS
C12
1uF
De-coupling for LDO1VOUT
C13
1uF
De-coupling for LDO2VOUT
C14
10uF
Reservoir capacitor for AVDD1
C15
10uF
Reservoir capacitor for AVDD2
C16
10uF
Reservoir capacitor for DBVDD
C17
10uF
Reservoir capacitor for LDO1VDD
C18
10uF
Reservoir capacitor for LDO2VDD
C19
10uF
Reservoir capacitor for LDOOUT
C20
10uF
Reservoir capacitor for LDOOUT
Table 15 External Components Descriptions
142
Rev 4.7
WM8233
PACKAGE DIMENSIONS
DM091.B
FL: 56 PIN QFN PLASTIC PACKAGE 8 X 8 X 0.85 mm BODY, 0.50 mm LEAD PITCH
D2
eee C B A
PIN 1
A
D2/2
D
B
56
43
L
36
INDEX AREA
(D/2 X E/2)
1
EXPOSED
6
GND
PADDLE
E2/2
E2
eee C B A
29
E
14
28
b
aaa C
2X
ddd M C A B
e
aaa C
2X
15
TOP VIEW
bbb C
(A3)
C
ccc C
M
Symbols
aaa
bbb
ccc
ddd
eee
REF
A
A1
SEATING PLANE
M
A
A1
A2
A3
b
D
D2
E
E2
e
L
A2
MIN
0.8
0
0.20
5.95
5.95
0.35
Dimensions (mm)
NOM
MAX
0.85
0.9
0.05
0.035
0.65
0.67
0.203 REF
0.25
0.30
8.00 BSC
6.05
6.15
8.00 BSC
6.05
6.15
0.5 BSC
0.45
0.4
NOTE
1
Tolerances of Form and Position
0.10
0.10
0.08
0.10
0.10
JEDEC, MO-220, VARIATION VLLD-2
NOTES:
1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.
2. ALL DIMENSIONS ARE IN MILLIMETRES
3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002.
4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION.
Rev 4.7
143
WM8233
IMPORTANT NOTICE
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic
group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the
time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided
pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its products and specifications or to
discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from
Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the
extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to
minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to
minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The
customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice
between many different modes of operation, some or all of which may require action by the user, and some or all of which may be
optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode over another.
Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they
would not be suitable for operation. Features and operations described herein are for illustrative purposes only.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL
INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS
ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY,
AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL
APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT
THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR
IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,
WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS,
CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS, EMPLOYEES,
DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT
MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
This document is the property of Cirrus Logic and by furnishing this information, Cirrus Logic grants no license, express or implied,
under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or
publication of any third party’s products or services does not constitute Cirrus Logic’s approval, license, warranty or endorsement
thereof. Cirrus Logic gives consent for copies to be made of the information contained herein only for use within your organization
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not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for
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information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents
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Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners.
Copyright © 2010–2016 Cirrus Logic, Inc. All rights reserved.
144
Rev 4.7
WM8233
REVISION HISTORY
DATE
REV
ORIGINATOR
CHANGES
PAGE
13/10/2010
1.0
AA
First Release
08/12/11
3.0
JMacD
Product status updated to pre-production,
10/12/11
3.0
AA
Corrected DAC description 4-bit to 8bit
1
Corrected temperature range to -40
5.8
Corrected ADCFS characteristics
9,10
Corrected RLCDAC resolution
10
Corrected Parameter name and Register name for RLCDAC
10,38
Added test condition for TG output
11
Corrected Supply Currents
21
Corrected Clamp timing diagram
24
Corrected Signal flow summary (removed INVOP description)
38,48
Corrected Register Map (ADCFS)
14/12/12
07/02/13
4.0
4.1
AA
AA
Corrected Channel ID description INP to IN
27
Corrected TG MASK description
31
Added spec of channel to channel offset matching
9
Corrected RLCDAC resolution
10
Corrected offset DAC INL DNL spec
10
Corrected supply current for full power down mode
11
Updated timing specification
16-18
Added description for 3pair, 4pair LVDS mode
26-28
Added LVDS output order
29
Corrected figure for ADC INPUT BLACK LEVEL ADJUST
20
Corrected figure for overall signal flow
21
Added description for PLL DLL setup
22
Corrected TG timing diagram
31-33
Added EXTENDED REGISTERS
50,118
Corrected description for R28
60
Corrected description for R128,R129
72,73
Corrected missing description.
21-30
(ADC PGA Bias current control, PLL DLL setup, Output data
format)
17/02/14
22/05/14
Rev 4.7
4.2
4.3
AA
AA
Corrected description of conversion rate
1
Corrected description of reference DAC resolution
1
Updated test condition for output noise specification
9
Corrected device ID descriptions (Table 2 and Table 3)
13,14
Corrected RESET CLAMPING description
17,18
Corrected CDS/Non-CDS PROCESSING description
19
Updated PLL and DLL setting table
22
Corrected TG-master/slave mode timing chart
34,35
Added TGSYNC low period specification
35
Added description for LINE BY LINE operation
48,58,74
Added description for TEST PATTERN GENERATOR
49,50,71,72
Added description for Register setting procedure
51~57
Added data latency specification
15
Updated tPER, tMCLKH and tMCLKL description
15
Removed tPER and tMCLKD description
32,34
Removed tTRGD and tPCKD description
35
Updated Data trigger timing delay specification
36
Corrected TG MASK TIMING description
42
Added description of Data Output Configuration
59,60
Corrected register description of SEL_PCK7,8,9,10,11
98,99
145
WM8233
DATE
REV
ORIGINATOR
CHANGES
PAGE
19/08/14
4.4
AA
Corrected pin name (PO0~PO9)
5,61,72~74
20/10/15
4.5
PH
Test limit (min/max) conditions added in Elec Chars
8-10
Signal timing limits added
15, 35
Amendment to LVDS_AMP description
60, 70
27/11/15
4.6
PH
Electrical characteristics updated
8-10
25/03/16
4.7
PH
Digital pin output impedance updated
10
146
Rev 4.7