APL3548

APL3548
Preliminary
6A, 24V High-Side Power Distribution Switch with Softstart
Features
General Description
•
•
•
•
•
•
•
•
•
•
•
APL3548 is a high-side power distribution switch, allow
for +12V, +19V or +9.5V power-supply rail. The wrong
Internal 40mΩ High-Side N-Channel MOSFET
Under-Voltage Lockout (UVLO)
input voltage protection function protects a wrong input of
adapter insertion, when input voltage is out of the target
Wrong VIN Input Voltage Protection
Short-Circuit Protection During Power-up (SCP)
input voltage range the IC is off.
The APL3548 provides a short-circuit protection during
Adjustable OCP Threshold
Adjustable Softstart Time
power-up. When a short circuit is present before soft start,
the IC will limit the output current at 300mA during dead
Selectable VIN Monitor Voltage
Shutdown Function
short condition (VOUT<1V) unless the short circuit has been
removed and the output voltage has risen above 1V. After
Power Good Output
power-up the OCP function prevents the IC from catastrophic failure from over-load and short circuit conditions.
Available in SOP-8P and TDFN3x3-10 Packages
Lead Free and Green Devices Available
If an OC event is detected, the IC immediately shuts down
the internal power switch and will initiate a new soft start
(RoHS Compliant)
cycle. The OCP tripping threshold is set by the external
resistor on OCSET pin.
Other features include an adjustable soft start time and a
logic-controlled shutdown mode. The device is available
Applications
•
•
in SOP-8P and TDFN3x3-10 Packages.
LCD TV
LCD Monitor
Pin Configuration
ISET 1
10 GND
SS 2
9 EN
VINSEL 3
8 VIN
VOUT 4
7 VIN
VOUT 5
6 POK
ISET 1
8 SS
VINSEL 2
7 GND
VIN 3
6 EN
VOUT 4
TDFN3x3-10
Top View
5 POK
SOP-8P
Top View
= Exposed Pad
(connected to ground plane for better heat dissipation)
= Exposed Pad
(connected to ground plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
1
www.anpec.com.tw
APL3548
Preliminary
Ordering and Marking Information
APL3548
Assembly Material
Handling Code
Temperature Range
Package Code
APL3548 KA :
APL3548 QB :
APL3548
XXXXX
APL
3548
XXXXX
Package Code
QB : TDFN3x3-10
KA : SOP-8P
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
XXXXX - Date Code
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
VIN
VEN ,VVINSEL
VPOK ,VOCSET,
VSS
TJ
(Note 1)
Parameter
Rating
Unit
VIN Input Voltage (VIN to GND)
-0.3 to 27
V
EN, VINSEL to GND Voltage
-0.3 to 27
V
-0.3 to 7
V
POK, OCSET, SS to GND Voltage
Maximum Junction Temperature
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature (10 Seconds)
150
o
-65 to 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Sym bol
θ JA
θ JC
P arame ter
Typic al Value
o
60
o
S OP -8P
7
o
TDFN3x3 -10
8
C/W
Junction-to- Ambien t Resistance
TDFN3x3 -10
Junction-to- Ca se Resista nce
Unit
50
S OP -8P
C/W
C/W
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
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APL3548
Preliminary
Recommended Operating Conditions
Symbol
VIN
P aramet er
VIN Inpu t Voltage (VIN to GND)
VEN ,VVINSEL EN, VINSE L to GND Voltage
In te rnal So ft-Soft Time
C SS_MIN
Minimum Soft-Start Ca pacito r
VOUT Maximum Continuo us Curre nt
Ambie nt Tempera tu re
TJ
4.5 to 2 4
V
4.5 to 2 4
V
Adjustable Soft-Start Time (VIN=19V)
TBD
Adjustable Soft-Start Time (VIN=12V)
TBD
Adjustable Soft-Start Time (VIN=5V)
TBD
nF
6
I OU T
Juncti on Temp erature
Unit
0
VOUT Maximum Pulse Curre nt
TA
Range
TA ≦50 C
o
A
5
A
-40 to 85
o
-40 to 12 5
o
C
C
Note 3: Refer to the typical application circuit
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=19V, VEN =5V and TA= -40 to 85 oC. Typical values are at TA=25oC.
Sym bol
Param eter
APL3548
Test Conditions
Min
Unit
Typ
Max
3.3
-
4.2
V
-
0.35
-
V
VIN >V UVLO , VEN =5V, and
VVINSEL(H )>VVINSEL> V VIN SEL (L)
-
10
-
ms
No load , VEN =5V
-
250
4 00
µA
No load , VEN =0V
-
10
50
µA
SOP- 8P
-
44
50
mΩ
TDFN3x3 -10
-
40
48
mΩ
VVINSEL rising, IC is on , VIN=4.5V to 24 V
1 .2 96
1.350
1 .4 04
V
VVINSEL falling , IC is o ff, VIN=4.5V to 24 V
1 .1 52
1.200
1 .2 48
mV
VVINSEL rising, IC is off, VIN=4.5 V to 24 V
1 .7 28
1.800
1 .8 72
V
VINSEL Hi gh Detectio n Fa lling
Th reshold
VVINSEL falling , IC is o n, VIN=4.5V to 2 4V
1 .5 84
1.650
1 .7 16
mV
VINSEL
Th reshold
UNDER-VO LTAGE LOCKOUT (UVLO) AND S UP PLY CURRENT
VU VLO_ R
VIN UVLO Thresho ld Vo ltag e
VIN rising
VU VLO_HYS VIN UVLO Hystere sis
T D (ON)
IVIN
Power-On Del ay Tim e
VIN Sup ply Cur rent
POWER MOSFET
Power MOSFET On Resistan ce
T J= 25 oC.
WRONG VIN INPUT VOLTAGE P ROTECTION
VVINSEL(L)
VVINSEL (H)
VINSEL Low
Th reshold
Detecti on
Rising
VINSEL L ow
Th reshold
Detecti on
Fa lling
VINSEL High
Th reshold
Detectio n Rising
Detectio n
Disable
VVINSEL fallin g, VINSE L d etectio n fun ction
is disabled . VIN=4.5V to 24 V
0.15
0.2
0.25
V
VINSEL
Detectio n
Th reshold Hystere sis
Disable
VVINSEL rising, VINSE L detection fun ction
is eable d. VIN=4.5V to 2 4V
-
100
-
mV
VINSEL Inp ut Curre nt
VVINSEL=24V
-
-
1
µA
VINSEL L ow Detection Debou nce
VVINSEL falling , VVINSEL < VVINSEL(L )
-
10
-
µs
VINSEL Hig h De tection Debo unce
VVINSEL rising, VVINSEL > VVINSEL(H)
-
10
-
µs
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
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APL3548
Preliminary
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VIN=19V, VEN =5V and TA= -40 to 85 oC. Typical values are at TA=25oC.
Symbol
Parame ter
Test Conditions
Min
Typ
Ma x
Unit
-
5.3
-
V
-
1.75
-
µA
CHARGE PUMP AND SOFTS TART AND DISCHARG E
Inte rnal 5V Voltage
SS P in O utput Cu rrent
V IN=4 .5 ~24V, SS =G ND
Inte rnal So ft-Soft Time
V IN=1 9V
SS P in Discharg e Re sistance
V IN=4 .5 ~24V, E N=GND, SS =1V
-
2
-
kΩ
VO UT Di scha rge Resistance
V IN=1 9V, E N=G ND, V OUT=1V
-
75
-
Ω
V IN=4 .5 ~24V
-
3 00
-
mA
-
0.6
-
V
A
TBD
ms
PROTECTIONS
Pre -Charge Curr ent
OCSE T Outpu t Voltage
Over Curren t Tr ippin g P oint
R OCSET =1 MΩ
-
3
-
R OCSET =3 90kΩ
-
8.1
-
(Not e 4 )
-
1 40
(Not e 4 )
-
EN Logi c Input Thre shold
A
-
o
C
20
-
o
C
0.9
1.25
1.6
V
EN In put L ogic Hyste resis
-
0.2
-
V
EN Pull- up Current
-
1
-
µA
85
90
95
% VIN
Over Tempera tu re P rotection
Over Tempera tu re P rotection
Hysteresis
EN INPUT
VEN_ TH
PO K OUTPUT
V POK
t D(POK)
Rising POK Thre sh old Volta ge
V OUT rising , VOUT/VIN, VPOK=High
PO K Thr eshold Hysteresis
V OUT falling , VPOK=L ow
-
5
-
% VIN
PO K Low Vol tag e
I POK=10 mA
-
-
0.5
V
PO K Leakag e Cu rrent
V POK=5V
-
-
1
µA
3
ms
-
µs
PO K Rising Del ay Time
V OUT rising , POK a ssertion
1
2
PO K Fa lling Debo unce Time
V OUT falling (N ot e 4 )
-
10
Note 4: Guarantee by design, not production test.
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
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APL3548
Preliminary
Pin Description
PIN
NO.
FUNCTION
NAM E
SOP-8P
TDFN3 x3- 10
1
1
OCSET
O ve r-Curren t Trip Poin t A djustment Pin. A resistor (R OCSET) from th is p in to gr ound
sets the over curre nt trippi ng point th reshold .
2
3
V INSEL
Inp ut Voltage Se nse P in. Con nect a resistive divide r from VIN to VINS EL to GND to
mo nitor the i nput vol tag e. Pu lling VVINSEL bel ow 0.3V will disab le this functio n.
3
7,8
VIN
P ower Inpu t Pin. Pro vid e po we r to th e intern al circuitry and also conn ect to the
i nte rnal p ower MOSFE T’ s Drain termin al. Wh en the Po we r MOSFET is tu rned o n,
V IN pro vid es po we r to VO UT.
4
4,5
VO UT
P ower Outpu t Pin. Th is pin is i nternally connected to the inter nal power MOSFET’ s
sou rce termin al. When the P ower MO SFET is tur ned on, the VOUT can dra w power
from VIN. Curre nt can flow from VOUT to VIN too.
5
6
PO K
P ower Okay Indicator Output. The POK is a n o pen-d rain pull- down d evice. When
V OUT voltage falls an d r eaches the falling Po we r-OK voltage threshold , the POK
o utput i s pu lled low; whe n VOUT voltag e r ise s an d reaches the rising Po wer -OK
voltage thre shold, the POK outpu t is in hi gh impeda nce.
6
9
EN
E nab le Inpu t. P ullin g the VEN above 2V will e nable the IC; pu lling VEN be low 0.6V
will di sa ble th e IC. This pin is p ulled hig h by an i nte rnal curren t source.
7
10
GND
8
2
SS
G roun d pin.
V OUT Risi ng S lew Rate Control . A cap aci to r from this pin to grou nd se ts a VOUT
r isi ng sl ew ra te.
Block Diagram
Power
MOSFET
VIN
VOUT
5V
5V
LDO
Charge
Pump
Pre-Charge
Current
5V
1µA
EN
OCSET
OCP
Enable
Control Logic
Gate Driver
and
Control Logic
Enable
Enable
1.6V
0.2V
5V
1. 75µA
1.8V
1. 65V
1
0
SS
OTP
VINSEL
1. 35V
1.2V
0
1
POK
VOUT
90%VIN
Enable
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
5
POK Rising Delay
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APL3548
Preliminary
Typical Application Circuit
19V
R1
20kΩ
1%
VIN
CIN2
100µF
VINSEL
CIN1
10µF
R3
100kΩ
R2
1.8kΩ
1%
APL3548
SS
VOUT
CSS
1nF
COUT
10µF
EN
OCSET
ROCSET
390kΩ
1%
POK
5V
ROCSET
10kΩ
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
GND
6
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APL3548
Preliminary
Function Description
Under-voltage Lockout (UVLO)
Enable/Shutdown Control
The APL3548 power switch is built-in an under-voltage
lockout circuit to keep the output shut off until internal
The APL3548 has an active-high enable function. Pulling
the VEN above 2V will enable the IC; pulling VEN below 0.6V
circuitry is operating properly. The UVLO circuit has hysteresis and a de-glitch feature so that it will typically ig-
will disable the IC and the POK is pulled low immediately
(ignore the VPOK(TH) and TD(POK)), the VOUT voltage is also
nore undershoot transients on the input. When input voltage exceeds the UVLO threshold, the output voltage starts
discharged to GND by an internal resistor . EN pin is pulled
high by an internal current source and can be left floating.
a soft-start to reduce the inrush current.
Soft-Start
Power Switch
The power switch is an N-channel MOSFET with a low
The APLA3548 provides an adjustable soft-start circuitry
to control rise rate of the output voltage and limit the cur-
RDS(ON). When IC is off, the MOSFET prevents a current
flowing from VIN to VOUT. Once the MOSFET is turned
rent surge during start-up. The soft-start ramp-up rate is
controlled by a capacitor from SS pin to the ground.
on, the current is by-directional. Note that the MOSFET
possesses a body diode which allows the current to flow
Under a specific VIN being applied to the APL3548, the soft
start time can be calculated by the following equation:
through it in shutdown and body diode forward-biased
condition, VOUT-VIN>0.3V.
tSS = (CSS x VIN )/(ISS x 7.82)
Over Current Protection
The APL3548 power switch provides the over current pro-
where,
tSS is soft-start time of VOUT rising from 0 to 100%, of which
tection function. The OCP threshold is set by the resis-
unit is second.
CSS is the value of the capacitor connected from SS pin to
tance from OCSET pin to ground. The OCP threshold
equation is as below:
GND, of which unit is micro-Farad.
VIN is the amplitude of input voltage applied to this device,
IOCP(A)=2800/ROCSET(kΩ)+0.7
of which unit is volt. ISS is typically 1.75µA.
When the OCP threshold is tripped, the IC immediately
turns off its power switch and thus prevents over current
flowing from VIN to VOUT. In output dead short condition,
POK Output
an internal 300mA current source provides the power to
VOUT. If the short circuit condition persists, so as the
drives the POK low to indicate a fault. When a fault condition such as over temperature, or wrong VIN input voltage
300mA current source. Only when OTP shutdown or dead
short removal the 300mA is turned off.
is occurred, or over-current and the VOUT output voltage
falls to 85% of the VIN input voltage, the POK is pulled
Wrong VIN Input Voltage Protection
low. When the VOUT output voltage reaches to 90% of
VIN input voltage, and after POK rising delay time, the
The power okay function monitors the output voltage and
The APL3548 provides an input voltage detection func-
POK is pulled high. Since the POK is an open-drain
device, connecting a resistor to a pull high voltage is
tion to protect a wrong input adapter insertion. Connect a
resistive divider from VIN to VINSEL to GND to set the
necessary.
target input voltage. The target input voltage is set at:
VIN(target)=1.5V x (1+R1/R2)
The IC is enabled When input voltage is within the VIN(target)
+15% (VIN also must be above VUVLO and EN is high); the
device is shut down when input voltage is outside the VIN
(target)+20%.
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
7
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APL3548
Preliminary
Function Description (Cont.)
Over-Temperature Protection
When the junction temperature exceeds 140oC, the internal thermal sense circuit turns off the power FET and
allows the device to cool down. When the device’s junction temperature cools by 20 oC, the internal thermal
sense circuit will enable the device, resulting in a pulsed
output during continuous thermal protection. Thermal protection is designed to protect the IC in the event of overtemperature conditions. For normal operation, the
junction temperature cannot exceed TJ=125oC.
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
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APL3548
Preliminary
Application Information
Input Capacitor
Layout Consideration
A 10µF or higher ceramic bypass capacitor from VIN to
The PCB layout should be carefully performed to maxi-
GND, located near the APL3548, is strongly recommended
to suppress the ringing during short circuit fault event.
mize thermal dissipation and to minimize voltage drop,
droop and EMI. The following guidelines must be
When the load current trips the OCP threshold in an over
load condition such as a short circuit, hot plug-in or heavy
considered:
1. Please place the input capacitors near the VIN pin as
load transient the IC immediately turns off the internal
power switch that will cause VIN ringing due to the para-
close as possible.
2. Output decoupling capacitors for load must be placed
sitical inductance between power source and VIN. Without
the bypass capacitor, the output short may cause suffi-
near the load as close as possible for decoupling high
frequency ripples.
cient ringing on the input to damage internal control
circuitry. Input capacitor is especially important to prevent
3. Locate APL3548 and output capacitors near the load to
reduce parasitic resistance and inductance for excellent
VIN from ringing too high in some applications where the
inductance between power source to VIN is large (ex, an
load transient performance.
4. The negative pins of the input and output capacitors
extra bead is added between power source line to VIN for
EMI reduction) or applications where VIN voltage is 19V or
and the GND pin must be connected to the ground plane
of the load.
so which is near its maximum rating, additional input
capacitance may be needed on the input to reduce volt-
5. Keep VIN and VOUT traces as wide and short as possible.
age overshoot from exceeding the absolute maximum
voltage of the device during over load conditions.
Output Capacitor
A low-ESR 10µF between VOUT and GND is strongly recommended to reduce the voltage droop during hot-attachment of downstream peripheral.
Higher-value output capacitor is better when the output
load is heavy. Additionally, bypassing the output with a 0.
1µF ceramic capacitor improves the immunity of the device to short-circuit transients.
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
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APL3548
Preliminary
Package Information
TDFN3x3-10
D
E
A
b
Pin 1
A1
D2
A3
L
K
E2
Pin 1 Corner
e
TDFN3x3-10
S
Y
M
B
O
L
A
MIN.
MAX.
MIN.
MAX.
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
0.30
0.007
0.012
3.10
0.114
0.122
A3
b
INCHES
MILLIMETERS
0.20 REF
0.18
0.008 REF
D
2.90
D2
2.20
2.70
0.087
0.106
E
2.90
3.10
0.114
0.122
1.75
0.055
0.069
0.50
0.012
E2
1.40
e
L
K
0.50 BSC
0.30
0.020 BSC
0.020
0.008
0.20
Note : 1. Followed from JEDEC MO-229 VEED-5.
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
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APL3548
Preliminary
Package Information
SOP-8P
D
SEE VIEW A
h X 45o
E
E1
THERMAL
PAD
E2
D1
c
0.25
A2
A1
NX
aaa
A
b
e
c
GAUGE PLANE
SEATING PLANE
L
VIEW A
S
Y
M
B
O
L
SOP-8P
MILLIMETERS
MIN.
INCHES
MIN.
MAX.
A
MAX.
1.60
A1
0.00
0.063
0.000
0.15
0.006
0.049
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
0.138
D1
2.50
3.50
0.098
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
3.00
0.079
0.118
E2
2.00
e
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0oC
8oC
0oC
8 oC
0
aaa
0.10
0.004
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
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APL3548
Preliminary
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
OD1
B
A
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.30±0.20
TDFN3x3-10
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
0.6+0.00
-0.40
6.55±0.20
5.25±0.20
2.10±0.20
Application
SOP-8P
4.0±0.10
8.0±0.10
1.5
MIN.
(mm)
Devices Per Unit
Package Type
U nit
Quantity
TDFN-3x3-10
Tape & Reel
3000
SOP-8P
Tape & Reel
2500
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
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APL3548
Preliminary
Taping Direction Information
TDFN3x3-10
USER DIRECTION OF FEED
SOP-8P
USER DIRECTION OF FEED
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
13
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APL3548
Preliminary
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
14
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APL3548
Preliminary
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
15
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APL3548
Preliminary
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. P.3 - Dec., 2015
16
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