CS3002 Precision Low-voltage Amplifier; DC to 2kHz Features & Description Description • Low Offset: 10V Max • Low Drift: 0.05V/°C Max • Low Noise - 6nV/ Hz @ 0.5Hz The CS3002 dual amplifier is designed for precision amplification of low-level signals and is ideally suited for applications that require very high closed-loop gains. These amplifiers achieve excellent offset stability, superhigh open-loop gain, and low noise over time and temperature. The devices also exhibit excellent CMRR and PSRR. The common mode input range includes the negative supply rail. The amplifiers operate with any total supply voltage from 2.7V to 6.7V (±1.35V to ±3.35V). - 0.1 to 10Hz = 125 nVpp - 1/f corner @ 0.08Hz • Open-loop Voltage Gain - 300dB Typical - 200dB Minimum Pin Configuration • Rail-to-rail Output Swing • Slew Rate: 5V/s CS3002 Applications Out A 1 • • • • -In A 2 Thermocouple/Thermopile Amplifiers Load Cell and Bridge Transducer Amplifiers Precision Instrumentation Battery-powered Systems +In A 3 V- 4 8 V+ A - + 7 Out B B + - 6 -In B 5 +In B 8-lead SOIC CS3002 Noise vs. Frequency (Measured) Dexter Research Thermophile 1M 100 nV/√Hz R2 64.9k 10 1 0.001 R1 100 0.01 0.1 1 C2 0.015F 10 Frequency (Hz) Cirrus Logic, Inc. http://www.cirrus.com Copyright Cirrus Logic, Inc. 2012 (All Rights Reserved) DEC ‘12 DS490F10 CS3002 TABLE OF CONTENTS 1. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Typical Performance Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Open-loop Gain and Phase Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Open-loop Gain and Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.1 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.2 Gain Calculation Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 11 Calculate the Compensation Capacitor Value: . . . . . . . . . . . . . . . . . 11 Verify the Op Amp Compensation: . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4. Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . 13 7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LIST OF FIGURES Figure 1. Noise vs. Frequency (Measured)................................................................................... 4 Figure 2. Noise vs. Frequency ...................................................................................................... 4 Figure 3. 0.01Hz to 10Hz Noise ................................................................................................... 4 Figure 4. Offset Voltage Stability (DC to 3.2Hz) ........................................................................... 4 Figure 5. Supply Current vs. Temperature.................................................................................... 4 Figure 6. Supply Current vs. Supply Voltage ................................................................................ 4 Figure 7. Open-loop Gain and Phase vs. Frequency.................................................................... 5 Figure 8. Open-loop Gain and Phase vs. Frequency (Expanded) ................................................ 5 Figure 9. Input Bias Current vs. Supply Voltage ........................................................................... 6 Figure 10. Input Bias Current vs. Common Mode Voltage ........................................................... 6 Figure 11. Voltage Swing vs. Output Current ............................................................................... 7 Figure 12. Voltage Swing vs. Output Current (5V) ....................................................................... 7 Figure 13. Open-loop Gain and Phase Response ........................................................................ 8 Figure 14. Non-inverting Gain Configuration ................................................................................ 9 Figure 15. Non-inverting Gain Configuration with Compensation ................................................. 9 Figure 16. Loop Gain Plot: Unity Gain and with Pole-zero Compensation ................................. 10 Figure 17. Thermopile Amplifier with a Gain of 650V/V ............................................................. 12 Figure 18. Load Cell Bridge Amplifier and A/D Converter .......................................................... 12 2 DS490F10 CS3002 1. CHARACTERISTICS AND SPECIFICATIONS 1.1 Electrical Characteristics Typical characteristics conditions: • TA = 25 °C, V+ = +5 V, V- = 0 V, VCM = 2.5V • All voltages are measured with respect to V- Minimum/Maximum characteristics conditions: • TJ = -40°C to +125 °C, V+ = +5 V, V- = 0 V, VCM = 2.5V Condition Parameter Min Typ Max Unit Input Offset Voltage (Note 1) - - ±10 µV Average Input Offset Drift (Note 1) - ±0.01 ±0.05 µV/ºC Long Term Input Offset Voltage Stability (Note 2) TA = 25ºC - ±100 - ±1000 pA pA TA = 25ºC - ±200 - ±2000 pA pA RS = 100, f0 = 1Hz RS = 100, f0 = 1kHz - 6 6 nV/ Hz nV/ Hz 0.1 to 10Hz - 125 nVpp f0 = 1Hz - 100 fA/ Hz 0.1 to 10Hz - 1.9 pAp-p Input Common Mode Voltage Range -0.1 - (V+)-1.25 V Common Mode Rejection Ratio (DC) (Note 3) 115 120 - dB Power Supply Rejection Ratio 120 136 - dB RL = 2k to V+/2 200 300 - dB RL = 2k to V+/2 RL = 100k to V+/2 +4.7 +4.99 - V V 5 - V/µs - 100 - µs Input Bias Current Input Offset Current Input Noise Voltage Density Input Noise Voltage Input Noise Current Density Input Noise Current Large Signal Voltage Gain (Note 4) Output Voltage Swing RL = 2k, 100pF Slew Rate Overload Recovery Time PWDN Threshold (Note 5) (V+) -1.0 - - V Start-up Time (Note 5) - 9 12 ms Notes: 1. 2. 3. 4. 5. This parameter is guaranteed by design and laboratory characterization. Thermocouple effects prohibit accurate measurement of these parameters in automatic test systems. 1000-hour life test data @ 125 °C indicates randomly distributed variation approximately equal to measurement repeatability of 1µV. Measured within the specified common mode range limits. Guaranteed within the output limits of (V+ - 0.3V) to (V- + 0.3V). Tested with proprietary production test method. The device has a controlled start-up behavior due to its complex open-loop gain characteristics. Start-up time applies when supply voltage is applied or when PDWN is released. 1.2 Absolute Maximum Ratings Parameter Min Max Unit 6.8 V (V-) - 0.3 (V+) + 0.3 V -65 +150 ºC Supply Voltage [(V+) - (V-)] Input Voltage Storage Temperature Range DS490F10 Typ 3 CS3002 2. TYPICAL PERFORMANCE PLOTS 1000 Noise vs. Frequency (Measured) 100 nV/√Hz nV/√Hz 100 10 10 1 10 1 0.001 0.01 0.1 1 100 1K 10K 100K 1M 10M 10 Frequency (Hz) Frequency (Hz) Figure 1. Noise vs. Frequency (Measured) Figure 2. Noise vs. Frequency 100 100 75 -50 -100 0 1 2 3 4 5 6 7 8 9 σ = 13 nV 50 25 0 -25 -50 -75 0 nV nV 50 10 -100 TIME (Sec) Time (1 Hour) Figure 4. Offset Voltage Stability (DC to 3.2Hz) Figure 3. 0.01Hz to 10Hz Noise 2 4.0 Supply Current (mA) Supply Current (mA) 4.5 6.7 V 3.5 2.7 V 3.0 2.5 2.0 1.8 1.7 1.6 1.5 -40 -20 0 20 40 60 Temperature (°C) Figure 5. Supply Current vs. Temperature 4 1.9 80 2 3 4 5 6 7 Supply Voltage (V) Figure 6. Supply Current vs. Supply Voltage DS490F10 CS3002 500 400 300 200 100 0 -100 -200 -300 -400 -500 GAIN PHASE 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) Figure 7. Open-loop Gain and Phase vs. Frequency 100 Gain (dB) 80 60 40 20 0 Phase (Degrees) -45 -90 -135 -180 -225 -270 -315 -360 10K 100K 1M 10M Figure 8. Open-loop Gain and Phase vs. Frequency (Expanded) DS490F10 5 CS3002 Input Bias Current (pA) -150 A1A1+ B1A2+ B1+ A2- -100 -50 0 -50 -100 B2B2+ CM = 0 V -150 -200 ±3.35 ±2.5 ±2 ±1.35 Supply Voltage (±V) Bias Current Normalized to CM = 2.5 V Figure 9. Input Bias Current vs. Supply Voltage 3 2 1 0 -1 -2 -3 0 1 2 3 4 5 Common Mode Voltage (Vs = 5V) Figure 10. Input Bias Current vs. Common Mode Voltage 6 DS490F10 CS3002 V+ V+ -50 -50 -100 Output Voltage (mV) +125°C -200 +25°C -250 +250 +125°C +200 +25°C +125°C -200 +25°C -250 +250 +125°C +200 +25°C +150 +150 -40°C +100 -40°C +100 +50 +50 V– -40°C -150 -150 Output Voltage (mV) -100 -40°C V– 0 1 2 3 Output Current (mA) 4 Figure 11. Voltage Swing vs. Output Current DS490F10 5 0 1 2 3 Output Current (mA) 4 5 Figure 12. Voltage Swing vs. Output Current (5V) 7 CS3002 3. OVERVIEW The CS3002 amplifiers are designed for precision measurement of signals from DC to 2kHz when operating from a supply voltage of +2.7V to +6.7V (1.35V to 3.35V). The amplifiers are designed with a patented architecture that utilizes multiple amplifier stages to yield very high open-loop gain at frequencies of 10 kHz and below. The amplifiers yield low noise and low offset drift while consuming relatively low supply current. An increase in noise floor above 2kHz is the result of intermediate stages of the amplifier being operated at very low currents. The amplifiers are intended for amplifying small signals with large gains in applications where the output of the amplifier can be band-limited to frequencies below 2kHz. 3.1 Open-loop Gain and Phase Response Figure 13 illustrates the open-loop gain and phase response of the CS3002. The gain slope of the amplifier is approximately -100dB/decade between 500Hz and 60kHz and transitions to -20dB/decade between 60kHz and its unity gain crossover frequency at approximately 4.8MHz. Phase margin at unity gain is about 70 and the gain margin is approximately 20dB. 100 Gain (dB) 80 -100 dB/ dec 60 40 -20 dB/ dec 20 0 Phase (Degrees) -45 -90 -135 -180 -225 -270 -315 -360 10K 100K 1M 10M Figure 13. Open-loop Gain and Phase Response 8 DS490F10 CS3002 RS Vin Vo CS3002 R2 R1 Figure 14. Non-inverting Gain Configuration 3.2 Open-loop Gain and Stability A higher value for R produces a pole at a lower frequency, thus reducing the phase margin. Resistor R1 is recommended to be less than or equal to 100 , which results in a pole at 30MHz or higher. If a higher value of R1 is desired, compensation capacitor C2 should be added in parallel with resistor R2. Capacitor C2 should be chosen using Equation 2: 3.2.1 Discussion The CS3002 achieves ultra-high open-loop gain. Figure 14 illustrates the amplifier in a non-inverting gain configuration. The open-loop gain and phase plots indicate that the amplifier is stable for closed-loop gains less than 50V/V and R1 100 . For a gain of 50, the phase margin is between 40 and 60 depending upon the loading conditions. As shown in Figure 15, on page 9, the operational amplifier has an input capacitance at the + and – signal inputs of typically 50pF. This capacitance adds an additional pole in the loop gain transfer function at a frequency defined using Equation 1: 1 f = -------------------------2R C in R2 C2 R1 C in [Eq. 2] The feedback capacitor C2 is required for closed-loop gains greater than 50V/V. The capacitor introduces a pole P1 and a zero Z1 in the loop gain transfer function T(s), see Equation 3 s – 1 + ------ Z1 T s = ------------------------- A ol s 1 + ----- P 1 [Eq. 1] where [Eq. 3] R = R1 R2; the parallel combination of R1 and R2 Vin Cin 50 pF CS3002 Vo 50 pF Cin R2 Choose C2 so that R2 C2 R1 C in R1 C2 Figure 15. Non-inverting Gain Configuration with Compensation DS490F10 9 CS3002 Equation 4 is used to determine transfer function zero Z1. 1 Z 1 = -------------------------------------------------2 A R1 C2 [Eq. 4] where |A| = R2/R1 Substituting A into Equation 4 then zero Z1 is: 1 Z 1 = ----------------------------------2 R2 C2 [Eq. 5] Equation 6 is used to determine the transfer function pole P1. 1 1 P 1 = ----------------------------------------------------- ----------------------------------2 R1 R2 C2 2 R1 C2 [Eq. 6] (the frequency at which the slope changes from -100dB/decade to -20dB/decade). The loop gain plot shown in Figure 16 illustrates the unity gain configuration, and indicates how this is modified when using the amplifier in a higher gain configuration with compensation. If it is configured for higher gain, for example, 60dB, the x-axis will move up by 60dB (line B). Capacitor C2 adds a zero and a pole. The modified plot indicates the effects of introducing the pole and zero due to capacitor C2. The pole can be located at any frequency higher than the hand-over frequency, the zero has to be at a frequency lower than the hand-over frequency so as to provide adequate gain margin. The separation between the pole and the zero is governed by the closed loop gain. The zero (Z1) occurs at the intersection of the -100dB/decade and -80dB/decade slopes. The point X in the figure should be at closed loop gain plus 20dB gain margin. The value for capacitor C2 is determined by Equation 7. Setting the 1 C2 = ---------------------------------2 R1 P 1 where R2>>R1 This indicates that the separation of the pole and the zero is governed by the closed loop gain. It is required that the zero falls on the steep slope (-100dB/decade) of the loop gain plot so that there is some gain higher than 0dB (typically 20dB) at the hand-over frequency [Eq. 7] pole of the filter to P1 = 1MHz works very well and is independent of gain. As the closed loop gain is changed, the zero location is also modified if R1 remains fixed. Capacitor C2 can be increased in value to limit the amplifier’s rising noise above 2kHz. |T| (Log gain) -100 dB/dec z1 p1 -80 dB/dec X Margin B Desired Closed Loop Gain -20 dB/dec 50kHz 1MHz 5MHz FREQUENCY Figure 16. Loop Gain Plot: Unity Gain and with Pole-zero Compensation 10 DS490F10 CS3002 3.2.2 Gain Calculation Recommendations Condition 1: |Av| 50 and R1 100 The op amp is inherently stable for |Av| 50 and R1 100. Capacitor C2 is not required for compensation across resistor R2. 1) |Av| = 1 configuration has 70° phase margin and 20dB gain margin. To simplify the calculation, set the pole of the filter to P1 = 1MHz. Pole P1 must be set higher than the op amp’s internal 50kHz crossover frequency. 2) Calculate a second value for C2 using Equation 10: R1 C in C2 --------------------------R2 [Eq. 10] where Cin = 50pF 2) |Av| = 50 configuration has phase margin between 40° for CLOAD 100 pF and 60° for CLOAD 0pF. 3) Use the larger of the two values calculated in steps 1 and 2. Condition 2: |Av| 50 and R1 100 Verify the Op Amp Compensation: Compensation capacitor C2 across resistor R2 is required. Calculate C2 using Equation 8: Verify the op amp compensation using the open-loop gain and phase response Bode plot in Figure 13. Plot the calculated closed loop gain transfer function and verify the following design criteria are met: R1 C in C2 --------------------------R2 [Eq. 8] 1) Pole P1 > op amp internal 50kHz crossover frequency where Cin = 50pF 1 P 1 = ----------------------------------------------2 R1 R2 C2 Condition 3: |Av| 50 Compensation capacitor C2 across resistor R2 is required. Calculate and verify a value for C2 using the following steps. Calculate the Compensation Capacitor Value: 1) Calculate a value for C2 using Equation 9: 1 C2 = -------------------------------------------------- 2 R1 R2 P 1 where P1 = 1MHz DS490F10 [Eq. 9] [Eq. 11] where P1 = 1MHz To simplify the calculation, set the pole to P1 = 1MHz. 2) Z1 < op amp internal 50kHz crossover frequency 1 Z 1 = ---------------------------------2 R2 C2 [Eq. 12] 3) Gain margin above the open-loop gain transfer function is required. A gain margin of +20dB above the open-loop gain transfer function is optimal. 11 CS3002 CS3002 R2 64.9k C2 0.015F R1 100 Figure 17. Thermopile Amplifier with a Gain of 650V/V 3.3 Applications The CS3002 amplifiers are optimum for applications that require high gain and low drift. Figure 17 illustrates a thermopile amplifier with a gain of 650V/V. The thermopile outputs only a few millivolts when subjected to infrared radiation. The amplifier is compensated and bandlimited by capacitor C2 in combination with resistor R2. Figure 18, on page 12 illustrates a load cell bridge amplifier with a gain of 768V/V. The load cell is excited with +5V and has a 1mV/V sensitivity. Its full scale output signal is amplified to produce a fully differential 3.8V into the CS5510/12 A/D converter. This circuit operates from +5V. +5 V +5 V VA 0.1 F + x768 V+ VREF 350 CS 100 SDO SCLK AIN+ CS3002 1 mV/V - +5 V 140 k 0.22 F 365 0.047 F 140 k 0.22 F C CS5510/12 + - AIN1 CS3002 + Counter/Timer 100 V- SCLK = 10 kHz to 100 (32.768 SCLK = 10 kHz to 100 kHz (32.768 nominal) Figure 18. Load Cell Bridge Amplifier and A/D Converter 12 DS490F10 CS3002 4. PACKAGE DRAWING 8L SOIC (150 MIL BODY) PACKAGE DRAWING E H 1 b c D SEATING PLANE A L e A1 INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 0° 8° 0° 8° JEDEC #: MS-012 5. ORDERING INFORMATION Model Container CS3002-ISZ (lead free) Bulk CS3002-ISZR (lead free) Tape & Reel 6. ENVIRONMENTAL, MANUFACTURING, Model Number CS3002-ISZ (lead free) Temperature Package -40 to +85 °C 8-pin SOIC (Lead Free) & HANDLING INFORMATION Peak Reflow Temp MSL Rating* Max Floor Life 260 °C 2 365 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS490F10 13 CS3002 7. REVISION HISTORY Revision Date Changes F3 OCT 2004 Added lead-free device ordering information. F4 AUG 2005 Added MSL specifications. Updated legal notice. Added leaded (Pb) devices. F5 AUG 2006 Updated Typical Performance Plots. F6 SEP 2006 Corrected error in Ordering Information section. F7 NOV 2007 Added additional information regarding open-loop and gain stability compensation. F8 OCT 2008 Minor, cosmetic correction to caption for Figure 10. F9 JUL 2009 Removed lead-containing devices from ordering information. F10 DEC 2012 Removed CS3001 and corrected typographical errors. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 14 DS490F10

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