CS4391A Evaluation Board Data Sheet

CDB4391A
Evaluation Board for CS4391A
Features
Description
z Demonstrates
The CDB4391A evaluation board is an excellent means
for quickly evaluating the CS4391A 24-bit, stereo D/A
converter. Evaluation requires an analog signal
analyzer, a digital signal source, a PC for controlling the
CS4391A (for control port mode only) and a power
supply. Analog line level outputs are provided via RCA
phono jacks.
recommended layout and
grounding arrangements
z CS8414 receives AES/EBU, S/PDIF, &
EIAJ-340 compatible digital audio
z Digital and analog patch areas
z Requires only a digital signal source and
power supplies for a complete Digital-toAnalog (D/A) converter system
The CS8414 digital audio receiver IC provides the system timing necessary to operate the D/A converter and
will accept AES/EBU, S/PDIF, and EIAJ-340 compatible
audio data. The evaluation board may also be configured to accept external timing and data signals for
operation in a user application during system
development.
ORDERING INFORMATION
CDB4391A
Evaluation Board
I/O for
Clocks
and Data
Control
Port
Channel A
Output and Mute
CS8414
Digital
Audio
Interface
CS4391A
Channel B
Output and Mute
www.cirrus.com
Copyright  Cirrus Logic, Inc. 2003
(All Rights Reserved)
MAY ‘03
DS600DB1
1
CDB4391A
TABLE OF CONTENTS
1. CDB4391A SYSTEM OVERVIEW ............................................................................................ 4
2. CS4391A DIGITAL TO ANALOG CONVERTER ..................................................................... 4
3. CS8414 DIGITAL AUDIO RECEIVER ...................................................................................... 4
4. CS8414 DATA FORMAT .......................................................................................................... 4
5. INPUT/OUTPUT FOR CLOCKS AND DATA ........................................................................... 5
6. POWER SUPPLY CIRCUITRY ................................................................................................. 5
7. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 5
8. CONTROL PORT SOFTWARE ................................................................................................ 5
9. DSD OPERATION .................................................................................................................... 6
10. PACKING LIST FOR CDB4391A ......................................................................................... 22
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow .......................................................................... 9
Figure 2. CS4391A and Level Shift ............................................................................................... 10
Figure 3. Channel B Audio Output and Mute Circuit ..................................................................... 11
Figure 4. Channel A Audio Output and Mute Circuit ..................................................................... 12
Figure 5. CS8414 Digital Audio Receiver...................................................................................... 13
Figure 6. Digital Audio Inputs ........................................................................................................ 14
Figure 7. Reset Circuit................................................................................................................... 15
Figure 8. Control Port Interface ..................................................................................................... 16
Figure 9. I/O for Clocks and Data.................................................................................................. 17
Figure 10. Power Supply ............................................................................................................... 18
Figure 11. Silkscreen Top ............................................................................................................. 19
Figure 12. Top Side....................................................................................................................... 20
Figure 13. Bottom Side.................................................................................................................. 21
LIST OF TABLES
Table 1. CS8414 Supported Formats.............................................................................................. 5
Table 2. System Connections ......................................................................................................... 6
Table 3. CDB4391A Jumper and Switch settings - STAND-ALONE MODE................................... 7
Table 4. CDB4391A Jumper and Switch settings - CONTOL PORT MODE .................................. 8
2
DS600DB1
CDB4391A
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of
relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement
of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied
under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the
information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated
circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes,
or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED
FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS
OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE
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MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF
THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER
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ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies
conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
DS600DB1
3
CDB4391A
1. CDB4391A SYSTEM OVERVIEW
The CDB4391A evaluation board is an excellent means of quickly evaluating the CS4391A. The CS8414
digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data
through a 10-pin header for system development.
The CDB4391A schematic has been partitioned into 9 schematics shown in Figures 2 through 10. Each
partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the system diagram also includes the interconnections between the partitioned schematics.
2. CS4391A DIGITAL TO ANALOG CONVERTER
A description of the CS4391A is included in the CS4391A data sheet.
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8414 Digital Audio Receiver,
Figure 5. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock (FSYNC), deemphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital
audio interface are included in the CS8414 data sheet.
During normal operation, the CS8414 operates in the Channel Status mode where the LED's display channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8414 to decode the de-emphasis bit from the digital audio interface for control of the CS4391A de-emphasis filter,
when the CS4391A is in stand-alone mode.
When the Error Information Switch is activated, the CS8414 operates in the Error and Frequency information mode. The information displayed by the LED's can be decoded by consulting the CS8414 data sheet.
It is likely that the de-emphasis control for the CS4391A will be erroneous and produce an incorrect audio
output if the Error Information Switch is activated and the CS4391A is in the stand-alone mode with internal serial clock mode selected.
Encoded sample frequency information can be displayed provided a proper clock is being applied to the
FCK pin of the CS8414. When an LED is lit, this indicates a "1" on the corresponding pin located on the
CS8414. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L nor R option of
CSLR/FCK should be selected if the FCK pin is being driven by a clock signal.
The evaluation board has been designed such that the input can be either optical or coax, see Figure 6.
However, both inputs cannot be driven simultaneously.
4
DS600DB1
CDB4391A
4. CS8414 DATA FORMAT
The CS8414 data format can be set with switches M0, M1, M2, and M3, as described in the CS8414 data
sheet. The format selected must be compatible with the data format of the CS4391A, as shown in the
CS4391A data sheet. Please note that the CS8414 does not support all the possible modes of the CS4391A
and the Left-Justified Format for the CS8414 and the CS4391A have incompatible serial clocks, see
Table 1. The default settings for M0-M3 on the evaluation board are given in Tables 3-4.
CS4391A CP
Mode Format
0
1
2
3
4
5
CS4391A SA
Mode Format
0
1
2
3
-
CS8414
Format
Unsupported
2
5
Unsupported
Unsupported
6
Table 1. CS8414 Supported Formats
5. INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, J9.
This header allows the evaluation board to accept externally generated clocks and data. The schematic for
the clock/data I/O is shown in Figure 9. The 74HC243 transceiver functions as an I/O buffer where HRD1
through HRD6 determine if the transceiver operates as a transmitter or receiver. A transmit function is implemented with all jumpers, HRD1 through HDR6 in the 8414 position. LRCK, SDATA, and SCLK from
the CS8414 will be outputs on J9. The transceiver operates as a receiver with HRD1 through HDR6 in the
EXT_CLK position. MCLK, LRCK, SDATA and SCLK on J9 become inputs.
6. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by six binding posts (GND, +5V(J6), +5V(J1), VL, VCC and
VEE), see Figure 10. The +5V(J6) input supplies power to the +5 volt digital circuitry (V+5, VD+5, VDPC+5), while the VL input supplies power to the Voltage Level Converters and the CS4391A VL pin.
+5V(J1) supplies power to the CS4391A. VCC and VEE supply power to the op-amp and can be +/-9 to
+/-12 volts.
WARNING: Refer to the CS4391A data sheet for maximum allowable voltages levels. Operation outside
of this range can cause permanent damage to the device.
7. GROUNDING AND POWER SUPPLY DECOUPLING
The CS4391A requires careful attention to power supply and grounding arrangements to optimize performance. Figure 10 details the power distribution used on this board. The decoupling capacitors are located
as close to the CS4391A as possible. Extensive use of ground plane fill in the evaluation board yields large
reductions in radiated noise.
DS600DB1
5
CDB4391A
8. CONTROL PORT SOFTWARE
The CDB4391A is shipped with Windows based software for interfacing with the CS4391A control port
via the DB25 connector, P1. The software can be used to communicate with the CS4391A in either SPI
or I2C mode; however, in SPI mode the CS4391A registers are write-only. Note: The CDB4391A must
be configured for control port mode as shown in Table 4.
Further documentation for the software is available on the distribution diskette. The documentation is
available in the plain text format file, README.TXT.
9. DSD OPERATION
The CDB4391A supports Direct Stream Digital (DSD) operation through the header for external clocks
and data, J9. The CS4391A must be placed into the DSD mode and the jumpers HDR1 through HDR6 must
be placed into the external clock positions.
CONNECTOR
INPUT/OUTPUT
SIGNAL PRESENT
+5V (J6)
Input
+ 5 Volt power
+5V (J1)
Input
+ 4.75 to + 5.25 Volt power for the CS4391A
VL
Input
+ 1.8 to +5.5 digital interface voltage (Note that VL should not
exceed the voltage applied to the +5V J1 terminal)
VEE
Input
-12 to -9V negative supply for the op-amp
VCC
Input
+9 to +12V positive supply for the op-amp
GND
Input
Ground connection from power supply
Coax Input
Input
Digital audio interface input via coax
Optical Input
Input
J9
Input/Output
I/O for master, serial, left/right clocks and serial data
Digital audio interface input via optical
Parallel Port
Input/Output
Parallel connection to PC for SPI / I2C control port signals
HDR9
Input/Output
I/O for SPI / I2C control port signals
AOUTA
Output
Channel A line level analog output
AOUTB
Output
Channel B line level analog output
Table 2. System Connections
6
DS600DB1
CDB4391A
JUMPER /
SWITCH
PURPOSE
POSITION
FUNCTION SELECTED
SW1 - M0
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 - M1
CS8414 mode selection
*HI
See CS8414 datasheet for details
SW1 - M2
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 - M3
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 CSLR/FCK
Selects channel for CS8414
channel status information
*LO
See CS8414 datasheet for details
HDR8
External mute for AOUTA
*ON
OFF
Mute Enabled
Mute Disabled
HDR7
External mute for AOUTB
*ON
OFF
Mute Enabled
Mute Disabled
ENCTRL
Enables / Disables parallel port
ENABLE
*DISABLE
Invalid for Stand-Alone Mode
Disables parallel port
M0/AD0/CS
CS4391A Mode Selection
*HI
LO
See CS4391A data sheet for details
M1/SDA/CDIN
CS4391A Mode Selection
HI
*LO
See CS4391A data sheet for details
M2/SCL/CCLK
CS4391A Mode Selection
GND
HI
*DEM
See CS4391A data sheet for details
Allows the CS8414 to control de-emphasis
M3
CS4391A Mode Selection
HI
*LO
See CS4391A data sheet for details
HDR1 to HDR6
Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes source
Table 3. CDB4391A Jumper and Switch settings - STAND-ALONE MODE
*Settings for Stand-Alone mode
Notes:
DS600DB1
The CDB4391A evaluation board is shipped from the factory configured for Control Port mode.
7
CDB4391A
JUMPER
PURPOSE
POSITION
FUNCTION SELECTED
SW1 - M0
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 - M1
CS8414 mode selection
*HI
See CS8414 datasheet for details
SW1 - M2
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 - M3
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 CSLR/FCK
Selects channel for CS8414
channel status information
*LO
See CS8414 datasheet for details
HDR8
External mute for AOUTA
*ON
OFF
Mute Enabled
Mute Disabled
HDR7
External mute for AOUTB
*ON
OFF
Mute Enabled
Mute Disabled
ENCTRL
Enables / Disables parallel port
*ENABLE
DISABLE
Enables parallel port
Invalid for Control Port mode
M0/AD0/CS
AD0/CS
*HI
LO
“Don’t Care” for Control Port mode
M1/SDA/CDIN
SDA/CDIN Pull-Up
*HI
LO
SDA/CDIN pulled high
Invalid for Control Port mode
M2/SCL/CCLK
SCL/CCLK Pull-Up
GND
*HI
DEM
Invalid for Control Port mode
SCL/CCLK pulled high
Invalid for Control Port mode
M3
Not Functional
HI
*LO
Must be low for Control Port mode
HDR1 to HDR6
Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes source
Table 4. CDB4391A Jumper and Switch settings - CONTOL PORT MODE
*Settings for Control Port mode
Notes:
8
The CDB4391A evaluation board is shipped from the factory configured for Control Port mode.
DS600DB1
DS600DB1
Fig 6
Digital
Audio
Inputs
Fig 5
CS8414
Digital
Audio
RXP
Receiver
Connections
RXN
MCLK
LRCK
SCLK
SDATA
Reset
Circuit
Fig 7
CS4391A
Fig 2
Figure 1. System Block Diagram and Signal Flow
I/O for
Clocks
and Data
Fig 9
Control
Port
Interface
Fig 8
Channel B
Outputs
and Mute
Circuit
Fig 3
Channel A
Outputs
and Mute
Circuit
Fig 4
CDB4391A
9
10
.1UF
GND
RST
MCLK
M3
LRCK
SCLK
SDATA
8414_DEM
C61
VL
GND
.1UF
C59
VL
GND
GND
1
2
4
5
13
12
10
9
1
2
4
5
13
12
10
9
GND
O3
O2
O1
O0
VCC
U6
GND
O3
O2
O1
O0
VCC
74VHC125M
/A0
B0
/A1
B1
/A2
B2
/A3
B3
74VHC125M
/A0
B0
/A1
B1
/A2
B2
/A3
B3
U9
6
3
6
3
7
8
7
11
GND
GND
11
14
8
14
DEM
VL
GND
M0
M1
M2
M3
MCLK
LRCK
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
U7
CS4391
\RST
VL
SDATA/DSD_A
SCLK/DSD_B
LRCK/DSDMODE
MCLK
(DSD_CLK)M3
(SCL/CCLK)M2
(SDA/CDIN)M1
(AD0/\CS\)M0
Figure 2. CS4391A and Level Shift
M0/AD0/CS
M1/SDA/CS
M2/SCL/CCLK
49.9
R41
R10
499
R13
499
R14
499
.1UF
X7R
C54
AMUTEC
AOUTAAOUTA+
VA
AGND
AOUTB+
AOUTBBMUTEC
CMOUT
FILT+
20
19
18
17
16
15
14
13
12
11
1UF
C20
.1UF
X7R
C34
AOUTB+
AOUTBBMUTEC
AMUTEC
AOUTAAOUTA+
GND
1UF
C21
.1UF
X7R
C17
GND
1UF
C40
FERRITE_BEAD
L1
VA+5
CDB4391A
DS600DB1
DS600DB1
AOUTB+
AOUTB-
BMUTEC
AOUTB+
AOUTB-
C39
C41
BMUTEC
10UF R33
10UF R34
1
5.62K
5.62K
GND
Q2
MMUN2211LT1
need cog
R31
5.62K
R32
R29
1
1.18K
1.18K
GND
+
-
3
2
VA+5
560PF
COG
C22
5
6
C18
R36
MMUN2111LT1
Q6
MC33078D
7
560PF
COG
U11
5.62K
2K
Figure 3. Channel B Audio Output and Mute Circuit
GND
2
3
GND
2700PF
COG
C28
GND
2700PF
COG
R35
R19
560
3
Q5
2SC2878
1
2
GND
HDR1X2
HDR7
1
2
C4
GND
R4
47K
GND
2
1
3
4 NC
J4
CON_RCA_RA
AOUTB
CDB4391A
11
12
AOUTA+
AOUTA-
AOUTA+
AOUTA-
C43
C42
AMUTEC
10UF
10UF
1
5.62K
5.62K
GND
2
3
GND
R15
5.62K
Q4
MMUN2211LT1
GND
2700PF
COG
C14
R18
R17
1
1.18K
1.18K
GND
3
2
4
.1UF
C49
GND
.1UF
C48
MC33078D
1
U11 GND
560PF
COG
R25
MMUN2111LT1
Q3
VEE
V-
+
-
V+
VA+5
560PF
COG
C5
3
2
8
VCC
C6
5.62K
Figure 4. Channel A Audio Output and Mute Circuit
AMUTEC
R26
R24
GND
2700PF
COG
R28
2K
R20
560
3
Q1
2SC2878
1
2
GND
HDR1X2
HDR8
1
2
C7
GND
R5
47K
GND
2
1
3
4 NC
J3
CON_RCA_RA
AOUTA
CDB4391A
DS600DB1
DS600DB1
RN3
560
U8
7
GND
GND
13
D2
12
LED_RECT
9
5
3
11
8
6
4
1
D4
10
LED_RECT
LED_RECT
D6
D5
LED_RECT
LED_RECT
D3
2
GND
RXP
RXN
1UF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CS8414
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDATA
HDR1X3
HDR1
LRCK
HDR1X3
HDR2
VERF
C
CE/F2
CD/F1
SDATA
CC/F0
ERF
CB/E2
M1
CA/E1
M0
/C0/E0
VA+
VD+
AGND
DGND
FILT
RXP
RXN
MCK
FSYNC
M2
SCK
M3
CS12/FCK
SEL
U
CBL
U2
GND
SCLK
HDR1X3
HDR3
Figure 5. CS8414 Digital Audio Receiver
C31
.1UF
X7R
10
1
2
3
VCC
C26
R11
1
2
3
14
VD1
VA
1
2
3
SN74HC04N
D1
LED_RECT
VD+5
.1UF
GND
C1
10UF
1
2
3
8414_DEM
VD+5
C16
V+5
1
2
3
HDR1X3
HDR4
HDR1X3
HDR5
VD1
1UF
C32
C33
.1UF
X7R
ERROR & FREQ
R7
47.5K
SW_B3W_1100
S4
R9
470
C27
MCLK
RN4
47K
CSLR/FCK
CS8414_M2
.068UF
X7R
GND
VA
CS8414_M1
CS8414_M0
VD1
SW1
SW_DIP_5
5
4
3
2
1
GND
CDB4391A
13
OPEN
14
3
NC 4
CON_RCA_RA
J5
GND
2
1
R30
75
C11
DIGITAL INPUT
.01UF
RXN
TORX173
Figure 6. Digital Audio Inputs
5
6
OPT1
4
3
2
1
.01UF
C9
L4
.01UF
47UH
C10
GND
OPTICAL INPUT
VD+5
RXP
CDB4391A
DS600DB1
DS600DB1
GND
GND
Figure 7. Reset Circuit
1
RST
Vcc
100PF
C23
GND
U3
DS1233-10
VD+5
CDB4391A
3
RST
2
GND
1
15
S1
SW_B3W_1100
16
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
DB25M_RA
P1
VDPC+5
GND
RN1
1K
R38
5
RN2
GND
11
M1/SDA/CDIN
D7
12
SN74HCT125D
8
U16
SN74HCT125D
6
U16
SN74HCT125D
3
U16
10
GND
GND
13
4
GND
GND
GND
7 1
14
VDPC+5
12
SN74HCT125D
GND
EN_SCL/CCLK
SN74HCT125D
8
U15
SN74HCT125D
6
U15
SN74HCT125D
3
U15
10
GND
4
GND
7 1
GND
VCC
U16
9
5
2
11
13
GND
14
VDPC+5
VCC
U15
9
5
2
SN74HCT125D
4.7K
GND
.1UF
C62
VDPC+5
12
4.7K
13
4.7K
14
4.7K
15
4.7K
16
4.7K
11
4.7K
PC PORT
4
RN2
3
RN2
2
RN2
1
RN2
6
RN2
.1UF
C63
VDPC+5
BAT85
U1
VCC
GND
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
SN74HC574DW
1D
2D
3D
4D
5D
6D
7D
8D
/OE
CLK
GND
VDPC+5
20
10
19
18
17
16
15
14
13
12
.1UF
C47
VDPC+5
EN_SCL/CCLK
1
2
4
5
13
12
10
9
U5
GND
O3
O2
O1
O0
VCC
74VHC125M
/A0
B0
/A1
B1
/A2
B2
/A3
B3
Figure 8. Control Port Interface
RST
GND
2
3
4
5
6
7
8
9
1
11
HDR10
HDR1X3
ENABLE
1
2
3
ENCTRL
DISABLE
GND
.1UF
C46
VD+5
6
3
8
7
11
14
GND
VL
C45
GND
R6
2K
1
2
3
M0/AD0/CS
HDR1X3
HDR11
GND
.1UF
R8
2K
M2/SCL/CCLK
GND
HDR4X2
HDR9
1
2
3
4
5
6
7
8
HDR21
1
2
HDR22
1
2
HDR23
1
2
GND
HDR1X3
HDR12
1
2
3
DEM
VL
GND
M1/SDA/CDIN
R12
2K
VL
M2/SCL/CCLK
M0/AD0/CS
M1/SDA/CDIN
CDB4391A
DS600DB1
DS600DB1
8414
EXTERNAL
CLK SOURCE
HDR1X3
HDR6
VD+5
GND
HDR5X2
J9
2
1
4
3
6
5
8
7
10
9
DIGITAL I/O
(DSD_CLK)M3
SDATA
LRCK
SCLK
MCLK
GND
1
2
3
3
4
5
6
1
13
3
4
5
6
1
13
VCC
GND
B1
B2
B3
B4
VCC
GND
B1
B2
B3
B4
14
7
11
10
9
8
14
7
11
10
9
8
VD+5
SDATA
LRCK
SCLK
MCLK
VD+5
GND
.1UF
C35
GND
.1UF
C24
Figure 9. I/O for Clocks and Data
SN74HC243N
A1
A2
A3
A4
G1
G2
U10
SN74HC243N
A1
A2
A3
A4
G1
G2
RN5
47K
M3
VD+5
0
GND
R1
U4
M3
HDR1X3
HDR14
1
2
3
CDB4391A
17
18
GND
VDPC+5
.1UF
10UF
C19
C8
L2
V+5
VD+5
FB
L3
FB
.1UF
C13
47UF
C25
GND
C3
VA+5
GND
J11
.1UF
Figure 10. Power Supply
C57
C29
47UF
Z5
P6KE6V8P
J1
VL
CON_BANANA
+5V
CON_BANANA
.1UF
Z2
C2
47UF
C12
47UF
P6KE6V8P
P6KE6V8P
GND
J7
J6
Z1
GND
CON_BANANA
+5V
CON_BANANA
VL
VCC
VCC
C30
47UF
Z3
C37
J8
CON_BANANA
.1UF
P6KE13
GND
Z4
C38
.1UF
C36
47UF
P6KE13
VEE
VEE
J10
CON_BANANA
CDB4391A
DS600DB1
CDB4391A
Figure 11. Silkscreen Top
DS600DB1
19
CDB4391A
Figure 12. Top Side
20
DS600DB1
CDB4391A
Figure 13. Bottom Side
DS600DB1
21
CDB4391A
10. PACKING LIST FOR CDB4391A
Inspect the Contents of the package and confirm that the following contents are included:
1) CDB4391A
2) CDB4391A data sheet
3) CS4391A data sheet
4) 3.5 inch floppy disk with the Windows based CDB4391A Graphical User Interface
5) 25-pin RS-232 cable
Item
Revision
CDB4391A
B
CS4391A-KZ
B
CDB4391A data sheet
DS600DB1
CS4391A Data sheet
DS600PP2
3.5 inch floppy disk with windows based
graphical user interface
1.0
25-pin RS-232 cable
22
DS600DB1
• Notes •
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