Data Sheet

VIV0102THJ
®
US
C
S
C
NRTL
US
VTM
Transformer
TM
FEATURES
• 48 Vdc to 1.5 Vdc 50 A transformer
- Operating from standard 48 V or 24 V PRMTM regulators
• High efficiency (>89%) reduces system power
consumption
• High density (334 A/in3)
• “Half Chip” V• I Chip package enables surface mount,
low impedance interconnect to system board
• Contains built-in protection features:
-
Overvoltage Lockout
Overcurrent
Short Circuit
Over Temperature
Reverse Inrush Protection
• Provides enable / disable control, internal temperature
monitoring, current monitoring
• ZVS / ZCS resonant Sine Amplitude Converter topology
• Less than 50ºC temperature rise at full load
in typical applications
TYPICAL APPLICATIONS
• High End Computing Systems
• Automated Test Equipment
• High Density Power Supplies
• Communications Systems
•0
DESCRIPTION
The V• I ChipTM transformer is a high efficiency (>89%) Sine
Amplitude ConverterTM (SACTM) operating from a 26 to 55 Vdc
primary bus to deliver an isolated output. The Sine Amplitude
Converter offers a low AC impedance beyond the bandwidth of
most downstream regulators, which means that capacitance
normally at the load can be located at the input to the Sine
Amplitude Converter. Since the K factor of the VIV0102THJ is
1/32, that capacitance value can be reduced by a factor of
1024, resulting in savings of board area, materials and total
system cost.
The VIV0102THJ is provided in a V• I Chip package compatible
with standard pick-and-place and surface mount assembly
processes. The co-molded V•I Chip package provides enhanced
thermal management due to large thermal interface area and
superior thermal conductivity. With high conversion efficiency
the VIV0102THJ increases overall system efficiency and lowers
operating costs compared to conventional approaches.
The VIV0102THJ enables the utilization of Factorized Power
ArchitectureTM providing efficiency and size benefits by lowering
conversion and distribution losses and promoting high density
point of load conversion.
VIN = 26 to 55 V
IOUT = 50 A (NOM)
VOUT = 0.8 to 1.7 V (NO LOAD)
K= 1/32
PART NUMBER
DESCRIPTION
VIV0102THJ
-40°C to 125°C TJ
VIV0102MHJ
-55°C TO 125°C TJ
Regulator
VC
SG
OS
CD
PR
PC
TM
IL
Voltage Transformer
PC
IM
VC
TM
VTM
PRM
+In
+Out
-In
-Out
+In
+Out
-In
-Out
VIN
L
O
A
D
Factorized Power Architecture
(See Application Note AN:024)
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.9
02/2010
Page 1 of 16
v i c o r p o w e r. c o m
VIV0102THJ
PRELIMINARY DATASHEET
1.0 ABSOLUTE MAXIMUM VOLTAGE RATINGS
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent
damage to the device.
MIN
MAX
UNIT
MIN
MAX
UNIT
+ IN to - IN . . . . . . . . . . . . . . . . . . . . . . .
-1
60
VDC
IM to - IN.................................................
PC to - IN . . . . . . . . . . . . . . . . . . . . . . . .
-0.3
20
VDC
+ IN / - IN to + OUT / - OUT (hipot)........
TM to -IN . . . . . . . . . . . . . . . . . . . . . . . .
-0.3
7
VDC
+ IN / - IN to + OUT / - OUT (working)...
VC to - IN . . . . . . . . . . . . . . . . . . . . . . . .
-0.3
20
VDC
+ OUT to - OUT.......................................
0
-1
3.15
VDC
2250
VDC
60
VDC
4
VDC
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25ºC unless otherwise noted.
ATTRIBUTE
SYMBOL
Input Voltage Range
VIN
VIN Slew Rate
dVIN /dt
VIN UV Turn Off
VIN_UV
CONDITIONS / NOTES
No external VC applied
VC applied
No Load Power Dissipation
PNL
Inrush Current Peak
IINRP
Module latched shutdown,
No external VC applied, IOUT = 50A
VIN = 42 V
VIN = 26 V to 55 V
VIN = 42 V, TC = 25ºC
VIN = 26 V to 55 V, TC = 25ºC
VC enable, VIN = 42 V COUT = 5000 µF,
RLOAD = 28 mΩ
IIN_DC
K
VOUT
K = VOUT / VIN, IOUT = 0 A
VOUT = VIN • K - IOUT • ROUT, Section 11
DC Input Current
Transfer Ratio
Output Voltage
Output Current (Average)
Output Current (Peak)
Output Power (Average)
IOUT_AVG
IOUT_PK
POUT_AVG
ηAMB
Efficiency (Ambient)
ηHOT
η20%
Efficiency (Hot)
Efficiency (Over Load Range)
Output Resistance (Cold)
Output Resistance (Ambient)
Output Resistance (Hot)
Switching Frequency
Output Ripple Frequency
ROUT_COLD
ROUT_AMB
ROUT_HOT
FSW
FSW_RP
Output Voltage Ripple
VOUT_PP
Output Inductance (Parasitic)
LOUT_PAR
Output Capacitance (Internal)
COUT_INT
Output Capacitance (External)
COUT_EXT
PROTECTION
OVLO
Overvoltage Lockout
Response Time
Output Overcurrent Trip
Short Circuit Protection Trip Current
Output Overcurrent Response
Time Constant
Short Circuit Protection Response Time
Thermal Shutdown Setpoint
TPEAK < 10 ms, IOUT_AVG ≤ 50 A
IOUT_AVG ≤ 50 A
VIN = 42 V, IOUT = 50 A
VIN = 26 V to 55 V, IOUT = 50 A
VIN = 42 V, IOUT = 25 A
VIN = 42 V, TC = 100°C, IOUT = 50 A
10 A < IOUT < 50 A
TC = -40°C, IOUT = 50 A
TC = 25°C, IOUT = 50 A
TC = 100°C, IOUT = 50 A
MIN
16.2
1.2
2.6
2.5
Module latched shutdown
TOVLO
Effective internal RC filter
IOCP
ISCP
MAX
V/µs
26
V
5
7.1
3.5
4.8
W
10
A
1.8
A
V/V
V
A
A
W
50
75
80
87.2
83.0
86.3
87.0
70.0
1.2
1.5
1.9
1.30
2.60
55.5
VDC
88.6
%
88.0
88.3
1.3
1.7
2.1
1.45
2.90
1.5
1.9
2.3
1.60
3.20
%
%
mΩ
mΩ
mΩ
MHz
MHz
155
300
mV
600
pH
130
µF
57.7
5000
µF
59.8
V
2.4
60
75
UNIT
55
55
1
1/32
COUT = 0 F, IOUT = 50 A, VIN = 42 V,
20 MHz BW, Section 12
Frequency up to 30 MHz,
Simulated J-lead model
VOUT = 1.5 V
VTM Standalone Operation
VIN pre-applied, VC enable
VIN_OVLO+
TYP
26
0
75
µs
100
A
A
TOCP
Effective internal RC filter (Integrative).
8
ms
TSCP
From detection to cessation
of switching (Instantaneous)
1
µs
TJ_OTP
125
130
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
135
ºC
Rev. 1.9
02/2010
Page 2 of 16
v i c o r p o w e r. c o m
VIV0102THJ
PRELIMINARY DATASHEET
3.0 SIGNAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25°C unless otherwise noted.
• Used to wake up powertrain circuit.
• A minimum of 12 V must be applied indefinitely for VIN < 26 V
to ensure normal operation.
• VC slew rate must be within range for a succesful start.
SIGNAL TYPE
STATE
Steady
VTM CONTROL : VC
• PRM VC can be used as valid wake-up signal source.
• VC voltage may be continuously applied;
there will be minimal VC current drawn when VIN > 26 V and VC < 13.
• Internal resistance used in adaptive loop compensation
ATTRIBUTE
SYMBOL
External VC Voltage
VVC_EXT
VC Current Draw Threshold
VVC_TH
VC Current Draw
IVC
VC Internal Resistor
RVC-INT
VC Slew Rate
dVC/dt
VC Inrush Current
CONDITIONS / NOTES
Required for startup, and operation
below 26 V. See Section 7.
Low VC current draw for VIN >26 V
VC = 13 V, VIN = 0 V
VC = 13 V, VIN > 26 V
VC = 16.5 V, VIN > 26 V
TYP
12
MAX UNIT
16.5
13
90
6
90
11
V
150
mA
kΩ
V/µs
IINR_VC
VC = 16.5 V, dVC/dt = 0.25 V/µs
750
VIN pre-applied, PC floating, VC enable
500
CPC = 0 µF, COUT = 5000 µF
Transitional
VC = 12 V to PC high, VIN = 0 V,
10
25
VC to PC Delay
TVC_PC
dVC/dt = 0.25 V/µs
Internal VC Capacitance
CVC_INT
VC = 0 V
2.2
PRIMARY CONTROL : PC
• The PC pin enables and disables the VTM.
• Module will shutdown when pulled low with an impedance
When held below 2 V, the VTM will be disabled.
less than 400 Ω.
• PC pin outputs 5 V during normal operation. PC pin is equal to 2.5 V
• In an array of VTMs, connect PC pin to synchronize startup.
during fault mode given VIN > 26 V and VC > 12 V.
• PC pin cannot sink current and will not disable other module
• After successful start-up and under no fault condition, PC can be used as
during fault mode.
a 5 V regulated voltage source with a 2 mA maximum current.
mA
TON
µs
Start Up
VC Output Turn-On Delay
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
0.02
V
0.25
ANALOG
INPUT
Required for proper startup;
MIN
MIN
TYP
PC Voltage
VPC
4.7
5.0
5.3
PC Source Current
IPC_OP
2
ANALOG
PC Resistance (Internal)
RPC_INT
Internal pull down resistor
50
150
400
OUTPUT
PC Source Current
IPC_EN
50
100
300
Start Up
PC Capacitance (Internal)
CPC_INT
Section 7
50
PC Resistance (External)
RPC_EXT
60
PC Voltage (Enable)
VPC_EN
2
2.5
3
Enable
PC Voltage (Disable)
VPC_DIS
2
Disable
DIGITAL
PC Pull Down Current
IPC_PD
5.1
INPUT / OUPUT
PC Disable Time
TPC_DIS_T
4
Transitional
PC Fault Response Time
TFR_PC
From fault to PC = 2 V
100
TEMPERATURE MONITOR : TM
• The TM pin monitors the internal temperature of the VTM controller IC
• The TM pin has a room temperature setpoint of 3 V (@27°C)
within an accuracy of ±5°C.
and approximate gain of 10 mV/°C.
• Can be used as a "Power Good" flag to verify that the VTM is operating.
STATE
ANALOG
OUTPUT
Steady
Disable
DIGITAL OUTPUT
(FAULT FLAG)
Transitional
ATTRIBUTE
TM Voltage
TM Source Current
TM Gain
SYMBOL
VTM_AMB
ITM
ATM
TM Voltage Ripple
VTM_PP
TM Voltage
TM Resistance (Internal)
TM Capacitance (External)
TM Fault Response Time
VTM_DIS
RTM_INT
CTM_EXT
TFR_TM
CONDITIONS / NOTES
TJ controller = 27°C
TYP
MAX UNIT
2.95
3.00
3.05
100
V
µA
mV/°C
200
mV
50
50
V
kΩ
pF
µs
10
From fault to TM = 1.5 V
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
V
mA
kΩ
µA
pF
kΩ
V
V
mA
µs
µs
MIN
CTM = 0 F, VIN = 42 V,
IOUT = 50 A
Internal pull down resistor
µF
MAX UNIT
Steady
SIGNAL TYPE
µs
120
25
0
40
10
Rev. 1.9
02/2010
Page 3 of 16
v i c o r p o w e r. c o m
VIV0102THJ
PRELIMINARY DATASHEET
3.0 SIGNAL CHARACTERISTICS (CONT.)
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25°C unless otherwise noted.
CURRENT MONITOR : IM
• The nominal IM pin voltage varies between 0.39 V and 1.86 V
representing the output current within ±25% under all operating line
temperature conditions between 50% and 100%.
SIGNAL TYPE
STATE
ANALOG
OUTPUT
ATTRIBUTE
IM Voltage (No Load)
IM Voltage (50%)
IM Voltage (Full Load)
IM Gain
IM Resistance (External)
Steady
• The IM pin provides a DC analog voltage proportional to
the output current of the VTM.
SYMBOL
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
VIM_NL
VIM_50%
VIM_FL
A IM
RIM_EXT
TC = 25ºC, VIN = 42 V, IOUT = 0 A
TC = 25ºC, VIN = 42 V, IOUT = 25 A
TC = 25ºC, VIN = 42 V, IOUT = 50 A
TC = 25ºC, VIN = 42 V, IOUT > 25 A
0.25
0.39
0.98
1.86
35.2
0.49
V
V
V
mV/A
MΩ
2.5
4.0 TIMING DIAGRAM
IOUT
6
7
ISSP
IOCP
1
2 3
VC
4
8
d
5
b
VVC-EXT
a
VOVLO
VIN
NL
≥ 26 V
c
e
f
VOUT
TM
VTM-AMB
PC
g
5V
3V
a: VC slew rate (dVC/dt)
b: Minimum VC pulse rate
c: TOVLO
d: TOCP
e: Output turn on delay (TON)
f: PC disable time (TPC-DIS)
g: VC to PC delay (TVC-PC)
1. Initiated VC pulse
2. Controller start
3. VIN ramp up
4. VIN = VOVLO
5. VIN ramp down no VC pulse
6. Overcurrent
7. Start up on short circuit
8. PC driven low
Notes:
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
– Timing and voltage is not to scale
– Error pulse width is load dependent
Rev. 1.9
02/2010
Page 4 of 16
v i c o r p o w e r. c o m
VIV0102THJ
5.0 APPLICATION CHARACTERISTICS
The following values, typical of an application environment, are collected at TC = 25ºC unless otherwise noted. See associated figures
for general trend data.
ATTRIBUTE
SYMBOL
No Load Power Dissipation
Efficiency (Ambient)
Efficiency (Hot)
Output Resistance (Ambient)
Output Resistance (Hot)
Output Resistance (Cold)
PNL
ηAMB
ηHOT
ROUT_AMB
ROUT_HOT
ROUT_COLD
Output Voltage Ripple
VOUT_PP
VOUT Transient (Positive)
VOUT_TRAN+
VOUT Transient (Negative)
VOUT_TRAN-
CONDITIONS / NOTES
TYP
UNIT
VIN = 42 V
VIN = 42 V, IOUT = 50 A
VIN = 42 V, IOUT = 50 A, TC = 100ºC
VIN = 42 V, IOUT = 50 A
VIN = 42 V, IOUT = 50 A, TC = 100ºC
VIN = 42 V, IOUT = 50 A, TC = -40ºC
COUT = 0 F, IOUT = 50 A, VIN = 42 V,
20 MHz BW, Section 12
IOUT_STEP = 0 A TO 50A, VIN = 42 V,
ISLEW > 10 A /us
IOUT_STEP = 50 A to 0 A, VIN = 42 V
ISLEW > 10 A /us
3.1
88.6
88.0
1.7
2.1
1.3
W
%
%
mΩ
mΩ
mΩ
235
mV
20
mV
20
mV
No Load Power Dissipation vs. Line
Full Load Efficiency vs. Case Temperature
92
Full Load Efficiency (%)
6
5
4
3
2
90
88
86
84
82
1
80
26
29
32
36
39
42
45
49
52
55
-40
-20
Input Voltage (V)
TCASE :
-40ºC
25ºC
100ºC
VIN :
92
85
18
88
Efficiency (%)
16
75
14
70
12
10
PD
8
55
6
50
4
45
2
40
0
0
5
10
15
20
25
30
35
26 V
42 V
55 V
60
80
100
42 V
55 V
40
45
18
16
η
26 V
Figure 3 – Efficiency and power dissipation at –40°C
14
12
80
10
76
PD
72
8
68
6
64
4
60
2
0
56
50
0
5
10
15
20
25
30
35
40
45
50
Output Current (A)
Output Current (A)
VIN:
26 V
84
Efficiency (%)
η
Power Dissipation (W)
20
60
40
Efficiency & Power Dissipation 25°C Case
Efficiency & Power Dissipation -40°C Case
90
65
20
Figure 2 – Full load efficiency vs. temperature
Figure 1 – No load power dissipation vs. VIN
80
0
Case Temperature (°C)
Power Dissipation (W)
Power Dissipation (W)
7
42 V
55 V
VIN:
26 V
42 V
55 V
26 V
42 V
55 V
Figure 4 – Efficiency and power dissipation at 25°C
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.9
02/2010
Page 5 of 16
v i c o r p o w e r. c o m
VIV0102THJ
ROUT vs. Case Temperature at VIN = 42 V
Efficiency & Power Dissipation 100°C Case
16
14
η
84
12
10
80
76
8
PD
72
6
68
4
64
2
2
Rout (mΩ)
Efficiency (%)
88
2.5
Power Dissipation (W)
92
0
5
10
15
20
25
30
35
40
45
1.5
1
0.5
0
60
PRELIMINARY DATASHEET
-40
50
-20
Output Current (A)
26 V
VIN:
42 V
55 V
0
20
40
60
80
100
Case Temperature (°C)
26 V
42 V
I OUT :
55 V
25 A
50 A
Figure 6 – ROUT vs. temperature
Figure 5 – Efficiency and power dissipation at 100°C
Ripple vs. Load
250
IM Voltage vs. Load at VIN = 42 V
2.5
2
1.75
150
IM (V)
Ripple (mV pk-pk)
2.25
200
100
1.5
1.25
1
50
0.75
0
0.25
0.5
0
5
10
15
20
25
30
35
40
45
50
0
5
TCASE:
42 V
V IN :
Figure 7 – VRIPPLE vs. IOUT ; No external COUT.
Board mounted module, scope setting : 20 MHz analog BW
15
20
25
30
35
40
45
50
-40ºC
25ºC
100ºC
Figure 8 – IM voltage vs. load
IM Voltage vs. TCASE & Line
IM Voltage vs. Load 25°C Case
2.25
2.5
2
2.4
1.75
2.3
2.2
IM (V)
1.5
IM (V)
10
Load Current (A)
Load Current (A)
1.25
1
2.1
2
1.9
0.75
1.8
0.5
1.7
0.25
1.6
1.5
0
0
5
10
15
20
25
30
35
40
45
50
-40
-20
0
VIN :
26 V
Figure 9 – IM voltage vs. load
42 V
20
40
60
80
100
TCASE (°C)
Load Current (A)
55 V
VIN
26 V
42 V
55 V
Figure 10 – Full load IM voltage vs. TCASE
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.9
02/2010
Page 6 of 16
v i c o r p o w e r. c o m
VIV0102THJ
PRELIMINARY DATASHEET
Safe Operating Area
80
Output Current (A)
70
60
10 ms Max
50
40
Continuous
30
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Output Voltage (V)
Figure 11 – Safe operating area
Figure 12 – Full load ripple, 100 µF CIN; No external COUT.
Board mounted module, scope setting : 20 MHz analog BW
Figure 13 –Start up from application of VIN; VC pre-applied
COUT = 0 µF
Figure 14 – Start up from application of VC; VIN pre-applied
COUT = 0 µF
Figure 15 – 0 A– 50 A transient response:
CIN = 100 µF, no external COUT
Figure 16 – 50 A – 0 A transient response:
CIN = 100 µF, no external COUT
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.9
02/2010
Page 7 of 16
v i c o r p o w e r. c o m
VIV0102THJ
PRELIMINARY DATASHEET
6.0 GENERAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40ºC < TJ < 125ºC (T-Grade); All Other specifications are at TJ = 25°C unless otherwise noted.
ATTRIBUTE
SYMBOL
MECHANICAL
Length
Width
Height
Volume
Weight
Lead Finish
L
W
H
Vol
W
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
21.7 / [0.85]
16.4 / [0.64]
6.48 / [0.255]
22.0 / [0.87]
16.5 / [0.65]
6.73 / [0.265]
2.44 / [0.15]
8.0 / 0.28
22.3 / [0.88]
16.6 / [0.66]
6.98 / [0.275]
mm/[in]
mm/[in]
mm/[in]
cm3/[in3]
g/[oz]
No heat sink
Nickel
Palladium
Gold
0.51
0.02
0.003
2.03
0.15
0.051
-40
-55
125
125
°C
°C
Ws/°C
3
lbs
125
125
°C
°C
µm
THERMAL
Operating Temperature
TJ
VIV0102THJ (T-Grade)
VIV0102MHJ (M-Grade)
Thermal Capacity
5
ASSEMBLY
Peak Compressive Force
Applied to Case (Z-axis)
Supported by J-lead only
Storage Temperature
TST
ESDHBM
ESD Withstand
ESDMM
VIV0102THJ (T-Grade)
VIV0102MHJ (M-Grade)
Human Body Model,
Machine Model,
2.5
-40
-65
1500
VDC
400
SOLDERING
MSL 5
MSL 6, TOB = 4hrs
Peak Temperature During Reflow
Peak Time Above 183°C
Peak Heating Rate During Reflow
Peak Cooling Rate Post Reflow
SAFETY
Working Voltage (IN – OUT)
Isolation Voltage (hipot)
Isolation Capacitance
Isolation Resistance
MTBF
Agency Approvals / Standards
1.5
1.5
VIN_OUT
VHIPOT
CIN_OUT
RIN_OUT
Unpowered Unit
MIL HDBK 217, 25ºC,
Ground Benign
cTUVus
cURus
CE Mark
RoHS 6 of 6
2250
1350
10
1750
4.5
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
225
245
150
3
6
°C
°C
s
°C/s
°C/s
60
VDC
VDC
pF
MΩ
2150
MHrs
Rev. 1.9
02/2010
Page 8 of 16
v i c o r p o w e r. c o m
VIV0102THJ
7.0 USING THE CONTROL SIGNALS VC, PC, TM, IM
The VTM Control (VC) pin is an input pin which powers the
internal VCC circuitry when within the specified voltage range
of 12 V to 16.5 V. This voltage is required in order for the VTM
to start, and must be applied as long as the input is below
26 V. In order to ensure a proper start, the slew rate of the
applied voltage must be within the specified range.
Some additional notes on the using the VC pin:
• In most applications, the VTM will be powered by an
upstream PRM which provides a 10 ms VC pulse during
startup. In these applications the VC pins of the PRM and
VTM should be tied together.
• The VC voltage can be applied indefinitely allowing for
continuous operation down to 0 VIN.
• The fault response of the VTM is latching. A positive edge on
VC is required in order to restart the unit. If VC is
continuously applied the PC pin may be toggled to restart
the VTM.
Primary Control (PC) pin can be used to accomplish the
following functions:
• Delayed start: Upon the application of VC, the PC pin will
source a constant 100 µA current to the internal RC
network. Adding an external capacitor will allow further
delay in reaching the 2.5 V threshold for module start.
• Auxiliary voltage source: Once enabled in regular
operational conditions (no fault), each VTM PC provides a
regulated 5 V, 2 mA voltage source.
• Output disable: PC pin can be actively pulled down in order
to disable the module. Pull down impedance shall be lower
than 400 Ω.
• Fault detection flag: The PC 5 V voltage source is internally
turned off as soon as a fault is detected. It is important to
notice that PC doesn’t have current sink capability. Therefore,
in an array, PC line will not be capable of disabling
neighboring modules if a fault is detected.
• Fault reset: PC may be toggled to restart the unit if VC
is continuously applied.
Temperature Monitor (TM) pin provides a voltage
proportional to the absolute temperature of the converter
control IC.
It can be used to accomplish the following functions:
• Monitor the control IC temperature: The temperature in
Kelvin is equal to the voltage on the TM pin scaled
by 100. (i.e. 3.0 V = 300 K = 27ºC). If a heat sink is applied,
TM can be used to thermally protect the system.
• Fault detection flag: The TM voltage source is internally
turned off as soon as a fault is detected. For system
monitoring purposes (microcontroller interface) faults are
detected on falling edges of TM signal.
PRELIMINARY DATASHEET
Current Monitor (IM) pin provides a voltage proportional to
the output current of the VTM. The nominal voltage will vary
between 0.39 V and 1.86 V over the output current range of
the VTM (See Figures 8–10). The accuracy of the IM pin will be
within 25% under all line and temperature conditions between
50% and 100% load.
8.0 STARTUP BEHAVIOR
Depending on the sequencing of the VC with respect to the
input voltage, the behavior during startup will vary as follows:
• Normal Operation (VC applied prior to VIN): In this case the
controller is active prior to ramping the input. When the
input voltage is applied, the VTM output voltage will track
the input (See Figure 13). The inrush current is determined by
the input voltage rate of rise and output capacitance. If the
VC voltage is removed prior to the input reaching 26 V, the
VTM may shut down.
• Stand Alone Operation (VC applied after VIN): In this case the
VTM output will begin to rise upon the application of the VC
voltage (See Figure 14). The Adaptive Soft Start circuit
(See Section 10) may vary the ouput rate of rise in order to
limit the inrush current to it’s maximum level. When starting
into high capacitance, or a short, the output current will be
limited for a maximum of 900 µsec. After this period, the
adaptive soft start circuit will time out and the VTM
may shut down. No restart will be attempted until VC is
re-applied, or PC is toggled. The maximum output
capacitance is limited to 5000 µF in this mode of operation
to ensure a sucessful start.
9.0 THERMAL CONSIDERATIONS
V• I Chip products are multi-chip modules whose temperature
distribution varies greatly for each part number as well as with
the input / output conditions, thermal management and
environmental conditions. Maintaining the top of the
VIV0102THJ case to less than 100ºC will keep all junctions
within the V• I Chip below 125ºC for most applications.
The percent of total heat dissipated through the top surface
versus through the J-lead is entirely dependent on the
particular mechanical and thermal environment. The heat
dissipated through the top surface is typically 60%. The heat
dissipated through the J-lead onto the PCB board surface is
typically 40%. Use 100% top surface dissipation when
designing for a conservative cooling solution.
It is not recommended to use a V• I Chip for an extended
period of time at full load without proper heatsinking.
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.9
02/2010
Page 9 of 16
v i c o r p o w e r. c o m
v i c o r p o w e r. c o m
PC
-VIN
VC
+VIN
560 pF
2.5 V
Rvc
Enable
100 uA
150 K
1.5 k
2.5 V
PC Pull-Up
& Source
10.5 V
Buck
Regulator
Supply
18 V
CIN
5V
Enable
2 mA
OVLO
UVLO
VIN
Adaptive
Soft Start
Gate
Drive
Supply
Enable
Fault Logic
Enable
Modulator
Q2
Primary Current
Sensing
Primary
Gate
Drive
Q1
Lr
Over
Temperature
Protection
Cr
Primary Stage &
Resonant Tank
Slow
current
limit
Fast
current
limit
Overcurrent
Protection
Secondary
Gate Drive
Power
Transformer
VREF
(130ºC ± 5°C)
Vref
C2
C1
40 K
Synchronous
Rectification
Q4
3 V max.
240 µA max.
Temperature
dependent
voltage source
Q3
COUT
TM
IM
-VOUT
+VOUT
VIV0102THJ
PRELIMINARY DATASHEET
10.0 VIV0102THJ VTM BLOCK DIAGRAM
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.9
02/2010
Page 10 of 16
VIV0102THJ
PRELIMINARY DATASHEET
11.0 SINE AMPLITUDE CONVERTER POINT OF LOAD CONVERSION
The Sine Amplitude Converter (SAC) uses a high frequency
resonant tank to move energy from input to output. (The
resonant tank is formed by Cr and leakage inductance Lr in the
power transformer windings as shown in the VTM Block
Diagram. See Section 10). The resonant LC tank, operated at
high frequency, is amplitude modulated as function of input
voltage and output current. A small amount of capacitance
embedded in the input and output stages of the module is
sufficient for full functionality and is key to achieving power
density.
The VIV0102THJ SAC can be simplified into the following
model:
61 pH
OUT
IIOUT
LLININ==3.7
nH
5 nH
ROUT
R
OUT
+
1.7 mΩ
R
RCIN
CIN
6.3 mΩ
VININ
V
LOUT = 600 pH
CCININ
V• I
1/32 • IOUT
+
+
–
900 nF
IIQQ
0.062 A
RCOUT
R
COUT
49 mΩ
+
130 µΩ
1/32 • VIN
CCOUT
OUT
130 µF
VOUT
V
OUT
–
K
–
–
Figure 17 – V•I Chip AC model
At no load:
VOUT = VIN • K
(1)
ROUT = 0 Ω and IQ = 0 A, Eq. (3) now becomes Eq. (1) and is
essentially load independent. A resistor R is now placed in
series with VIN as shown in Figure 18.
K represents the “turns ratio” of the SAC.
Rearranging Eq (1):
R
V
K = OUT
VIN
(2)
VVin
IN
+
–
SAC
SAC
= 1/32
1/32
KK =
Vout
V
OUT
In the presence of load, VOUT is represented by:
VOUT = VIN • K – IOUT • ROUT
(3)
The relationship between VIN and VOUT becomes:
and IOUT is represented by:
IOUT =
IIN – IQ
K
Figure 18 – K = 1/32 Sine Amplitude Converter with series
input resistor
(4)
ROUT represents the impedance of the SAC, and is a function of
the RDSON of the input and output MOSFETs and the winding
resistance of the power transformer. IQ represents the
quiescent current of the SAC control and gate drive circuitry.
The use of DC voltage transformation provides additional
interesting attributes. Assuming for the moment that
VOUT = (VIN – IIN • R) • K
(5)
Substituting the simplified version of Eq. (4)
(IQ is assumed = 0 A) into Eq. (5) yields:
VOUT = VIN • K – IOUT • R • K2
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
(6)
Rev. 1.9
02/2010
Page 11 of 16
v i c o r p o w e r. c o m
VIV0102THJ
This is similar in form to Eq. (3), where ROUT is used to
represent the characteristic impedance of the SAC. However, in
this case a real R on the input side of the SAC is effectively
scaled by K2 with respect to the output.
Assuming that R = 1 Ω, the effective R as seen from the secondary
side is 0.98 mΩ, with K = 1/32 as shown in Figure 18.
A similar exercise should be performed with the additon of a
capacitor, or shunt impedance, at the input to the SAC. A
switch in series with VIN is added to the circuit. This is depicted
in Figure 19.
S
VVin
IN
+
–
C
SAC
SAC
K = 1/32
K = 1/32
VVout
OUT
Figure 19 – Sine Amplitude Converter with input capacitor
A change in VIN with the switch closed would result in a
change in capacitor current according to the following
equation:
IC(t) = C
dVIN
dt
PRELIMINARY DATASHEET
Low impedance is a key requirement for powering a high
current, low voltage load efficiently. A switching regulation
stage should have minimal impedance, while simultaneously
providing appropriate filtering for any switched current. The
use of a SAC between the regulation stage and the point of
load provides a dual benefit, scaling down series impedance
leading back to the source and scaling up shunt capacitance
(or energy storage) as a function of its K factor squared.
However, these benefits are not useful if the series impedance
of the SAC is too high. The impedance of the SAC must be low
well beyond the crossover frequency of the system.
A solution for keeping the impedance of the SAC low involves
switching at a high frequency. This enables magnetic
components to be small since magnetizing currents remain
low. Small magnetics mean small path lengths for turns. Use of
low loss core material at high frequencies reduces core losses
as well.
The two main terms of power loss in the VTM module are:
- No load power dissipation (PNL): defined as the power
used to power up the module with an enabled power
train at no load.
- Resistive loss (ROUT): refers to the power loss across
the VTM modeled as pure resistive impedance.
PDISSIPATED = PNL + PROUT
(7)
(10)
Therefore,
POUT = PIN – PDISSIPATED = PIN – PNL – PROUT
Assume that with the capacitor charged to VIN, the switch is
opened and the capacitor is discharged through the idealized
SAC. In this case,
IC = IOUT • K
(11)
The above relations can be combined to calculate the overall
module efficiency:
(8)
η =
(9)
=
POUT = PIN – PNL – PROUT
PIN
PIN
(12)
Substituting Eq. (1) and (8) into Eq. (7) reveals:
IOUT =
C
K2
•
dVOUT
dt
Writing the equation in terms of the output has yielded a K2
scaling factor for C, this time in the denominator of the
equation. For a K factor less than unity, this results in an
effectively larger capacitance on the output when expressed in
terms of the input. With a K=1/32 as shown in Figure 19,
C=1 µF would effectively appear as C=1024 µF when viewed
from the output.
VIN • IIN – PNL – (IOUT)2 • ROUT
VIN • IIN
= 1–
(
)
PNL + (IOUT)2 • ROUT
VIN • IIN
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.9
02/2010
Page 12 of 16
v i c o r p o w e r. c o m
VIV0102THJ
12.0 INPUT AND OUTPUT FILTER DESIGN
A major advantage of a SAC system versus a conventional
PWM converter is that the former does not require large
functional filters. The resonant LC tank, operated at extreme
high frequency, is amplitude modulated as a function of input
voltage and output current and efficiently transfers charge
through the isolation transformer. A small amount of
capacitance embedded in the input and output stages of the
module is sufficient for full functionality and is key to achieving
high power density.
This paradigm shift requires system design to carefully evaluate
external filters in order to:
1.Guarantee low source impedance.
To take full advantage of the VTM dynamic response, the
impedance presented to its input terminals must be low
from DC to approximately 5 MHz. Input capacitance may
be added to improve transient performance or compensate
for high source impedance.
2.Further reduce input and/or output voltage ripple without
sacrificing dynamic response.
Given the wide bandwidth of the VTM, the source
response is generally the limiting factor in the overall
system response. Anomalies in the response of the source
will appear at the output of the VTM multiplied by its
K factor.
3.Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
cause failures.
The V•I Chip input/output voltage ranges must not be
exceeded. An internal overvoltage lockout function
prevents operation outside of the normal operating input
range. Even during this condition, the powertrain is
exposed to the applied voltage and power MOSFETs must
withstand it.
PRELIMINARY DATASHEET
13.0 CAPACITIVE FILTERING CONSIDERATIONS
FOR A SINE AMPLITUDE CONVERTER
It is important to consider the impact of adding input and
output capacitance to a Sine Amplitude Converter on the
system as a whole. Both the capacitance value, and the
effective impedance of the capacitor must be considered.
A Sine Amplitude Converter has a DC ROUT value which has
already been discussed in section 11. The AC ROUT of the SAC
contains several terms:
• Resonant tank impedance
• Input lead inductance and internal capacitance
• Output lead inductance and internal capacitance
The values of these terms are shown in the behavioral model in
section 11. It is important to note on which side of the
transformer these impedances appear and how they reflect
across the transformer given the K factor.
The overall AC impedance varies from model to model but for
most models it is dominated by DC ROUT value from DC to
beyond 500 KHz. The behavioral model in section 11 should be
used to approximate the AC impedance of the specific model.
Any capacitors placed at the output of the VTM reflect back to
the input of the VTM by the square of the K factor (Eq. 9) with
the impedance of the VTM appearing in series. It is very
important to keep this in mind when using a PRM to power
the VTM. Most PRMs have a limit on the maximum amount of
capacitance that can be applied to the output. This capacitance
includes both the PRM output capacitance and the VTM
output capacitance reflected back to the input. In PRM remote
sense applications, it is important to consider the reflected
value of VTM output capacitance when designing and
compensating the PRM control loop.
Capacitance placed at the input of the VTM appear to the load
reflected by the K factor, with the impedance of the VTM in
series. In step-down VTM ratios, the effective capacitance is
increased by the K factor. The effective ESR of the capacitor is
decreased by the square of the K factor, but the impedance of
the VTM appears in series. Still, in most step-down VTMs an
electrolytic capacitor placed at the input of the VTM will have a
lower effective impedance compared to an electrolytic
capacitor placed at the output. This is important to consider
when placing capacitors at the output of the VTM. Even
though the capacitor may be placed at the output, the majority
of the AC current will be sourced from the lower impedance,
which in most cases will be the VTM. This should be studied
carefully in any system design using a VTM. In most cases, it
should be clear that electrolytic output capacitors are not
necessary to design a stable, well-bypassed system.
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.9
02/2010
Page 13 of 16
v i c o r p o w e r. c o m
VIV0102THJ
14.0 CURRENT SHARING
The SAC topology bases its performance on efficient transfer
of energy through a transformer without the need of closed
loop control. For this reason, the transfer characteristic can be
approximated by an ideal transformer with some resistive drop
and positive temperature coefficient.
This type of characteristic is close to the impedance
characteristic of a DC power distribution system, both in
behavior (AC dynamic) and absolute value (DC dynamic).
When connected in an array with the same K factor, the VTM
module will inherently share the load current with parallel
units, according to the equivalent impedance divider that the
system implements from the power source to the point of load.
Some general recommendations to achieve matched array
impedances:
• Dedicate common copper planes within the PCB
to deliver and return the current to the modules.
• Provide the PCB layout as symmetric as possible.
• Apply same input / output filters (if present) to each unit.
PRELIMINARY DATASHEET
16.0 REVERSE INRUSH CURRENT PROTECTION
The VIV0102THJ provides reverse inrush protection which
prevents reverse current flow until the input voltage is high
enough to first establish current flow in the forward direction.
In the event that there is a DC voltage present on the output
before the VTM is powered up, this feature protects sensitive
loads from excessive dV/dT during power up as shown in
Figure 21.
If a voltage is present at the output of the VTM which satisfies
the condition VOUT > VIN • K after a successful power up the
energy will be transferred from secondary to primary. The input
to output ratio of the VTM will be maintained. The VTM will
continue to operate in reverse as long as the input and output
voltages are within the specified range. The VIV0102THJ has
not been qualified for continuous reverse operation.
PC
IM
VC
TM
R
R
VTM
VIN
+In
+
_
For further details see AN:016 Using BCM™ Bus Converters
in High Power Arrays.
-In
A
VIN
ZIN_EQ1
VTM1
ZOUT_EQ1
VTM2
–
CD
-Out
E
F
G
H
VC
VIN
ZOUT_EQ2
Supply
RO_2
+
B
Supply
VOUT
RO_1
ZIN_EQ2
+Out
DC
Load
VIN
VOUT
ZIN_EQn
VTMn
ZOUT_EQn
RO_n
VOUT
Supply
Figure 20 – VTM array
TM
15.0 FUSE SELECTION
In order to provide flexibility in configuring power systems
V• I Chip products are not internally fused. Input line fusing of
V• I Chip products is recommended at system level to provide
thermal protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
• Current rating (usually greater than maximum VTM current)
• Maximum voltage rating (usually greater than the maximum
possible input voltage)
• Ambient temperature
• Nominal melting I2t
PC
A: VOUT supply > 0 V
B: VC to -IN > 12 V controller wakes-up, PC & TM pulled
high, reverse inrush protection blocks VOUT supplying VIN
C: VIN supply ramps up
D: VIN > VOUT/K, powertrain starts in normal mode
E: VIN supply ramps down
F: VIN > VOUT/K, powertrain transfers reverse energy
G: VOUT ramps down, VIN follows
H: VC turns off
Figure 21 – Reverse inrush protection
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.9
02/2010
Page 14 of 16
v i c o r p o w e r. c o m
VIV0102THJ
PRELIMINARY DATASHEET
17.1 MECHANICAL DRAWING
mm
(inch)
17.2 RECOMMENDED LAND PATTERN
4
3
2
1
A
+Out
+In
B
C
D
E
F
G
H
J
K
-Out
L
M
IM
TM
VC
PC
-In
Bottom View
Signal
Name
Designation
+In
–In
IM
TM
VC
PC
+Out
–Out
A1-B1, A2-B2
L1-M1, L2-M2
E1
F2
G1
H2
A3-D3, A4-D4
J3-M3, J4-M4
17.3 RECOMMENDED LAND PATTERN FOR PUSH PIN HEATSINK
Notes:
1. Maintain 3.50 (0.138) Dia. keep-out zone
free of copper, all PCB layers.
2. (A) minimum recommended pitch is 24.00 (0.945)
this provides 7.50 (0.295) component
edge–to–edge spacing, and 0.50 (0.020)
clearance between Vicor heat sinks.
(B) Minimum recommended pith is 25.50 (1.004).
This provides 9.00 (0.354) component
edge–to–edge spacing, and 2.00 (0.079)
clearence between Vicor heat sinks.
3. V•I Chip land pattern shown for reference
only, actual land pattern may differ.
Dimensions from edges of land pattern
to push–pin holes will be the same for
all half size V•I Chip Products.
4. RoHS complient per CST–0001 latest revision.
5. Unless otherwise specified:
Dimensions are mm (inches)
tolerances are:
x.x (x.xx) = ±0.13 (0.01)
x.xx (x.xxx) = ±0.13 (0.005)
6. Plated through holes for grounding clips (33855)
shown for reference, Heatsink orientation and
device pitch will dictate final grounding solution.
(NO GROUNDING CLIPS)
(WITH GROUNDING CLIPS)
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.9
02/2010
Page 15 of 16
v i c o r p o w e r. c o m
VIV0102THJ
PRELIMINARY DATASHEET
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in
normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper
application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to
the original purchaser only.
EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING,
BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
Vicor will repair or replace defective products in accordance with its own best judgement. For service under this
warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping
instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges
incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within
the terms of this warranty.
Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is
assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve
reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or
circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not
recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten
life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes
all risks of such use and indemnifies Vicor against all damages.
Vicor’s comprehensive line of power solutions includes high density AC-DC
and DC-DC modules and accessory components, fully configurable AC-DC
and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for
its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or
malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are
available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent
applications) relating to the products described in this data sheet. Interested parties should contact Vicor's
Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917;
7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for
use under 6,975,098 and 6,984,965.
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: custserv@vicorpower.com
Technical Support: apps@vicorpower.com
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.9
02/2010
Page 16 of 16
v i c o r p o w e r. c o m