WM8950 Product Datasheet

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WM8950
ADC with Microphone Input and Programmable Digital Filters
DESCRIPTION
FEATURES
The WM8950 is a low power, high quality mono ADC designed
for portable applications such as Digital Still Camera, Digital
Voice Recorder or games console accessories.
Mono ADC:

Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz

SNR 94dB, THD -83dB (‘A’-weighted @ 8 – 48ks/s)

Multiple auxiliary analogue inputs
Mic Preamps:

Differential or single end Microphone Interface
- Programmable preamp gain
- Pseudo differential inputs with common mode rejection
- Programmable ALC / Noise Gate in ADC path

Low-noise bias supplied for electret microphones
The device integrates support for a differential or single ended
mic. External component requirements are reduced as no
separate microphone amplifiers are required.
Advanced Sigma Delta Converters are used along with digital
decimation filters to give high quality audio at sample rates
from 8 to 48ks/s. Additional digital filtering options are
available, to cater for application filtering such as wind noise
reduction, noise rejection, plus an advanced mixed signal ALC
function with noise gate is provided.
An on-chip PLL is provided to generate the required Master
Clock from an external reference clock. The PLL clock can
also be output if required elsewhere in the system.
The WM8950 operates at supply voltages from 2.5 to 3.6V,
although the digital supplies can operate at voltages down to
1.71V to save power. Different sections of the chip can also be
powered down under software control by way of the selectable
two or three wire control interface.
WM8950 is supplied in a very small 4x4mm QFN package,
offering high levels of functionality in minimum board area, with
high thermal performance.
OTHER FEATURES

5 band EQ

Programmable High Pass Filter (wind noise reduction)

Fully Programmable IIR Filter (notch filter)

On-chip PLL

Low power, low voltage
- 2.5V to 3.6V (digital: 1.71V to 3.6V)
- power consumption 10mA all-on 48ks/s mode

4x4x0.9mm 24 lead QFN package
APPLICATIONS




WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews
Digital Still Camera
General Purpose low power audio ADC
Games console accessories
Voice recorders
Production Data, November 2011, Rev 4.4
Copyright 2011 Wolfson Microelectronics plc
WM8950
Production Data
TABLE OF CONTENTS
DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ........................................................................ 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 5 ELECTRICAL CHARACTERISTICS ..................................................................... 6 TERMINOLOGY .............................................................................................................. 7 SIGNAL TIMING REQUIREMENTS ...................................................................... 8 SYSTEM CLOCK TIMING ............................................................................................... 8 AUDIO INTERFACE TIMING – MASTER MODE ............................................................ 8 AUDIO INTERFACE TIMING – SLAVE MODE ............................................................... 9 CONTROL INTERFACE TIMING – 3-WIRE MODE ...................................................... 10 CONTROL INTERFACE TIMING – 2-WIRE MODE ...................................................... 11 DEVICE DESCRIPTION ...................................................................................... 12 INTRODUCTION ........................................................................................................... 12 INPUT SIGNAL PATH ................................................................................................... 13 ANALOGUE TO DIGITAL CONVERTER (ADC) ........................................................... 18 INPUT AUTOMATIC LEVEL CONTROL (ALC) ............................................................. 21 DIGITAL AUDIO INTERFACES ..................................................................................... 38 AUDIO SAMPLE RATES ............................................................................................... 43 MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ................................................ 43 GENERAL PURPOSE INPUT/OUTPUT........................................................................ 45 CONTROL INTERFACE ................................................................................................ 46 RESETTING THE CHIP ....................................................................................... 47 POWER SUPPLIES....................................................................................................... 47 ADC POWER UP/DOWN SEQUENCE ......................................................................... 48 POWER MANAGEMENT .............................................................................................. 49 REGISTER MAP .................................................................................................. 50 DIGITAL FILTER CHARACTERISTICS .............................................................. 51 TERMINOLOGY ............................................................................................................ 51 ADC FILTER RESPONSES .......................................................................................... 52 DE-EMPHASIS FILTER RESPONSES ......................................................................... 53 HIGHPASS FILTER ....................................................................................................... 54 5-BAND EQUALISER .................................................................................................... 55 APPLICATIONS INFORMATION ........................................................................ 59 RECOMMENDED EXTERNAL COMPONENTS ........................................................... 59 PACKAGE DIAGRAM ......................................................................................... 60 IMPORTANT NOTICE ......................................................................................... 61 ADDRESS ..................................................................................................................... 61 REVISION HISTORY ........................................................................................... 62 w
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PIN CONFIGURATION
TOP VIEW
ORDERING INFORMATION
ORDER CODE
TEMPERATURE
RANGE
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PACKAGE BODY
TEMPERATURE
o
WM8950CGEFL/V
-40C to +85C
24-lead QFN (4x4x0.9mm)
(Pb-free)
MSL3
260 C
WM8950CGEFL/RV
-40C to +85C
24-lead QFN (4x4x0.9mm)
(Pb-free, tape and reel)
MSL3
260 C
o
Note:
Reel Quantity = 3,500
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PIN DESCRIPTION
PIN NO
NAME
TYPE
DESCRIPTION
1
MICBIAS
Analogue Output
2
AVDD
Supply
Analogue supply (feeds ADC)
3
AGND
Supply
Analogue ground (feeds ADC)
4
DCVDD
Supply
Digital core supply
5
DBVDD
Supply
Digital buffer (input/output) supply
6
DGND
Supply
7
ADCDAT
Digital Output
Microphone bias
Digital ground
ADC digital audio data output
8
TP
Test Pin
9
FRAME
Digital Input / Output
ADC sample rate clock or frame synch
10
BCLK
Digital Input / Output
Digital audio bit clock
11
MCLK
Digital Input
12
CSB/GPIO
Digital Input / Output
13
SCLK
Digital Input
14
SDIN
Digital Input / Output
15
MODE
Digital Input
DNC
Do not connect
Leave this pin floating
17
DNC
Do not connect
Leave this pin floating
18
AGND2
Supply
19
DNC
Do not connect
20
AVDD2
Supply
21
AUX
Analogue Input
22
VMID
Reference
23
MICN
Analogue Input
Microphone negative input
24
MICP
Analogue Input
Microphone positive input (common mode)
16
Connect to ground
Master clock input
3-Wire MPU chip select or general purpose input/output pin.
3-Wire MPU clock Input / 2-Wire MPU Clock Input
3-Wire MPU data Input / 2-Wire MPU Data Input
Control interface mode selection pin.
Analogue ground
Leave this pin floating
Analogue supply
Auxiliary analogue input
Decoupling for midrail reference voltage
Note:
It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating
at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under
Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
DBVDD, DCVDD, AVDD, AVDD2 supply voltages
MAX
-0.3V
+4.2
Voltage range digital inputs
DGND -0.3V
DVDD +0.3V
Voltage range analogue inputs
AGND -0.3V
AVDD +0.3V
-40C
+85C
Operating temperature range, TA
Storage temperature prior to soldering
30C max / 85% RH max
Storage temperature after soldering
-65C
+150C
Notes:
1.
Analogue and digital grounds must always be within 0.3V of each other.
2.
All digital and analogue supplies are completely independent from each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Digital supply range (Core)
DCVDD
1.71
1
3.6
Digital supply range (Buffer)
DBVDD
1.71
3.6
V
AVDD, AVDD2
2.5
3.6
V
Analogue supplies range
Ground
DGND, AGND, AGND2
TEST CONDITIONS
MIN
TYP
0
MAX
UNIT
V
V
Notes:
1.
When using PLL, DCVDD must be 1.9V or higher.
2.
AVDD must be  DBVDD and DCVDD.
3.
DBVDD must be  DCVDD.
4.
When using PLL, DCVDD must be  1.9V.
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ELECTRICAL CHARACTERISTICS
Test Conditions
o
DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, TA = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Microphone Inputs (MICN, MICP)
Full-scale Input Signal Level
(Note 1) – note this changes with
AVDD
Mic PGA equivalent input noise
VINFS
PGABOOST = 0dB
1.0
Vrms
INPPGAVOL = 0dB
0
dBV
150
uV
At 35.25dB
gain
Input resistance
RMICIN
Gain set to 35.25dB
1.6
k
Input resistance
RMICIN
Gain set to 0dB
47
k
Input resistance
RMICIN
Gain set to -12dB
75
k
Input resistance
RMICIP
(Constant for all gain
settings)
94
k
Input Capacitance
CMICIN
10
pF
Maximum Programmable Gain
35.25
dB
Minimum Programmable Gain
-12
dB
0.75
dB
108
dB
MIC Input Programmable Gain Amplifier (PGA)
Programmable Gain Step Size
Guaranteed monotonic
Mute Attenuation
Selectable Input Gain Boost (0/+20dB)
Gain Boost
0
20
dB
Automatic Level Control (ALC)/Limiter
Target Record Level
-28.5
Maximum Programmable Gain
Minimum Programmable Gain
Programmable Gain Step Size
Gain Hold Time (Note 2)
Gain Ramp-Up (Decay) Time
(Note 3)
Gain Ramp-Down (Attack) Time
(Note 3)
-6
35.25
tHOLD
tDCY
tATK
dB
dB
-12
dB
Guaranteed Monotonic
0.75
dB
MCLK=12.288MHz
(Note 4)
0, 2.67, 5.33, 10.67, … , 43691
ms
(time doubles with each step)
ALCMODE=0 (ALC),
MCLK=12.288MHz
(Note 4)
(time doubles with each step)
3.3, 6.6, 13.1, … , 3360
ALCMODE=1 (limiter),
MCLK=12.288MHz
(Note 4)
(time doubles with each step)
ALCMODE=0 (ALC),
MCLK=12.288MHz
(Note 4)
(time doubles with each step)
ALCMODE=1 (limiter),
MCLK=12.288MHz
(Note 4)
(time doubles with each step)
ms
0.73, 1.45, 2.91, … , 744
0.83, 1.66, 3.33, … , 852
ms
0.18, 0.36, 0.73, … , 186
Analogue to Digital Converter (ADC)
Signal to Noise Ratio (Note 5, 6)
A-weighted,
85
94
dB
-75
-83
dB
1.0
Vrms
0
dBV
20
k
10
pF
0dB PGA gain
Total Harmonic Distortion + Noise
THD+N
(Note 6)
-1dBFS input
0dB PGA gain
Auxiliary Analogue Input (AUX)
Full-scale Input Signal Level (0dB)
– note this changes with AVDD
VINFS
Input Resistance
RAUXIN
Input Capacitance
CAUXIN
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Test Conditions
o
DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, TA = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Microphone Bias
Bias Voltage (MBVSEL=0)
VMICBIAS
0.9*AVDD
V
Bias Voltage (MBVSEL=1)
VMICBIAS
0.65*AVDD
V
Bias Current Source
IMICBIAS
Output Noise Voltage
Vn
3
1K to 20kHz
15
mA
nV/Hz
Digital Input / Output
Input HIGH Level
VIH
Input LOW Level
VIL
Output HIGH Level
VOH
IOL=1mA
Output LOW Level
VOL
IOH-1mA
0.7DVDD
V
0.3DVDD
V
0.1xDVDD
V
0.9DVDD
V
TERMINOLOGY
1.
MICN input only in single ended microphone configuration. Maximum input signal to MICP without distortion is -3dBV.
2.
Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It does not
apply to ramping down the gain when the signal is too loud, which happens without a delay.
3.
Ramp-up and Ramp-Down times are defined as the time it takes for the PGA to change it’s gain by 6dB.
4.
All hold, ramp-up and ramp-down times scale proportionally with MCLK
5.
Signal-to-noise ratio (dB) – SNR is a measure of the difference in level between the full scale output and the output with
no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
6.
THD+N (dB) – THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
o
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25 C, Slave Mode fs = 48kHz, MCLK =
256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock cycle time
TMCLKY
Tbd
MCLK duty cycle
TMCLKDS
60:40
ns
40:60
AUDIO INTERFACE TIMING – MASTER MODE
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
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Test Conditions
o
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25 C, Master Mode, fs=48kHz, MCLK=256fs,
24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
FRAME propagation delay from BCLK falling edge
tDL
10
ns
ADCDAT propagation delay from BCLK falling edge
tDDA
10
ns
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
o
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25 C, Slave Mode, fs=48kHz, MCLK= 256fs,
24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
FRAME set-up time to BCLK rising edge
tLRSU
10
ns
FRAME hold time from BCLK rising edge
tLRH
10
ns
ADCDAT propagation delay from BCLK falling edge
tDD
ns
20
ns
Note:
BCLK period should always be greater than or equal to MCLK period.
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CONTROL INTERFACE TIMING – 3-WIRE MODE
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
o
DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, TA = +25 C, Slave Mode, fs = 48kHz,
MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
tSCS
80
ns
SCLK pulse cycle time
tSCY
200
ns
SCLK pulse width low
tSCL
80
ns
SCLK pulse width high
tSCH
80
ns
SDIN to SCLK set-up time
tDSU
40
ns
SCLK to SDIN hold time
tDHO
40
ns
CSB pulse width low
tCSL
40
ns
CSB pulse width high
tCSH
40
ns
CSB rising to SCLK rising
tCSS
40
tps
0
Pulse width of spikes that will be suppressed
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ns
5
ns
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CONTROL INTERFACE TIMING – 2-WIRE MODE
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t1
t9
t7
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
o
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25 C, Slave Mode, fs = 48kHz, MCLK =
256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
526
kHz
Program Register Input Information
SCLK Frequency
0
SCLK Low Pulse-Width
t1
1.3
us
SCLK High Pulse-Width
t2
600
ns
Hold Time (Start Condition)
t3
600
ns
Setup Time (Start Condition)
t4
600
ns
Data Setup Time
t5
100
SDIN, SCLK Rise Time
t6
300
ns
SDIN, SCLK Fall Time
t7
300
ns
Setup Time (Stop Condition)
t8
Data Hold Time
t9
Pulse width of spikes that will be suppressed
tps
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ns
600
0
ns
900
ns
5
ns
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DEVICE DESCRIPTION
INTRODUCTION
The WM8950 is a low power audio ADC, with flexible line and microphone input. Applications for this
device include games console accessories, digital still cameras, voice recorders and other general
purpose audio applications.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as
follows:
MICROPHONE INPUTS
Microphone inputs are provided, allowing for either a differential microphone input or a single ended
microphone to be connected. These inputs have a user programmable gain range of -12dB to
+35.25dB using internal resistors. After the input PGA stage comes a boost stage which can add a
further 20dB of gain. A microphone bias is output from the chip which can be used to bias the
microphones. The signal routing can be configured to allow manual adjustment of mic levels, or to
allow the ALC loop to control the level of mic signal that is transmitted.
Total gain through the microphone paths of up to +55.25dB can be selected.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually
or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the
recording volume constant.
AUX INPUT
The device includes a mono input, AUX, that can be used as an input for warning tones (beep) etc.
This path can also be summed into the input in a flexible fashion, either to the input PGA as a second
microphone input or as a line input. The configuration of this circuit, with integrated on-chip resistors
allows several analogue signals to be summed into the single AUX input if required.
ADC
The mono ADC uses a multi-bit high-order oversampling architecture to deliver optimum performance
with low power consumption. Various sample rates are supported, from the 8ks/s rate typically used
in voice dictation, up to the 48ks/s rate used in high quality audio applications.
DIGITAL FILTERING
Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to
give high quality audio at sample rates from 8ks/s to 48ks/s.
Application specific digital filters are also available which help to reduce the effect of specific noise
sources such as ‘wind noise’. The filters include a programmable ADC high pass filter, an IIR filter
with fully programmable coefficients, and a 5-band equaliser that can be applied to the record path in
order to improve the overall audio sound from the device.
AUDIO INTERFACES
The WM8950 has a standard audio interface, to support the transmission of audio data from the chip.
This interface is a 4 wire standard audio interface which supports a number of audio data formats
2
including I S, DSP Mode, MSB-First, left justified and MSB-First, right justified, and can operate in
master or slave modes.
CONTROL INTERFACES
To allow full software control over all its features, the WM8950 offers a choice of 2 or 3 wire MPU
control interface. It is fully compatible and an ideal partner for a wide range of industry standard
microprocessors, controllers and DSPs. The selection between 2-wire mode and 3-wire mode is
determined by the state of the MODE pin. If MODE is high then 3-wire control mode is selected, if
MODE is low then 2-wire control mode is selected.
In 2 wire mode, only slave operation is supported, and the address of the device is fixed as 0011010.
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CLOCKING SCHEMES
WM8950 offers the normal audio clocking scheme operation, where 256fs MCLK is provided to the
ADC.
However, a PLL is also included which may be used to generate the internal master clock frequency
in the event that this is not available from the system controller. This PLL uses an input clock,
typically the 12MHz USB or ilink clock, to generate high quality audio clocks. If this PLL is not
required for generation of these clocks, it can be reconfigured to generate alternative clocks which
may then be output on the CSB/GPIO pin and used elsewhere in the system.
POWER CONTROL
The design of the WM8950 has given much attention to power consumption without compromising
performance. It operates at low supply voltages, and includes the facility to power off any unused
parts of the circuitry under software control, includes standby and power off modes.
INPUT SIGNAL PATH
The WM8950 has 3 flexible analogue inputs: two microphone inputs, and an auxiliary input. These
inputs can be used in a variety of ways. The input signal path before the ADC has a flexible PGA
block which then feeds into a gain boost/mixer stage.
MICROPHONE INPUTS
The WM8950 can accommodate a variety of microphone configurations including single ended and
differential inputs. The inputs through the MICN, MICP and optionally AUX pins are amplified through
the input PGA as shown in Figure 6 .
A pseudo differential input is the preferential configuration where the positive terminal of the input
PGA is connected to the MICP input pin by setting MICP2INPPGA=1. The microphone ground
should then be connected to MICN (when MICN2INPPGA=1) or optionally to AUX (when
AUX2INPPGA=1) input pins.
Alternatively a single ended microphone can be connected to the MICN input with MICN2INPPGA set
to 1. The non-inverting terminal of the input PGA should be connected internally to VMID by setting
MICP2INPPGA to 0.
Figure 6 Microphone Input PGA Circuit (switch positions shown are for differential mic
input)
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REGISTER
ADDRESS
R44
BIT
LABEL
0
MICP2INPPGA
DEFAULT
1
DESCRIPTION
Connect input PGA amplifier positive
terminal to MICP or VMID.
Input Control
0 = input PGA amplifier positive terminal
connected to VMID
1 = input PGA amplifier positive terminal
connected to MICP through variable resistor
string
1
MICN2INPPGA
1
Connect MICN to input PGA negative
terminal.
0=MICN not connected to input PGA
1=MICN connected to input PGA amplifier
negative terminal.
2
AUX2INPPGA
0
Select AUX amplifier output as input PGA
signal source.
0=AUX not connected to input PGA
1=AUX connected to input PGA amplifier
negative terminal.
The input PGA is enabled by the IPPGAEN register bit.
REGISTER
ADDRESS
BIT
2
R2
LABEL
DEFAULT
INPPGAEN
DESCRIPTION
0
Input microphone PGA enable
0 = disabled
Power
Management 2
1 = enabled
INPUT PGA VOLUME CONTROL
The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain
from the MICN input to the PGA output and from the AUX amplifier to the PGA output are always
common and controlled by the register bits INPPGAVOL[5:0]. These register bits also affect the
MICP pin when MICP2INPPGA=1.
When the Automatic Level Control (ALC) is enabled the input PGA gain is then controlled
automatically and the INPPGAVOL bits should not be used.
REGISTER
ADDRESS
R45
BIT
5:0
LABEL
INPPGAVOL
DEFAULT
010000
Input PGA
volume
control
DESCRIPTION
Input PGA volume
000000 = -12dB
000001 = -11.25db
.
010000 = 0dB
.
111111 = 35.25dB
6
INPPGAMUTE
0
Mute control for input PGA:
0=Input PGA not muted, normal operation
1=Input PGA muted (and disconnected from
the following input BOOST stage).
7
INPPGAZC
0
Input PGA zero cross enable:
0=Update gain when gain register changes
st
1=Update gain on 1 zero cross after gain
register write.
R32
8
ALCSEL
ALC control 1
0
ALC function select:
0=ALC off (PGA gain set by INPPGAVOL
register bits)
1=ALC on (ALC controls PGA gain)
Table 1 Input PGA Volume Control
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AUXILIARY INPUT
An auxiliary input circuit (Figure 7) is provided which consists of an amplifier which can be configured
either as an inverting buffer for a single input signal or as a mixer/summer for multiple inputs with the
use of external resistors. The circuit is enabled by the register bit AUXEN.
Figure 7 Auxiliary Input Circuit
The AUXMODE register bit controls the auxiliary input mode of operation:
In buffer mode (AUXMODE=0) the switch labelled AUXSW in Figure 7 is open and the signal at the
AUX pin will be buffered and inverted through the aux circuit using only the internal components.
In mixer mode (AUXMODE=1) the on-chip input resistor is bypassed, this allows the user to sum in
multiple inputs with the use of external resistors. When used in this mode there will be gain
variations through this path from part to part due to the variation of the internal 20kΩ resistors relative
to the higher tolerance external resistors.
REGISTER
ADDRESS
R1
BIT
6
LABEL
AUXEN
DEFAULT
0
Auxiliary input buffer enable
0 = OFF
Power
management 1
R44
DESCRIPTION
1 = ON
3
AUXMODE
Input control
0
0 = inverting buffer
1 = mixer (on-chip input resistor bypassed)
Table 2 Auxiliary Input Buffer Control
INPUT BOOST
The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the AUX
amplifier output and the MICP input pin (when not using a differential microphone configuration).
These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure
8.
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Figure 8 Input Boost Stage
The input PGA path can have a +20dB boost (PGABOOST=1) a 0dB pass through (PGABOOST=0)
or be completely isolated from the input boost circuit (INPPGAMUTE=1).
REGISTER
ADDRESS
R45
BIT
6
LABEL
INPPGAMUTE
0
Mute control for input PGA:
Input PGA gain
control
R47
DESCRIPTION
DEFAULT
0=Input PGA not muted, normal operation
1=Input PGA muted (and disconnected from
the following input BOOST stage).
8
PGABOOST
1
0 = PGA output has +0dB gain through input
BOOST stage.
Input BOOST
control
1 = PGA output has +20dB gain through
input BOOST stage.
Table 3 Input BOOST Stage Control
The Auxiliary amplifier path to the BOOST stage is controlled by the AUX2BOOSTVOL[2:0] register
bits. When AUX2BOOSTVOL=000 this path is completely disconnected from the BOOST stage.
Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB.
The MICP path to the BOOST stage is controlled by the MICP2BOOSTVOL[2:0] register bits. When
MICP2BOOSTVOL=000 this input pin is completely disconnected from the BOOST stage. Settings
001 through to 111 control the gain in 3dB steps from -12dB to +6dB.
REGISTER
ADDRESS
R47
BIT
2:0
LABEL
AUX2BOOSTVOL
DEFAULT
000
Input BOOST
control
DESCRIPTION
Controls the auxiliary amplifier to the input
boost stage:
000=Path disabled (disconnected)
001=-12dB gain through boost stage
010=-9dB gain through boost stage
…
111=+6dB gain through boost stage
6:4
MICP2BOOSTVOL
000
Controls the MICP pin to the input boost
stage (NB, when using this path set
MICPZIUNPPGA=0):
000=Path disabled (disconnected)
001=-12dB gain through boost stage
010=-9dB gain through boost stage
…
111=+6dB gain through boost stage
Table 4 Input BOOST Stage Control
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The BOOST stage is enabled under control of the BOOSTEN register bit.
REGISTER
ADDRESS
R2
BIT
4
LABEL
BOOSTEN
DEFAULT
0
DESCRIPTION
Input BOOST enable
Power
management 2
0 = Boost stage OFF
1 = Boost stage ON
Table 5 Input BOOST Enable Control
MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type
microphones and the associated external resistor biasing network. Refer to the Applications
Information section for recommended external components. The MICBIAS voltage can be altered via
the MBVSEL register bit.
When MBVSEL=0, MICBIAS=0.9*AVDD and when MBVSEL=1,
MICBIAS=0.65*AVDD. The output can be enabled or disabled using the MICBEN control bit.
REGISTER
ADDRESS
R1
BIT
4
LABEL
MICBEN
DEFAULT
0
DESCRIPTION
Microphone Bias Enable
Power
management 1
0 = OFF (high impedance output)
1 = ON
Table 6 Microphone Bias Enable
REGISTER
ADDRESS
R44
BIT
8
LABEL
MBVSEL
DEFAULT
0
DESCRIPTION
Microphone Bias Voltage Control
Input Control
0 = 0.9 * AVDD
1 = 0.65 * AVDD
Table 7 Microphone Bias Voltage Control
The internal MICBIAS circuitry is shown in Figure 9. Note that the maximum source current capability
for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the
MICBIAS current to 3mA.
VMID
MB
internal
resistor
internal
resistor
MBVSEL=0
MICBIAS
= 1.8 x VMID
= 0.9 X AVDD
MBVSEL=1
MICBIAS
= 1.3 x VMID
= 0.65 X AVDD
AGND
Figure 9 Microphone Bias Schematic
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ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8950 uses a multi-bit, oversampled sigma-delta ADC channel. The use of multi-bit feedback
and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full
Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0Vrms.
Any voltage greater than -1dBfs may overload the ADC and cause distortion.
ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital
filter path is illustrated in Figure 10 .
Figure 10 ADC Digital Filter Path
The ADC is enabled by the ADCEN register bit.
REGISTER
ADDRESS
R2
BIT
0
LABEL
ADCEN
DEFAULT
0
DESCRIPTION
0 = ADC disabled
Power
management 2
1 = ADC enabled
Table 8 ADC Enable
The polarity of the output signal can also be changed under software control using the ADCPOL
register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit.
With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when
ADCOSR=1 the oversample rate is 128x which gives best performance.
REGISTER
ADDRESS
R14
BIT
3
LABEL
ADCOSR
DEFAULT
0
ADC Control
DESCRIPTION
ADC oversample rate select:
0=64x (lower power)
1=128x (best performance)
0
ADCPOL
0
0=normal
1=inverted
Table 9 ADC Oversample Rate Select
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SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two
modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off
frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off
frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown
in Table 11.
REGISTER
ADDRESS
BIT
R14
LABEL
DEFAULT
8
HPFEN
1
7
HPFAPP
0
DESCRIPTION
High Pass Filter Enable
0=disabled
ADC Control
1=enabled
Select audio mode or application mode
st
0=Audio mode (1 order, fc = ~3.7Hz)
nd
1=Application mode (2 order, fc =
HPFCUT)
6:4
HPFCUT
000
Application mode cut-off frequency
See Table 11 for details.
Table 10 ADC Filter Select
HPFCUT
[2:0]
SAMPLE FREQUENCY (kHz)
8
11.025
12
16
SR=101/100
22.05
24
32
SR=011/010
44.1
48
SR=001/000
000
82
113
122
82
113
122
82
113
122
001
102
141
153
102
141
153
102
141
153
010
131
180
196
131
180
196
131
180
196
011
163
225
245
163
225
245
163
225
245
100
204
281
306
204
281
306
204
281
306
101
261
360
392
261
360
392
261
360
392
110
327
450
490
327
450
490
327
450
490
111
408
563
612
408
563
612
408
563
612
Table 11 High Pass Filter Cut-off Frequencies (HPFAPP=1) Values in Hz
Note that the High Pass filter values (when HPFAPP=1) work on the basis that the SR register bits
are set correctly for the actual sample rate as shown in Table 11.
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PROGRAMMABLE IIR FILTER
An IIR filter with fully programmable coefficients is provided, typically used as a notch filter for
removing narrow band noise at a given frequency. This notch filter has a variable centre frequency
and bandwidth, programmable via two coefficients, a0 and a1. These coefficients should be
converted to 2’s complement numbers to determine the register values. a0 and a1 are represented
by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four
register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all
four registers are setup.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R27
6:0
NFA0[13:7]
0
Notch filter a0 coefficient, bits [13:7]
Notch Filter 1
7
NFEN
0
Notch filter enable:
0=Disabled
8
NFU
0
R28
6:0
NFA0[6:0]
0
Notch filter a0 coefficient, bits [6:0]
Notch Filter 2
8
NFU]
0
Notch filter update. The notch filter values
1=Enabled
Notch filter update. The notch filter values
used internally only update when one of
the NFU bits is set high.
used internally only update when one of
the NFU bits is set high.
R29
NFA1[13:7]
0
Notch filter a1 coefficient, bits [13:7]
8
NFU
0
Notch filter update. The notch filter values
used internally only update when one of
R30
6:0
NFA1[6:0]
0
Notch filter a1 coefficient, bits [6:0]
Notch Filter 4
8
NFU
0
Notch filter update. The notch filter values
6:0
Notch Filter 3
the NFU bits is set high.
used internally only update when one of
the NFU bits is set high.
Table 12 Notch Filter Function
The coefficients are calculated as follows:
a0 
1  tan( wb / 2)
1  tan( wb / 2)
a1  (1  a0 ) cos( w0 )
Where:
w0  2f c / f s
wb  2f b / f s
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz
The coefficients are calculated as follows:
13
NFA0 = -a0 x 2
12
NFA1 = -a1 x 2
These values are then converted to 2’s complement notation to determine the register values.
NOTCH FILTER WORKED EXAMPLE
The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre
frequency and -3dB bandwidth.
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fc = 1000 Hz
fb = 100 Hz
fs = 48000 Hz
w 0  2fc / fs
= 2 x (1000 / 48000) = 0.1308996939 rads
w b  2fb / fs
= 2 x (100 / 48000) = 0.01308996939 rads
a0 
1  tan( w b / 2)
1  tan( w b / 2)
=
1  tan(0.0130899693 9 / 2)
1  tan(0.0130899693 9 / 2)
a1  (1  a0 ) cos( w 0 )
=
= 0.9869949627
(1  0.9869949627 ) cos(0.1308996939 )
= -1.969995945
NFn_A0 = -a0 x 213 = -8085 (rounded to nearest whole number)
NFn_A1 = -a1 x 212 = 8069 (rounded to nearest whole number)
These values are then converted to 2’s complement:
NFA0 = 14’h206B = 14’b10000001101011
NFA1 = 14’h1F85 = 14’b 01111110000101
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally attenuated over a range from –127dB to 0dB in 0.5dB steps.
The gain for a given eight-bit code X is given by:
Gain = 0.5 x (x–255) dB for 1  x  255, MUTE for x = 0
REGISTER
ADDRESS
R15
BIT
7:0
ADC Digital
Volume
LABEL
DEFAULT
DESCRIPTION
ADCVOL
11111111
ADC Digital Volume Control
[7:0]
( 0dB )
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
Table 13 ADC Volume
INPUT AUTOMATIC LEVEL CONTROL (ALC)
The WM8950 has an automatic PGA gain control circuit, which can function as an input peak limiter
or as an automatic level control (ALC).
The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to
the amplitude of the input signal. A digital peak detector monitors the input signal amplitude and
compares it to a register defined threshold level (ALCLVL).
If the signal is below the threshold, the ALC will increase the gain of the PGA at a rate set by
ALCDCY. If the signal is above the threshold, the ALC will reduce the gain of the PGA at a rate set
by ALCATK.
The ALC has two modes selected by the ALCMODE register: normal mode and peak limiter mode.
The ALC/limiter function is enabled by setting the register bit R32[8] ALCSEL.
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REGISTER
ADDRESS
R32 (20h)
BIT
2:0
ALC Control 1
LABEL
ALCMIN
DEFAULT
000 (-12dB)
[2:0]
DESCRIPTION
Set minimum gain of PGA
000 = -12dB
001 = -6dB
010 = 0dB
011 = +6dB
100 = +12dB
101 = +18dB
110 = +24dB
111 = +30dB
5:3
ALCMAX
[2:0]
111
(+35.25dB)
Set Maximum Gain of PGA
111 = +35.25dB
110 = +29.25dB
101 = +23.25dB
100 = +17.25dB
011 = +11.25dB
010 = +5.25dB
001 = -0.75dB
000 = -6.75dB
8
ALCSEL
0
ALC function select
0 = ALC disabled
1 = ALC enabled
R33 (21h)
3:0
ALC Control 2
ALCLVL
1011
[3:0]
(-12dB)
ALC target – sets signal level at ADC
input
1111 = -6dBFS
1110 = -7.5dBFS
1101 = -9dBFS
1100 = -10.5dBFS
1011 = -12dBFS
1010 = -13.5dBFS
1001 = -15dBFS
1000 = -16.5dBFS
0111 = -18dBFS
0110 = -19.5dBFS
0101 = -21dBFS
0100 = -22.5dBFS
0011 = -24dBFS
0010 = -25.5dBFS
0001 = -27dBFS
0000 = -28.5dBFS
8
ALCZC
0 (zero cross
off)
ALC uses zero cross detection circuit.
0 = Disabled (recommended)
1 = Enabled
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REGISTER
ADDRESS
BIT
7:4
R34 (22h)
LABEL
DEFAULT
DESCRIPTION
ALCHLD
0000
[3:0]
(0ms)
8
ALCMODE
0
7:4
ALCDCY
0011
Determines the ALC mode of operation:
0 = ALC mode (Normal Operation)
1 = Limiter mode.
Decay (gain ramp-up) time
[3:0]
(26ms/6dB)
(ALCMODE ==0)
ALC Control 3
ALC hold time before gain is increased.
0000 = 0ms
0001 = 2.67ms
0010 = 5.33ms
0011 = 10.66ms
0100 = 21.32ms
0101 = 42.64ms
0110 = 85.28ms
0111 = 0.17s
1000 = 0.34s
1001 = 0.68s
1010 or higher = 1.36s
Per step
Per 6dB
90% of
range
0000
410us
3.38ms
23.6ms
0001
820us
6.56ms
47.2ms
0010
1.64ms
13.1ms
94.5ms
… (time doubles with every step)
0011
420ms
3.36s
1010
or
higher
Decay (gain ramp-up) time
(5.8ms/6dB)
(ALCMODE ==1)
Per step
Per 6dB
24.2s
90% of
range
0000
90.8us
726us
5.23ms
0001
182us
1.45ms
10.5ms
0010
363us
2.91ms
20.9ms
… (time doubles with every step)
1010
3:0
93ms
744ms
5.36s
ALCATK
0010
ALC attack (gain ramp-down) time
[3:0]
(3.3ms/6dB)
(ALCMODE == 0)
Per step
Per 6dB
90% of
range
0000
104us
832us
6ms
0001
208us
1.66ms
12ms
0010
416us
3.33ms
24ms
… (time doubles with every step)
1010 or 106ms
higher
852ms
6.13s
0010
ALC attack (gain ramp-down) time
(726us/6dB)
(ALCMODE == 1)
Per step
Per 6dB
90% of
range
0000
22.7us
182.4us
1.31ms
0001
45.4us
363us
2.62ms
0010
90.8us
726us
5.23ms
… (time doubles with every step)
1010 or
higher
23.2ms
186ms
1.34s
Table 14 ALC Control Registers
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When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input
gain update must be made by writing to the INPPGAVOLL/R register bits.
NORMAL MODE
In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing
the gain of the PGA. The following diagram shows an example of this.
Figure 11 ALC Normal Mode Operation
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LIMITER MODE
In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the
PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is
enabled in limiter mode. If the ALC is started in limiter mode, this is the gain setting of the PGA at
start-up. If the ALC is switched into limiter mode after running in ALC mode, the starting gain will be
the gain at switchover. The diagram below shows an example of limiter mode.
Figure 12 ALC Limiter Mode Operation
ATTACK AND DECAY TIMES
The attack and decay times set the update times for the PGA gain. The attack time is the time
constant used when the gain is reducing. The decay time is the time constant used when the gain is
increasing. In limiter mode, the time constants are faster than in ALC mode. The time constants are
shown below in terms of a single gain step, a change of 6dB and a change of 90% of the PGAs gain
range.
Note that, these times will vary slightly depending on the sample rate used (specified by the SR
register).
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NORMAL MODE
ALCMODE = 0 (Normal Mode)
ALCATK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
tATK
104µs
208µs
416µs
832µs
1.66ms
3.33ms
6.66ms
13.3ms
26.6ms
53.2ms
106ms
Attack Time (s)
tATK6dB
tATK90%
832µs
6ms
1.66ms
12ms
3.33ms
24ms
6.66ms
48ms
13.3ms
96ms
26.6ms
192ms
53.2ms
384ms
106ms
767ms
213.2ms
1.53s
426ms
3.07s
852ms
6.13s
ALCMODE = 0 (Normal Mode)
ALCDCY
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
tDCY
410µs
820µs
1.64ms
3.28ms
6.56ms
13.1ms
26.2ms
52.5ms
105ms
210ms
420ms
Decay Time (s)
tDCY6dB
tDCY90%
3.28ms
23.6ms
6.56ms
47.2ms
13.1ms
94.5ms
26.2ms
189ms
52.5ms
378ms
105ms
756ms
210ms
1.51s
420ms
3.02s
840ms
6.05s
1.68s
12.1s
3.36s
24.2s
Table 15 ALC Normal Mode (Attack and Decay times)
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LIMITER MODE
ALCMODE = 1 (Limiter Mode)
ALCATK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
tATKLIM
22.7µs
45.4µS
90.8µS
182µS
363µS
726µS
1.45ms
2.9ms
5.81ms
11.6ms
23.2ms
Attack Time (s)
tATKLIM6dB
tATKLIM90%
182µs
1.31ms
363µs
2.62ms
726µs
5.23ms
1.45ms
10.5ms
2.91ms
20.9ms
5.81ms
41.8ms
11.6ms
83.7ms
23.2ms
167ms
46.5ms
335ms
93ms
669ms
186ms
1.34s
ALCMODE = 1 (Limiter Mode)
ALCDCY
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
tDCYLIM
90.8µs
182µS
363µS
726µS
1.45ms
2.91ms
5.81ms
11.6ms
23.2ms
46.5ms
93ms
Attack Time (s)
tDCYLIM6dB
tDCYLIM90%
726µs
5.23ms
1.45ms
10.5ms
2.91ms
20.9ms
5.81ms
41.8ms
11.6ms
83.7ms
23.2ms
167ms
46.5ms
335ms
93ms
669ms
186ms
1.34s
372ms
2.68s
744ms
5.36s
Table 16 ALC Limiter Mode (Attack and Decay times)
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MINIMUM AND MAXIMUM GAIN
The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be
set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
REGISTER
ADDRESS
R32
BIT
5:3
ALC Control 1 2:0
LABEL
DEFAULT
DESCRIPTION
ALCMAX
111
Set Maximum Gain of PGA
ALCMIN
000
Set minimum gain of PGA
Table 17 ALC Max/Min Gain
In normal mode, ALCMAX sets the maximum boost which can be applied to the signal. In limiter
mode, ALCMAX will normally have no effect (assuming the starting gain value is less than the
maximum gain specified by ALCMAX) because the maximum gain is set at the starting gain level.
ALCMIN sets the minimum gain value which can be applied to the signal.
Figure 13 ALC Min/Max Gain
ALCMAX
111
110
101
100
011
010
001
000
Maximum Gain (dB)
35.25
29.25
23.25
17.25
11.25
5.25
-0.75
-6.75
Table 18 ALC Max Gain Values
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ALCMIN
000
001
010
011
100
101
110
111
Minimum Gain (dB)
-12
-6
0
6
12
18
24
30
Table 19 ALC Min Gain Values
Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC
outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will
immediately adjust the gain to return to the ALC operating range. It is recommended that the ALC
starting gain is set between the ALCMAX and ALCMIN limits.
ALC HOLD TIME (NORMAL MODE ONLY)
In Normal mode, the ALC has an adjustable hold time which sets a time delay before the ALC begins
its decay phase (gain increasing). The hold time is set by the ALCHLD register.
REGISTER
ADDRESS
R33
BIT
7:4
LABEL
ALCHLD
DEFAULT
0000
DESCRIPTION
ALC hold time before gain is increased.
ALC Control 2
Table 20 ALC Hold Time
If the hold time is exceeded this indicates that the signal has reached a new average level and the
ALC will increase the gain to adjust for that new average level. If the signal goes above the threshold
during the hold period, the hold phase is abandoned and the ALC returns to normal operation.
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Figure 14 ALCLVL
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Figure 15 ALC Hold Time
ALCHLD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
tHOLD (s)
0
2.67ms
5.34ms
10.7ms
21.4ms
42.7ms
85.4ms
171ms
342ms
684ms
1.37s
Table 21 ALC Hold Time Values
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PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is
ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below
87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is
designed to prevent clipping when long attack times are used.
NOISE GATE (NORMAL MODE ONLY)
When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise
pumping”, i.e. loud hissing noise during silence periods. The WM8950 has a noise gate function that
prevents noise pumping by comparing the signal level at the input pins against a noise gate
threshold, NGTH. The noise gate cuts in when:
Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB]
This is equivalent to:
Signal level at input pin [dBFS] < NGTH [dBFS]
The PGA gain is then held constant (preventing it from ramping up as it normally would when the
signal is quiet).
The table below summarises the noise gate control register. The NGTH control bits set the noise
gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps.
Levels at the extremes of the range may cause inappropriate operation, so care should be taken with
set–up of the function. The noise gate only operates in conjunction with the ALC and cannot be used
in limiter mode.
REGISTER
ADDRESS
R35 (23h)
BIT
2:0
LABEL
NGTH
DEFAULT
000
DESCRIPTION
Noise gate threshold:
ALC Noise Gate
000 = -39dB
Control
001 = -45dB
010 = -51db
011 = -57dB
100 = -63dB
101 = -69dB
110 = -75dB
111 = -81dB
3
NGATEN
0
Noise gate function enable
1 = enable
0 = disable
Table 22 ALC Noise Gate Control
The diagrams below show the response of the system to the same signal with and without noise
gate.
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Figure 16 ALC Operation Above Noise Gate Threshold
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Figure 17 Noise Gate Operation
GRAPHIC EQUALISER
A 5-band graphic EQ is provided, which can be applied to the ADC data under control of the
EQMODE register bit.
REGISTER
ADDRESS
R18
BIT
8
EQ Control 1
LABEL
EQMODE
DEFAULT
1
DESCRIPTION
0 = Equaliser applied to ADC data
1 = Equaliser bypassed
Table 23 EQ Select
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The equaliser consists of low and high frequency shelving filters (Band 1 and 5) and three peak filters
for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost (+/- 12dB
in 1dB steps). The peak filters have selectable bandwidth.
REGISTER
ADDRESS
R18
BIT
4:0
LABEL
EQ1G
EQ Band 1
Control
6:5
EQ1C
DEFAULT
01100
DESCRIPTION
(0dB)
Band 1 Gain Control. See Table 29 for
details.
01
Band 1 Cut-off Frequency:
00=80Hz
01=105Hz
10=135Hz
11=175Hz
Table 24 EQ Band 1 Control
REGISTER
ADDRESS
R19
BIT
4:0
LABEL
EQ2G
EQ Band 2
Control
6:5
EQ2C
DEFAULT
01100
DESCRIPTION
(0dB)
Band 2 Gain Control. See Table 29 for
details.
01
Band 2 Centre Frequency:
00=230Hz
01=300Hz
10=385Hz
8
EQ2BW
11=500Hz
Band 2 Bandwidth Control
0
0=narrow bandwidth
1=wide bandwidth
Table 25 EQ Band 2 Control
REGISTER
ADDRESS
R20
BIT
4:0
LABEL
EQ3G
EQ Band 3
Control
6:5
EQ3C
DEFAULT
01100
DESCRIPTION
(0dB)
Band 3 Gain Control. See Table 29 for
details.
01
Band 3 Centre Frequency:
00=650Hz
01=850Hz
8
EQ3BW
0
10=1.1kHz
11=1.4kHz
Band 3 Bandwidth Control
0=narrow bandwidth
1=wide bandwidth
Table 26 EQ Band 3 Control
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REGISTER
ADDRESS
R21
BIT
4:0
LABEL
EQ4G
EQ Band 4
Control
6:5
EQ4C
DEFAULT
01100
DESCRIPTION
(0dB)
Band 4 Gain Control. See Table 29 for
details
01
Band 4 Centre Frequency:
00=1.8kHz
01=2.4kHz
8
EQ4BW
10=3.2kHz
11=4.1kHz
Band 4 Bandwidth Control
0
0=narrow bandwidth
1=wide bandwidth
Table 27 EQ Band 4 Control
REGISTER
ADDRESS
R22
BIT
4:0
LABEL
EQ5G
EQ Band 5
Gain Control
6:5
EQ5C
DEFAULT
01100
DESCRIPTION
(0dB)
Band 5 Gain Control. See Table 29 for
details.
01
Band 5 Cut-off Frequency:
00=5.3kHz
01=6.9kHz
10=9kHz
11=11.7kHz
Table 28 EQ Band 5 Control
GAIN REGISTER
GAIN
00000
+12dB
00001
+11dB
00010
+10dB
…. (1dB steps)
01100
0dB
01101
-1dB
11000 to 11111
-12dB
Table 29 Gain Register Table
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A dedicated buffer is available for tieing off unused analogue input pins as shown below Figure 18.
This buffer can be enabled using the BUFIOEN register bit.
Figure 18 Unused Input Pin Tie-off Buffers
THERMAL SHUTDOWN
To protect the WM8950 from overheating a thermal shutdown circuit is included. If the device
0
temperature reaches approximately 125 C and the thermal shutdown circuit is enabled (TSDEN=1),
an interrupt can be generated. See the GPIO and Interrupt Controller section for details.
REGISTER
ADDRESS
R49
BIT
1
LABEL
TSDEN
Output control
DEFAULT
1
DESCRIPTION
Thermal Shutdown Enable
0 : thermal shutdown disabled
1 : thermal shutdown enabled
Table 30 Thermal Shutdown
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DIGITAL AUDIO INTERFACES
The audio interface has three pins:

ADCDAT: ADC data output

FRAME: Data alignment clock

BCLK: Bit clock, for synchronisation
The clock signals BCLK, and FRAME can be outputs when the WM8950 operates as a master, or
inputs when it is a slave (see Master and Slave Mode Operation, below).
Five different audio data formats are supported:

Left justified

Right justified

IS
DSP mode

2
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8950 audio interface may be configured as either master or slave. As a master interface
device the WM8950 generates BCLK and FRAME and thus controls sequencing of the data transfer
on ADCDAT. To set the device to master mode register bit MS should be set high. In slave mode
(MS=0), the WM8950 responds with data to clocks it receives over the digital audio interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an FRAME
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each FRAME transition.
Figure 19 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a FRAME
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each FRAME transition.
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Figure 20 Right Justified Audio Interface (assuming n-bit word length)
2
In I S mode, the MSB is available on the second rising edge of BCLK following a FRAME transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
2
Figure 21 I S Audio Interface (assuming n-bit word length)
nd
In DSP/PCM mode, the left channel MSB is available on the 2 (mode A) rising edge of BCLK
following a rising edge of FRAME. Right channel data immediately follows left channel data.
Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles
between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 22. In device
slave mode, Figure 23 it is possible to use any length of frame pulse less than 1/fs, providing the
falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the
next frame pulse.
Figure 22 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)
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Figure 23 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)
When using ADCLRSWAP = 1 in DSP/PCM mode, the data will appear in the Right Phase of the
FRAME, which will be 16/20/24/32 bits after the FRAME pulse.
REGISTER
ADDRESS
R4
BIT
1
LABEL
ADCLRSWAP
DEFAULT
0
Audio interface
control
DESCRIPTION
Controls whether ADC data appears in
‘right’ or ‘left’ phases of FRAME clock:
0=ADC data appear in ‘left’ phase of
FRAME
1=ADC data appears in ‘right’ phase of
FRAME
4:3
FMT
10
Audio interface Data Format Select:
00=Right Justified
01=Left Justified
2
10=I S format
11= DSP/PCM mode
6:5
WL
10
Word length
00=16 bits
01=20 bits
10=24 bits
11=32 bits (see note)
7
FRAMEP
0
Frame clock polarity
0=normal
1=inverted
DSP Mode – reserved
8
BCP
0
BCLK polarity
0=normal
1=inverted
Table 31 Audio Interface Control
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AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised
below. Each audio interface can be controlled individually.
Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK,
and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with
BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses at
the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks.
REGISTER
ADDRESS
R6
BIT
0
LABEL
MS
DEFAULT
0
Clock
generation
control
DESCRIPTION
Sets the chip to be master over FRAME
and BCLK
0=BCLK and FRAME clock are inputs
1=BCLK and FRAME clock are outputs
generated by the WM8950 (MASTER)
4:2
BCLKDIV
000
Configures the BCLK and FRAME output
frequency, for use when the chip is master
over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
7:5
MCLKDIV
010
Sets the scaling for either the MCLK or
PLL clock output (under control of
CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
8
CLKSEL
1
Controls the source of the clock for all
internal operation:
0=MCLK
1=PLL output
Table 32 Clock Control
COMPANDING
The WM8950 supports A-law and -law companding. Companding can be enabled on the ADC
audio interface by writing the appropriate value to the ADC_COMP register bit.
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REGISTER
ADDRESS
R5
BIT
2:1
LABEL
DEFAULT
ADC_COMP
0
DESCRIPTION
ADC companding
Companding
control
00=off
01=reserved
10=µ-law
11=A-law
Table 33 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out
by ITU-T G.711 standard) for data compression:
-law (where =255 for the U.S. and Japan):
F(x) = ln( 1 + |x|) / ln( 1 + )
-1 ≤ x ≤ 1
A-law (where A=87.6 for Europe):
F(x) = A|x| / ( 1 + lnA)
 for x ≤ 1/A
F(x) = ( 1 + lnA|x|) / (1 + lnA)
 for 1/A ≤ x ≤ 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s
of data.
Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The
input data range is separated into 8 levels, allowing low amplitude signals better precision than that
of high amplitude signals. This is to exploit the operation of the human auditory system, where louder
sounds do not require as much resolution as quieter sounds. The companded signal is an 8-bit word
containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
BIT7
BIT[6:4]
BIT[3:0]
SIGN
EXPONENT
MANTISSA
Table 34 8-bit Companded Word Composition
u-law Companding
1
120
0.9
Companded Output
0.7
80
0.6
0.5
60
0.4
40
0.3
Normalised Output
0.8
100
0.2
20
0.1
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Normalised Input
Figure 24 u-Law Companding
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A-law Companding
1
120
0.9
Companded Output
0.7
80
0.6
0.5
60
0.4
40
0.3
Normalised Output
0.8
100
0.2
20
0.1
0
0
0
0.2
0.4
0.6
0.8
1
Normalised Input
Figure 25 A-Law Companding
AUDIO SAMPLE RATES
The WM8950 sample rate for the ADC is set using the SR register bits. The cutoffs for the digital
filters and the ALC attack/decay times stated are determined using these values and assume a 256fs
master clock rate.
If a sample rate that is not explicitly supported by the SR register settings is required then the closest
SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay
and hold times will scale appropriately.
REGISTER
ADDRESS
R7
BIT
3:1
LABEL
SR
DEFAULT
000
Additional
control
DESCRIPTION
Approximate sample rate (configures the
coefficients for the internal digital filters):
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
Table 35 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8950 has an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate master clocks for the WM8950 audio functions from another external clock, e.g. in
telecoms applications.
Generate and output (on pin CSB/GPIO) a clock for another part of the system that is derived from an
existing audio master clock.
Figure 26 shows the PLL and internal clocking arrangement on the WM8950.
The PLL can be enabled or disabled by the PLLEN register bit.
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REGISTER
ADDRESS
BIT
R1
LABEL
5
PLLEN
DEFAULT
0
DESCRIPTION
PLL enable
Power
management 1
0=PLL off
1=PLL on
Table 36 PLLEN Control Bit
Figure 26 PLL and Clock Select Circuit
The PLL frequency ratio R = f2/f1 (see Figure 26) can be set using the register bits PLLK and PLLN:
PLLN = int R
24
PLLK = int (2 (R-PLLN))
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable
divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz.
R = 98.304 / 12 = 8.192
PLLN = int R = 8
24
k = int ( 2 x (8.192 – 8)) = 3221225 = 3126E9h
REGISTER
ADDRESS
R36
BIT
4
LABEL
PLLPRESCALE
DEFAULT
0
PLL N value
R37
0 = MCLK input not divided (default)
1 = Divide MCLK by 2 before input to
PLL
3:0
PLLN
1000
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
5:0
PLLK [23:18]
0Ch
8:0
PLLK [17:9]
093h
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
8:0
PLLK [8:0]
0E9h
PLL K value 1
R38
DESCRIPTION
PLL K Value 2
R39
PLL K Value 3
Table 37 PLL Frequency Ratio Control
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The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown in Figure 35.
MCLK
(MHz)
(F1)
F2
DESIRED
OUTPUT
(MHz)
PRESCALE POSTSCALE
DIVIDE
(MHz)
R
DIVIDE
N
K
(Hex)
(Hex)
86C220
12
11.2896
90.3168
1
2
7.5264
7
12
12.288
98.304
1
2
8.192
8
3126E8
13
11.2896
90.3168
1
2
6.947446
6
F28BD4
13
12.288
98.304
1
2
7.561846
7
8FD525
14.4
11.2896
90.3168
1
2
6.272
6
45A1CA
D3A06E
14.4
12.288
98.304
1
2
6.826667
6
19.2
11.2896
90.3168
2
2
9.408
9
6872AF
19.2
12.288
98.304
2
2
10.24
A
3D70A3
19.68
11.2896
90.3168
2
2
9.178537
9
2DB492
19.68
12.288
98.304
2
2
9.990243
9
FD809F
19.8
11.2896
90.3168
2
2
9.122909
9
1F76F7
19.8
12.288
98.304
2
2
9.929697
9
EE009E
24
11.2896
90.3168
2
2
7.5264
7
86C226
24
12.288
98.304
2
2
8.192
8
3126E8
26
11.2896
90.3168
2
2
6.947446
6
F28BD4
26
12.288
98.304
2
2
7.561846
7
8FD525
27
11.2896
90.3168
2
2
6.690133
6
BOAC93
27
12.288
98.304
2
2
7.281778
7
482296
Table 38 PLL Frequency Examples
GENERAL PURPOSE INPUT/OUTPUT
The CSB/GPIO pin can be configured to perform a variety of useful tasks by setting the GPIOSEL
register bits. The GPIO is only available in 2 wire mode.
REGISTER
ADDRESS
R8
BIT
2:0
LABEL
GPIOSEL
DEFAULT
000
DESCRIPTION
CSB/GPIO pin function select:
GPIO
000=CSB input
control
001=Reserved
010=Temp ok
011=Amute active
100=PLL clk o/p
101=PLL lock
110=Reserved
111=Reserved
3
GPIOPOL
0
GPIO Polarity invert
0=Non inverted
1=Inverted
5:4
OPCLKDIV
00
PLL Output clock division ratio
00=divide by 1
01=divide by 2
10=divide by 3
11=divide by 4
Table 39 CSB/GPIO Control
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CONTROL INTERFACE
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin
determines the 2 or 3 wire mode as shown in Table 40.
The WM8950 is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each
control register.
MODE
INTERFACE FORMAT
Low
2 wire
High
3 wire
Table 40 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB/GPIO latches in a complete control word consisting of the last 16 bits.
Figure 27 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8950 supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit
address of each register in the WM8950).
The WM8950 operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8950, then the WM8950 responds by pulling SDIN low on the next clock pulse
(ACK). If the address is not recognised or the R/W bit is ‘1’ when operating in write only mode, the
WM8950 returns to the idle condition and wait for a new start condition and valid address.
During a write, once the WM8950 has acknowledged a correct address, the controller sends the first
byte of control data (B15 to B8, i.e. the WM8950 register address plus the first bit of register data).
The WM8950 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The
controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register
data), and the WM8950 acknowledges again by pulling SDIN low.
Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a
complete sequence the WM8950 returns to the idle state and waits for another start condition. If a
start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN
changes while SCLK is high), the device jumps to the idle condition.
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DEVICE ADDRESS
(7 BITS)
SDIN
RD / WR
BIT
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
CONTROL BYTE 1
(BITS 7 TO 0)
ACK
(LOW)
SCLK
START
register address and
1st register data bit
remaining 8 bits of
register data
STOP
Figure 28 2-Wire Serial Control Interface
In 2-wire mode the WM8950 has a fixed device address, 0011010.
RESETTING THE CHIP
The WM8950 can be reset by performing a write of any value to the software reset register (address
0 hex). This will cause all register values to be reset to their default values. In addition to this there
is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the device
is powered up.
POWER SUPPLIES
The WM8950 can use up to three separate power supplies:
AVDD, AVDD2, AGND and AGND2: Analogue supply, powers all analogue functions. AVDD can
range from 2.5V to 3.6V and has the most significant impact on overall power consumption. A large
AVDD slightly improves audio quality.
DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces.
DCVDD can range from 1.71V to 3.6V, and has no effect on audio quality. The return path for
DCVDD is DGND, which is shared with DBVDD.
DBVDD Can range from 1.71V to 3.6V. DBVDD return path is through DGND.
It is possible to use the same supply voltage for all supplies. However, digital and analogue supplies
should be routed and decoupled separately on the PCB to keep digital switching noise out of the
analogue signal paths.
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ADC POWER UP/DOWN SEQUENCE
Vpor_on
Vpora
Vpor_off
Power Supply
DGND
POR
Device Ready
No Power
POR Undefined
Internal POR active
POR
DNC
I2S Clocks
DNC
tadcint
ADC Internal
State
Power down
Init
tadcint
Normal Operation
PD
Init
Normal Operation
tmidrail_on
tmidrail_off
(Note 1)
Analogue Inputs
Power down
(Note 2)
AVDD/2
GD
GD
GD
GD
ADCDAT pin
(Note 3)
ADCEN bit
ADC enabled
ADC off
INPPGAEN bit
VMIDSEL/
BIASEN bits
ADC enabled
INPPGA enabled
(Note 4)
VMID enabled
Figure 29 ADC Power Up and Down Sequence (not to scale)
SYMBOL
MIN
TYPICAL
MAX
UNIT
tmidrail_on
500
tmidrail_off
>10
ms
s
tadcint
2/fs
n/fs
Table 41 Typical POR Operation (typical values, not tested)
Notes:
w
1.
The analogue input pin charge time, tmidrail_on, is determined by the VMID pin charge time. This
time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance
and AVDD power supply rise time.
2.
The analogue input pin discharge time, tmidrail_off, is determined by the analogue input coupling
capacitor discharge time. The time, tmidrail_off, is measured using a 1μF capacitor on the analogue
input but will vary dependent upon the value of input coupling capacitor.
3.
While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system
noise but no significant digital output will be present.
4.
The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for
normal ADC operation.
5.
ADCDAT data output delay from power up - with power supplies starting from 0V - is determined
primarily by the VMID charge time. ADC initialisation and power management bits may be set
immediately after POR is released; VMID charge time will be significantly longer and will dictate
when the device is stabilised for analogue input.
6.
ADCDAT data output delay at power up from device standby (power supplies already applied) is
determined by ADC initialisation time, 2/fs.
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POWER MANAGEMENT
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC digital filters is in 64x oversampling mode. Under the
control of ADCOSR the oversampling rate may be doubled. 64x oversampling results in a slight
decrease in noise performance compared to 128x but lowers the power consumption of the device.
REGISTER
ADDRESS
R14
BIT
LABEL
3
ADCOSR128
DEFAULT
0
DESCRIPTION
ADC oversample rate select
ADC control
0 = 64x (lowest power)
1 = 128x (best SNR)
Table 42 ADC Oversampling Rate Selection
VMID
The analogue circuitry will not work unless VMID is enabled (VMIDSEL≠00). The impedance of the
VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the
startup time of the VMID circuit.
REGISTER
ADDRESS
R1
BIT
1:0
LABEL
DEFAULT
VMIDSEL 00
Power
management 1
DESCRIPTION
Reference string impedance to VMID pin
(detemines startup time):
00=off (open circuit)
01=50kΩ
10=500kΩ
11=5kΩ (for fastest startup)
Table 43 VMID Impedance Control
BIASEN
REGISTER
ADDRESS
R1
BIT
3
LABEL
BIASEN
DEFAULT
0
DESCRIPTION
Analogue amplifier bias control
Power
management 1
Table 44 BIASEN Control
ESTIMATED SUPPLY CURRENTS
When the ADC is enabled it is estimated that approximately 4mA will be drawn from DCVDD when
DCVDD=1.8V and fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an
additional 700 microamps will be drawn from DCVDD.
Table 59 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit.
REGISTER BIT
AVDD CURRENT (MILLIAMPS)
PLLEN
1.4 (with clocks applied)
MICBEN
0.5
BIASEN
0.3
BUFIOEN
0.1
VMIDSEL
10K=>0.3, less than 0.1 for 50k/500k
INPPGAEN
0.2
ADCEN
x64 (ADCOSR=0)=>2.6, x128 (ADCOSR=1)=>4.9
Table 45 AVDD Supply Current
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REGISTER MAP
ADDR
B[15:9]
REGISTER
NAME
B8
B7
B6
B5
B4
B3
B2
B1
B0
DEF’T
VAL
(HEX)
DEC HEX
0
00
Software Reset
1
01
Power manage’t 1
0
0
AUXEN
PLLEN
Software reset
MICBEN
BIASEN
BUFIOEN
2
02
Power manage’t 2
0
0
0
0
BOOSTEN
0
INPPGAEN
0
ADCEN
000
4
04
Audio Interface
BCP
FRAMEP
0
ALRSWAP
0
050
5
05
Companding ctrl
0
0
0
000
6
06
Clock Gen ctrl
CLKSEL
MS
140
7
07
Additional ctrl
0
SLOWCLK
EN
000
8
08
GPIO Stuff
14
0E
ADC Control
WL
FMT
0
0
0
MCLKDIV
0
0
0
0
0
HPFEN
HPFAPP
VMIDSEL
ADC_COMP
BCLKDIV
0
0
0
SR
OPCLKDIV
GPIOPOL
HPFCUT
ADCOSR
000
GPIOSEL
0
0
000
ADCPOL
100
128
15
0F
ADC Digital Vol
0
18
12
EQ1 – low shelf
0
0
EQ1C
ADCVOL
EQ1G
12C
19
13
EQ2 – peak 1
EQ2BW
0
EQ2C
EQ2G
02C
20
14
EQ3 – peak 2
EQ3BW
0
EQ3C
EQ3G
02C
21
15
EQ4 – peak 3
EQ4BW
0
EQ4C
EQ4G
02C
22
16
EQ5 – high shelf
0
0
EQ5C
EQ5G
02C
27
1B
Notch Filter 1
NFU
NFEN
NFA0[13:7]
000
28
1C
Notch Filter 2
NFU
0
NFA0[6:0]
000
29
1D
Notch Filter 3
NFU
0
NFA1[13:7]
000
30
1E
Notch Filter 4
NFU
0
NFA1[6:0]
32
20
ALC control 1
ALCSEL
0
33
21
ALC control 2
ALCZC
34
22
ALC control 3
ALCMODE
35
23
Noise Gate
0
0
0
0
0
36
24
PLL N
0
0
0
0
PLL_PRE
0
0FF
000
ALCMAX
ALCMIN
ALCHLD
ALCDCY
038
ALCLVL
00B
ALCATK
032
NGEN
NGTH
000
PLLN[3:0]
008
SCALE
37
25
PLL K 1
38
26
PLL K 2
PLLK[17:9]
093
39
27
PLL K 3
PLLK[8:0]
0E9
44
2C
Input ctrl
45
2D
INP PGA gain ctrl
0
MBVSEL
0
0
0
INPPGAZC
0
PLLK[23:18]
0
0
0
INPPGA
AUXMODE
00C
AUX2
MICN2
MICP2
INPPGA
INPPGA
INPPGA
INPPGAVOL
003
010
MUTE
47
2F
ADC Boost ctrl
49
31
Thermal Shutdown
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PGABOOST
0
0
0
MICP2BOOSTVOL
0
0
0
0
0
AUX2BOOSTVOL
0
TSDEN
100
0
002
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DIGITAL FILTER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Filter
Passband
+/- 0.025dB
0
-6dB
0.454fs
0.5fs
Passband Ripple
+/- 0.025
Stopband
Stopband Attenuation
dB
0.546fs
f > 0.546fs
-60
Group Delay
dB
21/fs
ADC High Pass Filter
High Pass Filter Corner
Frequency
-3dB
3.7
-0.5dB
10.4
-0.1dB
21.6
Hz
Table 46 Digital Filter Characteristics
TERMINOLOGY
1.
Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2.
Pass-band Ripple – any variation of the frequency response in the pass-band region
3.
Note that this delay applies only to the filters and does not include additional delays through other digital circuits. See
Table 47 for the total delay.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Path Group Delay
Total Delay (ADC analogue
input to digital audio interface
output)
EQ disabled
26/fs
28/fs
30/fs
EQ enabled
27/fs
29/fs
31/fs
Table 47 Total Group Delay
Note:
1.
Wind noise filter is disabled.
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ADC FILTER RESPONSES
0.2
0
0.15
0.1
Response (dB)
Response (dB)
-20
-40
-60
-80
0.05
0
-0.05
-0.1
-100
-0.15
-0.2
-120
0
0.5
1
1.5
2
Frequency (Fs)
Figure 30 ADC Digital Filter Frequency Response
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2.5
3
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 31 ADC Digital Filter Ripple
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DE-EMPHASIS FILTER RESPONSES
0
0.30
-1
0.25
-2
0.20
Response (dB)
Response (dB)
-3
-4
-5
-6
-7
0.15
0.10
0.05
0.00
-8
-0.05
-9
-0.10
-10
-0.15
0
2000
4000
6000
8000
10000
12000
14000
16000
0
2000
4000
Frequency (Hz)
Figure 32 De-emphasis Frequency Response (32kHz)
8000
10000
12000
14000
16000
Figure 33 De-emphasis Error (32kHz)
0.10
0
-1
0.05
-2
Response (dB)
-3
Response (dB)
6000
Frequency (Hz)
-4
-5
-6
-7
-8
0.00
-0.05
-0.10
-0.15
-9
-0.20
-10
0
5000
10000
15000
0
20000
5000
Figure 34 De-emphasis Frequency Response (44.1kHz)
15000
20000
Figure 35 De-emphasis Error (44.1kHz)
0
0.10
-1
0.08
-2
0.06
-3
0.04
Response (dB)
Response (dB)
10000
Frequency (Hz)
Frequency (Hz)
-4
-5
-6
-7
0.02
0.00
-0.02
-0.04
-8
-0.06
-9
-0.08
-10
-0.10
0
5000
10000
15000
20000
Frequency (Hz)
Figure 36 De-emphasis Frequency Response (48kHz)
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0
5000
10000
15000
20000
Frequency (Hz)
Figure 37 De-emphasis Error (48kHz)
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HIGHPASS FILTER
The WM8950 has a selectable digital highpass filter in the ADC filter path. This filter has two modes,
st
audio and applications. In audio mode the filter is a 1 order IIR with a cut-off of around 3.7Hz. In
nd
applications mode the filter is a 2 order high pass filter with a selectable cut-off frequency.
5
10
0
0
-5
-10
-15
Response (dB)
Response (dB)
-10
-20
-25
-30
-35
-20
-30
-40
-40
0
5
10
15
20
25
30
35
40
45
-50
Frequency (Hz)
-60
0
200
400
600
800
1000
1200
Frequency (Hz)
Figure 38 ADC Highpass Filter Response, HPFAPP=0
Figure 39 ADC Highpass Filter Responses (48kHz),
HPFAPP=1, all cut-off settings shown.
10
10
0
0
-10
-10
-20
Response (dB)
Response (dB)
-20
-30
-40
-30
-40
-50
-60
-50
-70
-60
-80
-70
-90
0
-80
200
400
600
800
1000
1200
Frequency (Hz)
0
200
400
600
800
1000
1200
Frequency (Hz)
Figure 40 ADC Highpass Filter Responses (24kHz),
HPFAPP=1, all cut-off settings shown.
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Figure 41 ADC Highpass Filter Responses (12kHz),
HPFAPP=1, all cut-off settings shown.
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5-BAND EQUALISER
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
The WM8950 has a 5-band equaliser which can be applied to the ADC path. The plots from Figure
42 to Figure 55 show the frequency responses of each filter with a sampling frequency of 48kHz,
firstly showing the different cut-off/centre frequencies with a gain of 12dB, and secondly a sweep of
the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each filter.
0
0
-5
-5
-10
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
-15
-1
10
5
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
Figure 42 EQ Band 1 – Low Frequency Shelf Filter Cut-offs Figure 43 EQ Band 1 – Gains for Lowest Cut-off Frequency
0
0
-5
-5
-10
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 44 EQ Band 2 – Peak Filter Centre Frequencies,
EQ2BW=0
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 45 EQ Band 2 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ2BW=0
15
10
Magnitude (dB)
5
0
-5
-10
-15
-2
10
10
-1
10
0
1
10
Frequency (Hz)
10
2
10
3
10
4
Figure 46 EQ Band 2 – EQ2BW=0, EQ2BW=1
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PD, Rev 4.4, November 2011
55
Production Data
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
WM8950
0
0
-5
-5
-10
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 47 EQ Band 3 – Peak Filter Centre Frequencies,
EQ3BW=0
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 48 EQ Band 3 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ3BW=0
15
10
Magnitude (dB)
5
0
-5
-10
-15
-2
10
Figure 49
10
-1
10
0
1
10
Frequency (Hz)
10
2
10
3
10
4
EQ Band 3 – EQ3BW=0, EQ3BW=1
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56
WM8950
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
Production Data
0
0
-5
-5
-10
-10
-15
-1
10
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
-15
-1
10
5
Figure 50 EQ Band 4 – Peak Filter Centre Frequencies,
EQ3BW=0
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Figure 51 EQ Band 4 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ4BW=0
15
10
Magnitude (dB)
5
0
-5
-10
-15
-2
10
-1
10
0
1
10
Frequency (Hz)
10
2
10
3
10
4
EQ Band 4 – EQ3BW=0, EQ3BW=1
15
15
10
10
5
5
Magnitude (dB)
Magnitude (dB)
Figure 52
10
0
0
-5
-5
-10
-10
-15
-1
10
Figure 53
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
-15
-1
10
EQ Band 5 – High Frequency Shelf Filter Cut-offs Figure 54
w
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
EQ Band 5 – Gains for Lowest Cut-off Frequency
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WM8950
Production Data
Figure 55 shows the result of having the gain set on more than one channel simultaneously. The
blue traces show each band (lowest cut-off/centre frequency) with 12dB gain. The red traces show
the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EQxBW=0 for the
peak filters.
20
15
Magnitude (dB)
10
5
0
-5
-10
-15
-1
10
Figure 55
w
10
0
10
1
2
10
Frequency (Hz)
10
3
10
4
10
5
Cumulative Frequency Boost/Cut
PD, Rev 4.4, November 2011
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Production Data
WM8950
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 56
Recommended External Components
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WM8950
Production Data
PACKAGE DIAGRAM
FL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.9 mm BODY, 0.50 mm LEAD PITCH
DETAIL 1
D2
19
DM102.C
D
24
1
18
EXPOSED
GROUND 6
PADDLE
INDEX AREA
(D/2 X E/2)
4
E2
E
SEE DETAIL 2
13
6
2X
12
b7
e
1
bbb M C A B
2X
aaa C
aaa C
TOP VIEW
BOTTOM VIEW
ccc C
DETAIL 1
DETAIL 2
A
0.08 C
C
45°
A1
SIDE VIEW
SEATING PLANE M
Datum
0.30mm
DETAIL 3
M
L
5
1
A3
EXPOSED
GROUND
PADDLE
Terminal
Tip
e/2
e
W
Exposed lead
T
A3
G
H
Half etch tie bar
b
DETAIL 3
Symbols
A
A1
A3
b
D
D2
E
E2
e
G
H
L
T
W
MIN
0.80
0
0.20
2.40
2.40
0.35
Dimensions (mm)
NOM
MAX
NOTE
0.85
0.90
0.035
0.05
0.203 REF
1
0.25
0.30
4.00 BSC
2.50
4.00 BSC
2.50
0.50 BSC
0.20
0.10
0.40
0.103
0.15
2.60
2
2.60
2
0.45
Tolerances of Form and Position
aaa
bbb
ccc
REF:
0.10
0.10
0.10
JEDEC, MO-220, VARIATION VGGD-8.
NOTES:
1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.
2. FALLS WITHIN JEDEC, MO-220, VARIATION VGGD-8.
3. ALL DIMENSIONS ARE IN MILLIMETRES.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002.
5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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60
Production Data
WM8950
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product
design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such
selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any
use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual
property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might
be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval,
licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective
third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not
liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted
at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed
thereon by any person.
ADDRESS
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
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Production Data
REVISION HISTORY
DATE
REV
ORIGINATOR
26/09/11
4.4
JMacD
Order codes changed from WM8950GEFL/V and WM8950GEFL/RV to
WM8950CGEFL/V and WM8950CGEFL/RV to reflect change to copper wire
bonding.
26/09/11
4.4
JMacD
Package diagram changed to DM102.C
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CHANGES
PD, Rev 4.4, November 2011
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