w WM8782A 24-Bit, 192kHz Stereo ADC DESCRIPTION FEATURES The WM8782A is a high performance, low cost stereo audio ADC designed for recordable media applications. • • • SNR 100dB (‘A’ weighted @ 48kHz) THD -93dB (at –1dB) Sampling Frequency: 8 – 192kHz • • Slave Clocking Mode System Clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs Audio Data Interface Modes 16-24 bit I2S, 16-24 bit Left, 16-24 bit Right Justified The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow operation of the audio interface in three industry standard modes. An internal op-amp is integrated on the front end of the chip to accommodate analogue input signals greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets. WM8782A offers a Slave mode clocking scheme. A stereo 24-bit multi-bit sigma-delta ADC is used with 128x, 64x or 32x over-sampling, according to sample rate. Digital audio output word lengths from 16-24 bits and sampling rates from 8kHz to 192kHz are supported. • • Supply Voltages Analogue: 2.7 to 5.5V Digital core: 2.7V to 3.6V • • 20-lead SSOP package Accelerated Lifetime Screened Devices available. The device is a hardware controlled device and is supplied in a 20-lead SSOP. APPLICATIONS The device is available over a functional temperature range of -40°C to +85°C • • • • • Recordable DVD Players Personal Video Recorders STB Studio Audio Processing Equipment Automotive WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews I WL F SAMPEN M /S F ORM AT VR EFGN D VR EFP AVD D VM ID DVD D D GND AGN D BLOCK DIAGRAM Production Data, April 2010, Rev 4.8 Copyright ©2010 Wolfson Microelectronics plc WM8782A Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION ........................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ......................................................................... 5 THERMAL PERFORMANCE ................................................................................. 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 ELECTRICAL CHARACTERISTICS ...................................................................... 6 TERMINOLOGY............................................................................................................. 7 SIGNAL TIMING REQUIREMENTS ....................................................................... 8 SYSTEM CLOCK TIMING .............................................................................................. 8 AUDIO INTERFACE TIMING – SLAVE MODE .............................................................. 9 DEVICE DESCRIPTION ....................................................................................... 10 INTRODUCTION.......................................................................................................... 10 ADC ............................................................................................................................. 10 ADC DIGITAL FILTER ................................................................................................. 10 DIGITAL AUDIO INTERFACE ...................................................................................... 11 POWER ON RESET .................................................................................................... 14 DIGITAL FILTER CHARACTERISTICS ............................................................... 16 ADC FILTER RESPONSES ......................................................................................... 16 ADC HIGH PASS FILTER ............................................................................................ 17 APPLICATIONS INFORMATION ......................................................................... 18 RECOMMENDED EXTERNAL COMPONENTS........................................................... 18 RECOMMENDED EXTERNAL COMPONENTS VALUES............................................ 18 PACKAGE DIMENSIONS .................................................................................... 19 IMPORTANT NOTICE.................................................................................................. 20 ADDRESS: ................................................................................................................... 20 w PD, April 2010, Rev 4.8 2 WM8782A Production Data PIN CONFIGURATION MCLK 1 20 M/S DOUT 2 19 AINL LRCLK 3 18 AINOPL DGND 4 17 COM DVDD 5 16 AINR BCLK 6 15 AINOPR IWL 7 14 AGND FSAMPEN 8 13 AVDD FORMAT 9 12 VREFP 10 11 VREFGND VMID ORDERING INFORMATION DEVICE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8782ASEDS/V -40°C to +85°C 20-lead SSOP (Pb-free) MSL2 260oC WM8782ASEDS/RV -40°C to +85°C 20-lead SSOP (Pb-free, tape and reel) MSL2 260 C o Note: Reel quantity = 2,000 w PD, April 2010, Rev 4.8 3 WM8782A Production Data PIN DESCRIPTION NAME TYPE DESCRIPTION PIN NO. 1 MCLK Digital Input 2 DOUT Digital Output 3 LRCLK Digital Input DGND Supply DVDD Supply 6 BCLK Digital Input 7 IWL Digital Tristate Input Word Length 0 = 16 bit 1 = 20 bit Z = 24 bit 8 FSAMPEN Digital Tristate Input Fast Sampling Rate Enable 0 = 48kHz 1= 96kkHz Z= 192kHz 9 FORMAT Digital Tristate Input Audio Mode Select 0 = RJ 1 = LJ Z = I2S 10 VMID Analogue Output 11 VREFGND Supply 12 VREFP Analogue Output 13 AVDD Supply Analogue Positive Supply 14 AGND Supply Analogue Negative Supply and Substrate Connection 15 AINOPR Analogue Output 16 AINR Analogue Input Right Channel Input Common mode high impedance input should be set to midrail. 4 5 17 COM Analogue Input 18 AINOPL Analogue Output 19 AINL Analogue Input 20 M/S Digital Input w Master Clock ADC Digital Audio Data Audio Interface Left / Right Clock Digital Negative Supply Digital Positive Supply Audio Interface Bit Clock Mid rail Voltage Decoupling Capacitor Negative Supply and Substrate Connection Positive Reference Voltage Decoupling Pin; 10uF external decoupling Right Channel Internal Op-Amp Output Left Channel Internal Op-Amp Output Left Channel Input Interface Mode Select 0 = Slave mode (128fs, 192fs, 256fs, 384fs, 512fs, 768fs) 1 = Reserved (fs=word clock frequency) PD, April 2010, Rev 4.8 4 WM8782A Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level is specified in Ordering Information. CONDITION Digital supply voltage Analogue supply voltage MIN MAX -0.3V +4.5V -0.3V +7V Voltage range digital inputs DGND -0.3V DVDD + 0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Ambient temperature (supplies applied) -55°C +125°C Storage temperature -65°C +150°C Pb free package body temperature (reflow 10 seconds) +260°C Package body temperature (soldering 2 minutes) +183°C Notes: 1. Analogue and digital grounds must always be within 0.3V of each other. THERMAL PERFORMANCE PARAMETER Thermal resistance – junction to ambient SYMBOL RθJA TEST CONDITIONS MIN TYP MAX 81 See note 1 UNIT °C/W Notes: 1. Figure given for package mounted on 4-layer FR4 according to JESD51-7. (No forced air flow is assumed). 2. Thermal performance figures are estimated. w PD, April 2010, Rev 4.8 5 WM8782A Production Data RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN Digital supply range DVDD WM8782SEDS, WM8782SEDS/R 2.7 3.6 V Analogue supply range AVDD WM8782SEDS, WM8782SEDS/R 2.7 5.5 V WM8782SEDS, WM8782SEDS/R -40 +85 °C Ground TYP DGND,AGND Operating temperature range TA MAX 0 UNIT V Notes: 1. Digital supply DVDD must never be more than 0.3V greater than AVDD. ELECTRICAL CHARACTERISTICS Test Conditions DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ADC Performance – WM8782SEDS, WM8782SEDS/R (+25˚C) Full Scale Input Signal Level (for ADC 0dB Input) 1.0 Vrms Input resistance, using recommended external resistor network on p22. 10 kΩ Input capacitance Signal to Noise Ratio (see Terminology note 1,2,4) Signal to Noise Ratio (see Terminology note 1,2,4) Total Harmonic Distortion Dynamic Range SNR SNR THD DNR 20 pF 100 dB Unweighted, @ fs = 48kHz 98 dB weighted, @ fs = 48kHz, AVDD = 3.3V 98 dB weighted, @ fs = 96kHz 98 dB Unweighted, @ fs = 96kHz 98 dB weighted, @ fs = 96kHz AVDD = 3.3V 98 dB 1kHz, -1dB Full Scale @ fs = 48kHz -93 dB 1kHz, -1dB Full Scale @ fs = 96kHz -93 dB 1kHz, -1dB Full Scale @ fs = 192kHz -92 dB weighted, @ fs = 48kHz -60dBFS 93 93 100 dB 90 dB Channel Separation (see Terminology note 4) 1kHz Input Channel Level Matching 1kHz signal 0.1 dB Channel Phase Deviation 1kHz signal 0.0001 Degree 1kHz 100mVpp, applied to AVDD, DVDD 50 dB Power Supply Rejection Ratio w PSRR PD, April 2010, Rev 4.8 6 WM8782A Production Data Test Conditions DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (TTL Levels) Input LOW level VIL Input HIGH level VIH 0.8 V +1 μA 2.0 Input leakage current – digital pad -1 Input leakage current – digital tristate input (Note 3) V ±0.2 85 Input capacitance μA 5 Output LOW VOL IOL=1mA Output HIGH VOH IOH= -1mA 0.9 x DVDD VMID AVDD to VMID and VMID to VREFN –4% AVDD/2 –4% AVDD/2 pF 0.1 x DVDD V V Analogue Reference Levels Midrail Reference Voltage Potential Divider Resistance RVMID Buffered Reference Voltage VREFP +4% V 70 kΩ +4% V VREF source current IVREF 5 mA VREF sink current IVREF 5 mA Supply Current Analogue supply current Digital supply current AVDD = 5V 26 mA DVDD = 3.3V 5 mA 0.5 mA Power Down Notes: 1. All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible, it may affect dynamic specification values. 2. VMID is decoupled with 10uF and 0.1uF capacitors close to the device package. Smaller capacitors may reduce performance. 3. This high leakage current is due to the topology of the instate pads. The pad input is connected to the midpoint of an internal resistor string to pull input to vmid if undriven. TERMINOLOGY 1. Signal-to-noise ratio (dB) – Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, over a 20Hz to 20kHz bandwidth. (No Auto-zero or Automute function is employed in achieving these results). 2. Dynamic range (dB) – DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. THD+N (dB) – THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. 4. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. w PD, April 2010, Rev 4.8 7 WM8782A Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING Figure 1 System Clock Timing Requirements Test Conditions o DVDD = 3.3V, DGND = 0V, TA = +25 C, fs = 48kHz, Slave Mode, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT MCLK System clock pulse width high TMCLKL 11 MCLK System clock pulse width low TMCLKH 11 ns MCLK System clock cycle time TMCLKY 28 ns MCLK duty cycle TMCLKDS 40:60 System Clock Timing Information ns 60:40 Table 1 Master Clock Timing Requirements w PD, April 2010, Rev 4.8 8 WM8782A Production Data AUDIO INTERFACE TIMING – SLAVE MODE Figure 2 Digital Audio Data Timing – Slave Mode Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 10 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DOUT propagation delay from BCLK falling edge tDD 0 10 ns Table 2 Digital Audio Data Timing – Slave Mode Note: LRCLK should be synchronous with MCLK, although the WM8782A interface is tolerant of phase variations or jitter on these signals. w PD, April 2010, Rev 4.8 9 WM8782A Production Data DEVICE DESCRIPTION INTRODUCTION The WM8782A is a stereo 24-bit ADC designed for demanding recording applications such as DVD recorders, studio mixers, PVRs, and AV amplifiers. The WM8782A consists of stereo line level inputs, followed by a sigma-delta modulator and digital filtering. The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow operation of the audio interface in three industry standard modes (left justified, right justified or I2S) . An internal op-amp is integrated on the front end of the chip to accommodate analogue input signals greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets. The WM8782A offers Slave mode clocking schemes. The WM8782A supports master clock rates from 128fs to 768fs and digital audio output word lengths from 16-24 bits. Sampling rates from 8kHz to 192kHz are supported, delivering high SNR operating with 128x, 64x or 32x over-sampling, according to the sample rate. The line inputs are biased internally through the operational amplifier to VMID. ADC The WM8782A uses a multi-bit over sampled sigma-delta ADC. A single channel of the ADC is illustrated in Figure 3 Multi-Bit Oversampling Sigma Delta ADC Schematic. LIN/RIN ANALOG INTEGRATOR TO ADC DIGITAL FILTERS MULTI BITS Figure 3 Multi-Bit Oversampling Sigma Delta ADC Schematic The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input is 1.0V rms at AVDD = 5.0 volts. Any input voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input has a linear relationship with AVDD. The internal op-amp and appropriate resistors can be used to reduce signals greater than 1Vrms before they reach the ADC. The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. ADC OUTPUT PHASE In the input to output data-path, the digital output data DOUT, is a phase inverted representation of the analogue input signal. ADC DIGITAL FILTER The ADC digital filters contain a digital high pass filter. The high-pass filter response detailed in Digital Filter Characteristics. The operation of the high pass filter removes residual DC offsets that are present on the audio signal. . w PD, April 2010, Rev 4.8 10 WM8782A Production Data DIGITAL AUDIO INTERFACE The digital audio interface uses three pins: • • • DOUT: ADC data output LRCLK: ADC data alignment clock BCLK: Bit clock, for synchronisation The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always an output. BCLK and LRCLK are always inputs. Three different audio data formats are supported: • • Left justified Right justified • I 2S SLAVE MODE OPERATION The WM8782A can be configured as a slave mode device. In slave mode, the WM8782A responds with data to clocks it receives over the digital audio interface. The mode is selected by setting the MS input pin (see Table 3 Slave selection below). Slave mode is illustrated below. Figure 4 Slave Mode PIN M/S DESCRIPTION Slave Selection 0 = Slave Mode 1= Reserved Table 3 Slave selection AUDIO INTERFACE CONTROL The Input Word Length and Audio Format mode can be selected by using IWL and FORMAT pins. PIN DESCRIPTION IWL Word Length 0 = 16 bit 1 = 20 bit Z = 24 bit FORMAT Audio Mode Select 0 = RJ 1 = LJ Z = I2S Table 4 Audio Data Format Control w PD, April 2010, Rev 4.8 11 WM8782A Production Data AUDIO DATA FORMATS In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. Figure 5 Left Justified Audio Interface (assuming n-bit word length) In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition. Figure 6 Right Justified Audio Interface (assuming n-bit word length) 2 In I S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. Figure 7 I2S Audio Interface (assuming n-bit word length) w PD, April 2010, Rev 4.8 12 WM8782A Production Data MASTER CLOCK AND AUDIO SAMPLE RATES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock (MCLK). The external master system clock can be applied directly through the MCLK input pin. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8782A supports master clocks of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs, where fs is the audio sampling frequency (LRCLK). In Slave Mode, the WM8782A automatically detects the audio sample rate. Table 5 shows the common MCLK frequencies for different sample rates. SAMPLING RATE (LRCLK) Master Clock Frequency (MHz) 128fs 192fs 256fs 384fs 512fs 768fs 8kHz 1.024 1.536 2.048 3.072 4.096 6.144 16kHz 2.048 3.072 4.096 6.144 8.192 12.288 32kHz 4.096 6.144 8.192 12.288 16.384 24.576 44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 36.864 48kHz 6.144 9.216 12.288 18.432 24.576 96kHz 12.288 18.432 24.576 36.864 - - 192kHz 24.576 36.864 - - - - Table 5 Master Clock Frequency Selection In Slave mode, the WM8782A has a master detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is a greater than 32 clocks error the interface sets itself to the highest rate available (768fs). There must be a fixed number of MCLKS per LRCLK, although the WM8782A is tolerant of phase variations or jitter on these clocks. FSAMPEN The FSAMPEN pin controls the over sampling rate of the ADC. The WM8782A can operate at sample rates from 8kHz to 192kHz. The WM8782A uses a sigma-delta modulator that operates at an optimal frequency of 6.144MHz. By default the WM8782A generates the ADC frequency at 128xOSR. At fs=48kHz, the ADC frequency is 128xOSR = 128x48kHz = 6.144MHz. If fs=96KHz, the FSAMPEN pin must be set to 1. In this case, the ADC frequency is 64xOSR = 64x96kHz = 6.144MHz. If fs=192KHz, the FSAMPEN pin must be set to z. In this case, the ADC frequency is 32xOSR = 32x192kHz = 6.144MHz. PIN FSAMPEN DESCRIPTION Fast sampling rate enable 0 = 48ken (128x OSR) 1= 96ken (64x OSR) z= 192ken (32x OSR) Table 6 Sampling Rate Enable Selection w PD, April 2010, Rev 4.8 13 WM8782A Production Data POWER DOWN CONTROL The WM8782A can be powered down by stopping MCLK. Power down mode using MCLK is entered after 65536/fs clocks. On power-up, the WM8782A applies the power-on reset sequence described below. When MCLK is stopped DOUT is forced to zero. POWER ON RESET Figure 8 Power Supply Timing Requirements – Power-on Figure 9 Power Supply Timing Requirements – Power-down w PD, April 2010, Rev 4.8 14 WM8782A Production Data Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = DGND = 0V, TA = +25°C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Power Supply Input Timing Information DVDD level to activate POR – power on Vpora Measured from DGND 0.7 V AVDD level to activate POR – power on Vpora Measured from AGND 0.7 V VMID level to activate POR – power on Vpora Measured from AGND 0.7 V DVDD level to release POR – power on (see notes 1 and 2) Vporr Measured from DGND DVDD Min V AVDD level to release POR – power on (see notes 1 and 2) Vporr Measured from AGND AVDD Min V VMID level to release POR – power on (see notes 1 and 2) Vporr Measured from AGND 1 V POR active period (see notes 1 and 2) tpor Measured from POR active to POR release DVDD level to activate POR – power off (see note 5) Vpor_off Measured from DGND 0.8 V AVDD level to activate POR – power off (see note 5) Vpor_off Measured from AGND 0.8 V VMID level to activate POR – power off (see note 5) Vpor_off Measured from AGND 0.7 V Power on – POR propagation delay through device tpon Measured from rising EDGE of POR 30 μs Power down – POR propagation delay through device tpoff Measured from falling EDGE of POR 30 μs 30 (note 6) Defined by DVDD/AVDD/ VMID Rise Time μs Notes: 1. 2. 3. 4. 5. 6. POR is activated when DVDD or AVDD or VMID reach their stated Vpora level (Figure 8) POR is only released when DVDD and AVDD and VMID have all reached their stated Vporr levels (Figure 8). The rate of rise of VMID depends on the rate of rise of AVDD, the internal 50kΩ resistance and the external decoupling capacitor. Typical tolerance of 50K resistor can be taken as +/-20%. If AVDD, DVDD or VMID suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below Vpor_off,), then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. The chip will enter reset at power down when AVDD or DVDD or VMID falls below Vpor_off. This may be important if the supply is turned on and off frequently by a power management system. The minimum tpor period is maintained even if DVDD, AVDD and VMID have zero rise time. This specification is guaranteed by design rather than test. w PD, April 2010, Rev 4.8 15 WM8782A Production Data DIGITAL FILTER CHARACTERISTICS The WM8782A digital filter characteristics scale with sample rate. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Sample Rate (Single Rate – 48Hz typically) Passband +/- 0.01dB 0 0.4535fs -6dB 0.4892fs Passband Ripple +/- 0.01 Stopband dB 0.5465fs Stopband Attenuation f > 0.5465fs -65 dB Group Delay 22 fs ADC Sample Rate (Dual Rate – 96kHz typically) Passband +/- 0.01dB 0 0.4535fs -6dB 0.4892fs Passband Ripple +/- 0.01 Stopband dB 0.5465fs Stopband Attenuation f > 0.5465fs -65 dB Group Delay 22 fs Table 7 Digital Filter Characteristics ADC FILTER RESPONSES 0.02 0 0.015 0.01 Response (dB) Response (dB) -20 -40 0.005 0 -0.005 -60 -0.01 -0.015 -80 -0.02 0 0.5 1 1.5 Frequency (Fs) 2 Figure 10 Digital Filter Frequency Response w 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 11 ADC Digital Filter Ripple PD, April 2010, Rev 4.8 16 WM8782A Production Data ADC HIGH PASS FILTER The WM8782A has a digital highpass filter to remove DC offsets. The filter response is characterised by the following polynomial. H(z) = 1 - z-1 1 - 0.9995z-1 Response (dB) 0 -5 -10 -15 0 0.0005 0.001 Frequency (Fs) 0.0015 0.002 Figure 12 ADC Highpass Filter Response w PD, April 2010, Rev 4.8 17 WM8782A Production Data APPLICATIONS INFORMATION + + RECOMMENDED EXTERNAL COMPONENTS Figure 13 External Components Diagram RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT REFERENCE SUGGESTED VALUE DESCRIPTION C1 and C8 10μF De-coupling for DVDD and AVDD C2 and C7 0.1μF De-coupling for DVDD and AVDD C5 and C6 10μF Analogue input AC coupling caps R1 10kΩ Current limiting resistors R2 and R5 10kΩ Internal op-amp input resistor R3 and R6 5kΩ R4 3.3kΩ Common mode resistor C4 0.1μF Reference de-coupling capacitors for VMID pin C3 10μF C9 0.1μF C10 10μF Internal op-amp feedback resistor Reference de-coupling capacitors for VREFP pin Table 8 External Components Description The above Table 8 shows resistor values which will give a gain of 0.5. This assumes an input signal of 2Vrms to C4 and C5. w PD, April 2010, Rev 4.8 18 WM8782A Production Data PACKAGE DIMENSIONS DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm) b DM0015.C e 20 11 E1 1 A A2 D E GAUGE PLANE 10 c A1 Θ L 0.25 L1 -C0.10 C Symbols A A1 A2 b c D e E E1 L L1 θ MIN ----0.05 1.65 0.22 0.09 6.90 7.40 5.00 0.55 o 0 REF: Dimensions (mm) NOM --------1.75 0.30 ----7.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 SEATING PLANE MAX 2.0 ----1.85 0.38 0.25 7.50 8.20 5.60 0.95 o 8 JEDEC.95, MO -150 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. w PD, April 2010, Rev 4.8 19 WM8782A Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 2000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w PD, April 2010, Rev 4.8 20