CDB4391 Evaluation Board Data Sheet

CDB4391
Evaluation Board for CS4391
Features
Description
l Demonstrates
The CDB4391 evaluation board is an excellent means
for quickly evaluating the CS4391 24-bit, stereo D/A converter. Evaluation requires an analog signal analyzer, a
digital signal source, a PC for controlling the CS4391 (for
control port mode only) and a power supply. Analog line
level outputs are provided via RCA phono jacks.
recommended layout and
grounding arrangements
l CS8414 receives AES/EBU, S/PDIF, & EIAJ340 compatible digital audio
l Digital and analog patch areas
l Requires only a digital signal source and
power supplies for a complete Digital-toAnalog-Converter system
The CS8414 digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog
converter and will accept AES/EBU, S/PDIF, and EIAJ340 compatible audio data. The evaluation board may
also be configured to accept external timing and data
signals for operation in a user application during system
development.
ORDERING INFORMATION
CDB4391
Evaluation Board
I/O for
Clocks
and Data
Control
Port
Channel A
Output and Mute
CS8414
Digital
Audio
Interface
CS4391
Channel B
Output and Mute
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 2000
(All Rights Reserved)
MAR ‘00
DS335DB2
1
CDB4391
TABLE OF CONTENTS
1. CDB4391 SYSTEM OVERVIEW .............................................................................................. 3
2. CS4391 DIGITAL TO ANALOG CONVERTER ........................................................................ 3
3. CS8414 DIGITAL AUDIO RECEIVER ...................................................................................... 3
4. CS8414 DATA FORMAT .......................................................................................................... 3
5. INPUT/OUTPUT FOR CLOCKS AND DATA ........................................................................... 4
6. POWER SUPPLY CIRCUITRY ................................................................................................. 4
7. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 4
8. CONTROL PORT SOFTWARE ................................................................................................ 4
9. DSD OPERATION .................................................................................................................... 4
10. ERRATA FOR THE REVISION A CIRCUIT BOARD ............................................................ 4
11. PACKING LIST FOR CDB4391 ............................................................................................ 21
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow .......................................................................... 8
Figure 2. CS4391 and Level Shift ................................................................................................... 9
Figure 3. Channel B Audio Output and Mute Circuit ..................................................................... 10
Figure 4. Channel A Audio Output and Mute Circuit ..................................................................... 11
Figure 5. CS8414 Digital Audio Receiver...................................................................................... 12
Figure 6. Digital Audio Inputs ........................................................................................................ 13
Figure 7. Reset Circuit................................................................................................................... 14
Figure 8. Control Port Interface ..................................................................................................... 15
Figure 9. I/O for Clocks and Data.................................................................................................. 16
Figure 10. Power Supply ............................................................................................................... 17
Figure 11. Silkscreen Top ............................................................................................................. 18
Figure 12. Top Side....................................................................................................................... 19
Figure 13. Bottom Side.................................................................................................................. 20
LIST OF TABLES
Table 1. CS8414 Supported Formats.............................................................................................. 3
Table 2. System Connections ......................................................................................................... 5
Table 3. CDB4391 Jumper and Switch settings - STAND-ALONE MODE ..................................... 6
Table 4. CDB4391 Jumper and Switch settings - CONTOL PORT MODE..................................... 7
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
I2C is a registered trademark of Philips Semiconductors.
SPI is a registered trademark of International Business Machines Corporation.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS335DB2
CDB4391
1. CDB4391 SYSTEM OVERVIEW
The CDB4391 evaluation board is an excellent
means of quickly evaluating the CS4391. The
CS8414 digital audio interface receiver provides an
easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to
supply clocks and data through a 10-pin header for
system development.
The CDB4391 schematic has been partitioned into
9 schematics shown in Figures 2 through 10. Each
partitioned schematic is represented in the system
diagram shown in Figure 1. Notice that the system
diagram also includes the interconnections between the partitioned schematics.
2. CS4391 DIGITAL TO ANALOG
CONVERTER
A description of the CS4391 is included in the
CS4391 datasheet.
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard
S/PDIF data format using a CS8414 Digital Audio
Receiver, Figure 5. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock
(FSYNC), de-emphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital audio interface are included in
the CS8414 datasheet.
During normal operation, the CS8414 operates in
the Channel Status mode where the LED’s display
channel status information for the channel selected
by the CSLR/FCK jumper. This allows the CS8414
to decode the de-emphasis bit from the digital audio interface for control of the CS4391 de-emphasis filter, when the CS4391 is in stand-alone mode.
When the Error Information Switch is activated,
the CS8414 operates in the Error and Frequency information mode. The information displayed by the
LED’s can be decoded by consulting the CS8414
DS335DB2
datasheet. It is likely that the de-emphasis control
for the CS4391 will be erroneous and produce an
incorrect audio output if the Error Information
Switch is activated and the CS4391 is in the standalone mode with internal serial clock mode selected.
Encoded sample frequency information can be displayed provided a proper clock is being applied to
the FCK pin of the CS8414. When an LED is lit,
this indicates a "1" on the corresponding pin located on the CS8414. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L
nor R option of CSLR/FCK should be selected if
the FCK pin is being driven by a clock signal.
The evaluation board has been designed such that
the input can be either optical or coax, see Figure 6.
However, both inputs cannot be driven simultaneously.
4. CS8414 DATA FORMAT
The CS8414 data format can be set with switches
M0, M1, M2, and M3, as described in the CS8414
datasheet. The format selected must be compatible
with the data format of the CS4391, as shown in the
CS4391 datasheet. Please note that the CS8414
does not support all the possible modes of the
CS4391 and the Left-Justified Format for the
CS8414 and the CS4391 have incompatible serial
clocks, see Table 1. The default settings for M0-M3
on the evaluation board are given in Tables 3-4.
CS4391 CP Mode
Format
0
1
2
3
4
5
CS4391 SA
Mode Format
0
1
2
3
-
CS8414
Format
Unsupported
2
5
Unsupported
Unsupported
6
Table 1. CS8414 Supported Formats
3
CDB4391
5. INPUT/OUTPUT FOR CLOCKS AND
DATA
7. GROUNDING AND POWER SUPPLY
DECOUPLING
The evaluation board has been designed to allow
interfacing to external systems via the 10-pin header, J9. This header allows the evaluation board to
accept externally generated clocks and data. The
schematic for the clock/data I/O is shown in
Figure 9. The 74HC243 transceiver functions as an
I/O buffer where HRD1 through HRD6 determine
if the transceiver operates as a transmitter or receiver. A transmit function is implemented with all
jumpers, HRD1 through HDR6 in the 8414 position. LRCK, SDATA, and SCLK from the CS8414
will be outputs on J9. The transceiver operates as a
receiver with HRD1 through HDR6 in the
EXT_CLK position. MCLK, LRCK, SDATA and
SCLK on J9 become inputs.
The CS4391 requires careful attention to power
supply and grounding arrangements to optimize
performance. Figure 10 details the power distribution used on this board. The decoupling capacitors
are located as close to the CS4391 as possible. Extensive use of ground plane fill in the evaluation
board yields large reductions in radiated noise.
6. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by six
binding posts (GND, +5V, +3/+5V, VL, VCC and
VEE), see Figure 10. The +5V input supplies power to the +5 volt digital circuitry (VA+5, VD+5,
VDPC+5), while the VL input supplies power to
the Voltage Level Converters and the CS4391
VL pin. +3/+5V supplies power to the CS4391.
VCC and VEE supply power to the op-amp and can
be +/-5 to +/-12 volts.
WARNING: Refer to the CS4391 datasheet for
maximum allowable voltages levels. Operation
outside of this range can cause permanent damage
to the device.
4
8. CONTROL PORT SOFTWARE
The CDB4391 is shipped with Windows based
software for interfacing with the CS4391 control
port via the DB25 connector, P1. The software can
be used to communicate with the CS4391 in either
SPI or I2C mode; however, in SPI mode the
CS4391 registers are write-only. Note: The
CDB4391 must be configured for control port
mode as shown in Table 4.
Further documentation for the software is available
on the distribution diskette. The documentation is
available in the plain text format file,
README.TXT.
9. DSD OPERATION
The CDB4391 supports Direct Stream Digital
(DSD) operation through the header for external
clocks and data, J9. The CS4391 must be placed
into the DSD mode and the jumpers HDR1 through
HDR6 must be placed into the external clock positions.
DS335DB2
CDB4391
CONNECTOR
INPUT/OUTPUT
SIGNAL PRESENT
+5V
Input
+ 5 Volt power
+3/+5V
Input
+ 2.7 to + 5.5 Volt power for the CS4391
VL
Input
+ 1.8 to +5.5 digital interface voltage (Note that VL should not
exceed the voltage applied to the+3/+5V terminal)
VEE
Input
-12 to -5V negative supply for the op-amp
VCC
Input
+5 to +12V positive supply for the op-amp
GND
Input
Ground connection from power supply
Coax Input
Input
Digital audio interface input via coax
Optical Input
Input
Digital audio interface input via optical
J9
Input/Output
I/O for master, serial, left/right clocks and serial data
Parallel Port
Input/Output
Parallel connection to PC for SPI / I2C control port signals
HDR9
Input/Output
I/O for SPI / I2C control port signals
AOUTA
Output
Channel A line level analog output
AOUTB
Output
Channel B line level analog output
Table 2. System Connections
DS335DB2
5
CDB4391
JUMPER /
SWITCH
PURPOSE
POSITION
FUNCTION SELECTED
SW1 - M0
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 - M1
CS8414 mode selection
*HI
See CS8414 datasheet for details
SW1 - M2
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 - M3
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 CSLR/FCK
Selects channel for CS8414
channel status information
*LO
See CS8414 datasheet for details
HDR8
External mute for AOUTA
*ON
OFF
Mute Enabled
Mute Disabled
HDR7
External mute for AOUTB
*ON
OFF
Mute Enabled
Mute Disabled
ENCTRL
Enables / Disables parallel port
ENABLE
*DISABLE
Invalid for Stand-Alone Mode
Disables parallel port
M0/AD0/CS
CS4391 Mode Selection
*HI
LO
See CS4391 datasheet for details
M1/SDA/CDIN
CS4391 Mode Selection
HI
*LO
See CS4391 datasheet for details
M2/SCL/CCLK
CS4391 Mode Selection
GND
HI
*DEM
See CS4391 datasheet for details
Allows the CS8414 to control de-emphasis
M3
CS4391 Mode Selection
HI
*LO
See CS4391 datasheet for details
HDR1 to HDR6
Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes source
Table 3. CDB4391 Jumper and Switch settings - STAND-ALONE MODE
*Settings for Stand-Alone mode
Notes:
6
The CDB4391 evaluation board is shipped from the factory configured for Control Port mode.
DS335DB2
CDB4391
JUMPER
PURPOSE
POSITION
FUNCTION SELECTED
SW1 - M0
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 - M1
CS8414 mode selection
*HI
See CS8414 datasheet for details
SW1 - M2
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 - M3
CS8414 mode selection
*LO
See CS8414 datasheet for details
SW1 CSLR/FCK
Selects channel for CS8414
channel status information
*LO
See CS8414 datasheet for details
HDR8
External mute for AOUTA
*ON
OFF
Mute Enabled
Mute Disabled
HDR7
External mute for AOUTB
*ON
OFF
Mute Enabled
Mute Disabled
ENCTRL
Enables / Disables parallel port
*ENABLE
DISABLE
Enables parallel port
Invalid for Control Port mode
M0/AD0/CS
AD0/CS
*HI
LO
“Don’t Care” for Control Port mode
M1/SDA/CDIN
SDA/CDIN Pull-Up
*HI
LO
SDA/CDIN pulled high
Invalid for Control Port mode
M2/SCL/CCLK
SCL/CCLK Pull-Up
GND
*HI
DEM
Invalid for Control Port mode
SCL/CCLK pulled high
Invalid for Control Port mode
M3
Not Functional
HI
*LO
Must be low for Control Port mode
HDR1 to HDR6
Selects source of clocks and
audio data
*8414
EXT
Selects CS8414 as source
Digital I/O header becomes source
Table 4. CDB4391 Jumper and Switch settings - CONTOL PORT MODE
*Settings for Control Port mode
Notes:
DS335DB2
The CDB4391 evaluation board is shipped from the factory configured for Control Port mode.
7
8
I/O for
Clocks
and Data
Fig 9
Digital
Audio
Inputs
Fig 6
CS8414
Digital
Audio
RXP
Receiver
Connections
RXN
Reset
Circuit
Fig 7
MCLK
LRCK
SCLK
SDATA
Control
Port
Interface
Fig 8
Channel A
Outputs
and Mute
Circuit
Fig 4
CS4391
Fig 2
Fig 5
CDB4391
DS335DB2
Figure 1. System Block Diagram and Signal Flow
Channel B
Outputs
and Mute
Circuit
Fig 3
DS335DB2
C54
.1UF
X7R
VL
U9
FERRITE_BEAD
L1
GND
VL
1
2
4
5
13
12
10
9
SDATA
C59
SCLK
.1UF
LRCK
M3
GND
14
VCC
/A0
B0
/A1
B1
/A2
B2
/A3
B3
O0
3
O1
6
U7
11
O2
R10
499
R13
499
R14
499
SDATA
R41
MCLK
8
O3
SCLK
LRCK
7
GND
49.9
74VHC125M
GND
M3
M2
GND
M2/SCL/CCLK
1
2
3
4
5
6
7
8
9
10
\RST
VL
SDATA/DSD_A
SCLK/DSD_B
LRCK/DSDMODE
MCLK
(DSD_CLK)M3
(SCL/CCLK)M2
(SDA/CDIN)M1
(AD0/\CS\)M0
AMUTEC
AOUTAAOUTA+
VA
AGND
AOUTB+
AOUTBBMUTEC
CMOUT
FILT+
VA+3/+5
20
19
18
17
16
15
14
13
12
11
AMUTEC
AOUTAAOUTA+
M0
C40
.1UF
X7R
1UF
AOUTB+
AOUTBBMUTEC
CS4391
M1
M1/SDA/CS
C17
GND
C20
C34
C21
1UF
.1UF
X7R
1UF
M0/AD0/CS
GND
U6
1
2
4
5
13
12
10
9
MCLK
RST
VL
8414_DEM
C61
O0
3
O1
6
11
O2
O3
GND
.1UF
14
VCC
/A0
B0
/A1
B1
/A2
B2
/A3
B3
DEM
8
7
74VHC125M
GND
GND
GND
9
CDB4391
Figure 2. CS4391 and Level Shift
10
R35
5.62K
C4
2700PF
COG
AOUTB-
10UF R34
AOUTB-
5.62K
GND
R29
C18
1.18K
C41
560PF
COG
U11
6
-
AOUTB+
10UF R33
AOUTB+
R32
5.62K
+
2
MC33078D
560PF
COG
AOUTB
GND
GND
HDR1X2
HDR7
1
2
GND
3
4 NC
R4
47K
C22
R31
5.62K
2700PF
COG
GND
1
5
1.18K
C39
C28
R19
7
J4
CON_RCA_RA
560
need cog
GND
VA+3/+5
2
MMUN2111LT1
Q6
1
Q5
2SC2878
3
2
3
R36
BMUTEC
BMUTEC
2K
Q2
MMUN2211LT1
1
3
1
2
GND
GND
CDB4391
DS335DB2
Figure 3. Channel B Audio Output and Mute Circuit
DS335DB2
R28
5.62K
C7
C6
2700PF
COG
560PF
COG
VCC
GND
C49
.1UF
V+
C42
C43
AOUTA+
10UF
R24
10UF
R26
R17
5.62K
R18
5.62K
AOUTA+
C14
-
560
1
V-
R5
47K
MC33078D
4
560PF
COG
GND
R20
1
+
C5
2700PF
COG
J3
CON_RCA_RA
U11 GND
3
1.18K
R15
5.62K
8
2
1.18K
C48
VEE
GND
2
3
4 NC
AOUTA
HDR1X2
HDR8
1
2
AOUTAAOUTA-
GND
.1UF
GND
GND
GND
VA+3/+5
2
MMUN2111LT1
Q3
1
Q1
2SC2878
3
2
3
R25
AMUTEC
AMUTEC
Q4
MMUN2211LT1
1
2K
3
1
2
GND
GND
11
CDB4391
Figure 4. Channel A Audio Output and Mute Circuit
12
1
2
3
HDR1X3
HDR5
MCLK
1
2
3
VA+5
C1
10UF
HDR1X3
HDR4
VA
1
2
3
HDR1X3
HDR3
1
2
3
HDR1X3
HDR2
GND
SCLK
GND
LRCK
R11
C26
RN3
560
VD+5
VCC
2
1UF
GND
U8
D1
LED_RECT
1
SN74HC04N
D3
C27
U2
CS8414_M0
.1UF
X7R
.1UF
C31
14
HDR1X3
HDR1
SDATA
.1UF
X7R
RN4
47K
4
3
D5
LED_RECT
6
5
D6
8
LED_RECT
RXP
RXN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VERF
C
CE/F2
CD/F1
SDATA
CC/F0
ERF
CB/E2
M1
CA/E1
M0
/C0/E0
VA+
VD+
AGND
DGND
FILT
RXP
RXN
MCK
FSYNC
M2
SCK
M3
CS12/FCK
SEL
U
CBL
SW1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CS8414_M1
1UF
C32
VA
R9
470
C33
CS8414
CS8414_M2
5
4
3
2
1
OPEN
VD+5
C16
10
1
2
3
VD1
VD1
SW_DIP_5
.068UF
X7R
GND
GND
CSLR/FCK
8414_DEM
9
LED_RECT
SW_B3W_1100
S4
D4
10
LED_RECT
11
D2
12
LED_RECT
13
R7
47.5K
ERROR & FREQ
VD1
7
GND
GND
CDB4391
DS335DB2
Figure 5. CS8414 Digital Audio Receiver
DS335DB2
DIGITAL INPUT
OPTICAL INPUT
OPT1
J5
CON_RCA_RA
3
NC 4
6
1
2
C11
.01UF
C10
1
RXN
2
R30
75
3
RXP
C9
L4
.01UF
4
47UH
5
GND
.01UF
VD+5
TORX173
GND
13
CDB4391
Figure 6. Digital Audio Inputs
14
U3
DS1233-10
3
GND
Vcc
1
VD+5
RST
GND
2
1
RST
C23
S1
SW_B3W_1100
100PF
GND
GND
CDB4391
DS335DB2
Figure 7. Reset Circuit
DS335DB2
VDPC+5
VD+5
C63
.1UF
C46
VDPC+5
PC PORT
RN2
GND
4.7K
6
11
14
GND
7 1
U15
2
VL
3
SN74HCT125D
GND
ENCTRL
ENABLE
5
GND
6
SN74HCT125D
RN1
1K
VDPC+5
U5
U15
16
4
EN_SCL/CCLK
U1
GND
RN2
15
RN2
4.7K
3
14
DB25M_RA
P1
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
1
11
/OE
CLK
2
3
4
5
6
7
8
9
1D
2D
3D
4D
5D
6D
7D
8D
4.7K
2
RN2
4
U15
4.7K
13
9
8
RN2
5
4.7K
1
2
4
5
13
12
10
9
O0
3
O1
6
19
18
17
16
15
14
13
12
VCC
GND
20
10
SN74HC574DW
M1/SDA/CDIN
11
O2
O3
GND
14
VCC
/A0
B0
/A1
B1
/A2
B2
/A3
B3
GND
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
EN_SCL/CCLK
SN74HCT125D
10
GND
.1UF
VDPC+5
HDR10
HDR1X3
GND
4.7K
1
C45
1
2
3
DISABLE
RN2
HDR4X2
HDR9
1
2
3
4
5
6
7
8
.1UF
VCC
M0/AD0/CS
8
M2/SCL/CCLK
7
74VHC125M
R8
2K
R6
2K
R12
2K
GND
VL
HDR1X3
HDR11
VDPC+5
HDR1X3
HDR12
1
2
3
C47
1
2
3
M0/AD0/CS
.1UF
GND
M2/SCL/CCLK
M1/SDA/CDIN
GND
12
GND
U15
11
12
13
GND
HDR23
1
2
VL
HDR22
1
2
M1/SDA/CDIN
HDR21
1
2
SN74HCT125D
DEM
GND
GND
VDPC+5
VDPC+5
GND
VCC
14
GND
7 1
U16
C62
2
3
.1UF
SN74HCT125D
GND
GND
U16
5
6
SN74HCT125D
4
GND
U16
R38
4.7K
9
8
D7
BAT85
SN74HCT125D
10
GND
RST
U16
11
12
13
GND
Figure 8. Control Port Interface
15
CDB4391
SN74HCT125D
16
U4
(DSD_CLK)M3
G1
G2
3
4
5
6
A1
A2
A3
A4
B1
B2
B3
B4
11
10
9
8
VCC
GND
14
7
C24
.1UF
DIGITAL I/O
1
2
3
HDR1X3
HDR6
VD+5
GND
VD+5
SN74HC243N
GND
8414
EXTERNAL
CLK SOURCE
SDATA
LRCK
SCLK
MCLK
U10
1
13
G1
G2
3
4
5
6
A1
A2
A3
A4
RN5
47K
VD+5
HDR1X3
HDR14
1
2
3
GND
B1
B2
B3
B4
VCC
GND
11
10
9
8
M3
M3
14
7
0
SDATA
LRCK
SCLK
MCLK
1
13
VD+5
C35
SN74HC243N
.1UF
R1
HDR5X2
J9
2
1
4
3
6
5
8
7
10
9
GND
GND
CDB4391
DS335DB2
Figure 9. I/O for Clocks and Data
DS335DB2
+5V
GND
CON_BANANA
+3V/+5V
J6
Z2
C12
47UF
C2
47UF
VEE
CON_BANANA
CON_BANANA
J11
P6KE6V8P
P6KE6V8P
VCC
CON_BANANA
J1
J7
Z1
VL
CON_BANANA
CON_BANANA
J10
J8
P6KE6V8P
Z3
Z4
P6KE13
P6KE13
Z5
GND
C29
47UF
C30
47UF
C36
47UF
VL
C25
VA+5
C3
.1UF
.1UF
VA+3/+5
C57
.1UF
C37
L3
FB
C8
L2
.1UF
FB
C38
.1UF
.1UF
GND
C13
47UF
VCC
VEE
GND
GND
GND
10UF
C19
VDPC+5
VD+5
17
CDB4391
Figure 10. Power Supply
CDB4391
Figure 11. Silkscreen Top
18
DS335DB2
CDB4391
Figure 12. Top Side
DS335DB2
19
CDB4391
Figure 13. Bottom Side
20
DS335DB2
CDB4391
10. PACKING LIST FOR CDB4391
Inspect the Contents of the package and confirm that the following contents are included:
1) CDB4391
2) CDB4391 datasheet
3) CS4391 datasheet
4) 3.5 inch floppy disk with the Windows based CDB4391 Graphical User Interface
5) 25-pin RS-232 cable
Item
Revision
CDB4391
B
CS4391-KZ
A
CDB4391 data sheet
DS335DB2
CS4391 Data sheet
DS335PP2
3.5 inch floppy disk with windows based
graphical user interface
1.0
25-pin RS-232 cable
If any of the items are missing please contact Cirrus for Crystal® Audio support at (800) 888-5016.
DS335DB2
21
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