Application Notes

Application Note
HELP3TM and Coupler
WCDMA Power Amplifier Module
Rev 1
Relevant products
• AWU6601, AWU6602, AWU6604, AWU6605 and
AWU6608.
General Description
This ANADIGICS 3 mm x 3 mm hetero-junction bipolar
transistor (HBT) power amplifier module is designed
for UMTS/WCDMA handsets and datacards. The
amplifier inputs and outputs are matched to provide
optimum performance in a 50 V system, and minimal
external components are required to proper RF
bypassing.
Table 1: Module Pin Description
piN
Name
description
1
VBATT
Battery Voltage
2
RFIN
RF Input
3
VMODE2 (N/C)
4
VMODE1
5
VEN
6
CPLOUT
7
GND
Ground
8
CPLIN
Coupler Input
9
RFOUT
RF Output
10
VCC
No Connection
Mode Control Voltage 1
PA Enable Voltage
Coupler Output
Supply Voltage
12/2010
WCDMA Power Amplifier Module
REFERENCE DESIGN BOARD
The Evaluation Board shown in Figure 2 was designed on ROGERS (R04003) material with 8 mils.
Figure 1: Evaluation Board Layout
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Application Note - Rev 1
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WCDMA Power Amplifier Module
TEST SET-UP
PA FDD Analysis
Recommended Test Equipment
Turn-on procedure
1. Vector Signal Generator
i. Optioned for digital modulation standards
2. Spectrum Analyzer
i. Standard measurement options preferred
ii. Frequency range to cover harmonics of
interest.
3. Power Meter
i. Recommend total of 4 channels
ii. Sense heads should cover frequency/
power range of interest and bandwidth
of modulation. 4. Power Supply
i. Recommend 4 channels minimum
ii. 1 channel should be capable of ~1A @ 5 V
and have remote sense capability
iii. Supply lines and sense lines should be close
as possible to DC power ports.
Minimum ~16 ga. wire recommended.
5. Directional couplers with good directivity
6. ~20 dB power attenuator with good VSWR
1. Assure all RF/DC power is OFF
a. HOT SWITCHING IS NOT RECOMMENDED!
2. Connect DUT DC power
3. VCC connection should be on high current line and sense lines a close to device as
possible.
4. Connect RF connections, torque to specification
5. Turn on DC power set for levels recommended
on DUT data sheet
6. Check for quiescent current
7. Apply RF power and set for desired RF output level stepping slowly from minimum signal generator power
Turn-off sequence:
1. Turn off RF input power
2. Turn off DC power
3. Remove DUT
Equipment Presets
1. Vector Signal Generator
i. Select modulation
ii. Reduce RF power to minimum
iii. Turn RF output power OFF
2. Spectrum Analyzer
i. Assure adequate RF input attenuation
to assure overload protection
3. Power Meter
i. Measure and set offsets for each frequency
of interest.
4. Power Supply
i. Set Over-voltage trip for ~8 V
ii. Set VCC channel for over-current
protection ~800 mA
iii. Set remaining over-current settings for
~100 mA
Application Note - Rev 1
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3
WCDMA Power Amplifier Module
Sig. Gen.
VMODE2
VMODE1
VEN
BP Filter
VCC
Isolator
Vcc/BATT
RF
VBATT
REF
Trig.
Power
Meter 1
4 CH Power
Supply
Vm1
Ven
Trig.
Ch A
Ch B
(NC)
Cpl_in
RFin
RFout
DUT
-20 dB
Cpl_in
C pl _o ut
Directional Coupler
Power
Meter 2
Trig.
Ch A
50
Directional Coupler
Spectrum
Analyzer
Ch A RF input reflection
Ch B Cpl_out
Ch B
Figure 2: Test Setup Diagram 1
4
50
Application Note - Rev 1
12/2010
Trig
RF
WCDMA Power Amplifier Module
TD-SCDMA Test Procedure
Connect test bench as shown in Diagram below.
Spectrum Analyzer
Agilent MXG
REF
OUT
RFin
Vcc
Vm1
RFout
DUT
-20 dB
Isolator
Cpl
out
Directional Coupler
Ch A
Trig
Cpl
in
Directional Coupler
50
50
50
Ch A RF
input
power
RF IN
TRIG IN
Vm2
TRIG OUTPUT
Vbatt
EVENT 1
Ven
REF RF
IN OUT
Pulse Generator
Power
Meter
Ch B
Ch A Trig
Power
Meter
Ch B
Figure 3: Test Setup Diagram 2
Follow all previous directions for Test bench settings,
Turning on and Turning off the PA.
Signal setup
The waveform was created using Agilent Signal
Studio for 3GPP TD-SCDMA N7612B version
1.3.2.0. The following images show the settings in
Signal Studio. In the first image the uplink signal is
enabled for timeslot 1 while also enabling the reverse
pilot timeslot. The second image shows that only the
first code channel is enabled. The waveform is then
downloaded to the Agilent MXG signal generator.
RF frequency and input power are selected on the
MXG.
Application Note - Rev 1
12/2010
5
WCDMA Power Amplifier Module
Figure 4: Signal Studio Timeslot 1
Figure 5: Signal Studio Code Channel Setup
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WCDMA Power Amplifier Module
Trigger/Synchronization setup
As with all time division signals (i.e. GSM), the test PA
and the measurement equipment need to be synchronized to the input signal. For the ANADIGICS PA, the
ENABLE pin is used as the input on/off control by the
trigger. The trigger signal originates from EVENT 1
output on the back of the MXG. The EVENT 1 signal
provides the trigger input to a pulse generator.
The TD-SCDMA signal is made up of 2 subframes.
Each subframe consists of 7 traffic timeslots and an
uplink and downlink pilot timeslot.
The overall subframe is 5 mS and each time slot is
675 uS. Knowing the timing values, the pulse generator is set to create a 675 uS pulse and a 12% duty
cycle.
The output of the pulse generator is used as the trigger signal for the spectrum analyzer.
Figure 6: Subframe
PA Output analysis
Signal analysis for TD-SCDMA is similar to measuring
CDMA signals with the exception of choosing the
trigger source and sweep.
Application Note - Rev 1
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7
WCDMA Power Amplifier Module
VBATT
C6
GND
C1
GND
RFIN
C7
C8
TX filter
L2
BB
VBATT
VCC
RFIN
RFOUT
VMODE2 (N/C)
CPL IN
VMODE1
C9
GND
C2
GND
at slug
VEN
GND
GND
C4
C10
L1
50Ω
CPLOUT
GND
GND
GND
PA_R1
PA_R0
PA_0N
(N/C)
To
Detector
C5
GND
Figure 7: Appliation Schematic
Figure 8: Suggested Layout Concept
Notes:
Pin 1 (Vbatt) is a low current line. Neck down feed from buss.
Bypass capacitors should be close to pins as possible. Pins 6 and 8 coupled ports should be
maintained at 50 ohms and used on pad filled vias.
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Application Note - Rev 1
12/2010
RFOUT
Duplexer
WCDMA Power Amplifier Module
PCB Board Design Guidelines
Refer to Figure 4 for the recommended PCB metal
design, soldermask design, and stencil print patterns
when assembling with ANADIGICS modules.
It is important to note that the PCB metal design is
dependent upon several factors: the electrical and
thermal performance requirement of the product and
the PCB-to-device interconnect pattern.
PCB metal design recommendations primarily deal
with the PCB-to-device interconnection. Specific
board-level electrical and thermal performance
requirements will be dictated by the physical geometry
of the specific application and are the responsibility of
the end product manufacturer.
Figure 9: PCB Board Design Guidelines
Application Note - Rev 1
12/2010
9
WCDMA Power Amplifier Module
Thermal Considerations
In PA module very little heat is dissipated to the air
through the top surface of the mold compound. The
major thermal path for heat dissipation from the heat
sources on the device is the path from the die to the
package substrate to the PCB, and through the PCB
surfaces to the air.
The efficiency of heat dissipation (measured by the
device junction temperature) is largely dependent on
the thermal resistance of the package and the PCB
(including the thermal resistance of the PCB to the
ambient air):
Tj = T ja + Ta = P (R Pkg + R PCB) + Ta
where,
-Tj is the junction temperature of the PA
-Tja is the temperature difference between the
junction and the ambient
-Ta is the ambient temperature
-P is the total power dissipation from the PA
-RPkg is the thermal resistance of the PA package
-RPCB is the thermal resistance of the PCB and PCB
to ambient air.
For a given maximum junction temperature, Tj max,
the maximum power that can be dissipated through
the package and the PCB to the ambient air is
determined by:
Pmax = Tj, max - Ta
RPkg + R PCB
This shows that in order to reduce the junction
temperature or to dissipate more power from the
device, the thermal resistance of the package, the
PCB, and the PCB to ambient air must be minimized.
Thermal resistance of the package is determined by
the package size, materials, and structures. High
thermal conductivity die attach materials are used.
Thermal vias and large metal pads are implemented
in the substrate to minimize the thermal resistance
and enhance the efficiency of the heat dissipation
from the device to the PCB.
When assembled onto a PCB, the package center
ground pad for an effective thermal path. Almost all
the heat generated from the package must eventually
dissipate through the PCB to the air.
10
Since the PCB-to-air thermal resistance is the major
portion of the overall thermal resistance, appropriate
design of the system PCB and proper assembly of the
package onto the PCB are crucial to overall system
thermal performance.
The following guidelines should be considered for PCB
designs and board level assembly:
Optimize the board level attachment process and
minimize the voids in the solder joints.
Maximize the common ground copper planes in the
PCB at the top and bottom surface. More copper
content in the inner layers of the PCB can also help
reduce the thermal resistance of the PCB.
Ensure sufficient thermal vias connect the top and
bottom ground copper planes in the PCB. These are
most effective when as many as possible are placed
under the PA ground pad. Effectiveness of thermal
vias diminishes the farther from the package ground
pad they are placed.
Minimize the interaction of the PA package with
other heat sources on the PCB. Heat sources near
the package can increase the PCB temperature
and thus increase the ambient temperature. This is
especially critical for the double-sided assembly where
placement of heat sources should be avoided in the
PCB area opposite to the PA. Conversely, passive
components on the PCB can increase the efficiency
of heat dissipation from the PCB to the air. Passive
components placed near the PA package on either
side of the PCB can improve the efficiency of heat
dissipation from the PA package.
Increase the contact areas between the PCB and the
case, such as the phone case. Heat transfer is much
more efficient via conduction than convection. More
contact area increases the heat dissipation to the case
and eventually to the air.
In general, a larger PCB area is better for heat
dissipation through the PCB to the ambient air. A
large PCB should be used to allowable by the system
design.
Application Note - Rev 1
12/2010
WCDMA Power Amplifier Module
Thermal Vias
To improve thermal and electrical performance of a
mounted PA module, an array of thermal vias placed
on the ground pad should be connected to the internal
and bottom common ground copper planes of the
PCB. The number of vias is based on via configuration
and the thermal and electrical requirements of the
particular module under consideration. In general,
there is a direct correlation between the thermal via
cross-sectional area and the heat dissipation rate.
However, the heat dissipation rate through thermal
vias can be easily saturated once it is greater than
that of solder joint or package heat sink. Large and
excessive thermal vias may introduce more voids
in the solder joint and actually reduce overall heat
dissipation performance.
Recommended thermal vias are 0.30 mm to 0.33 mm
in diameter, via barrels should be plated with 1 oz. of
copper to plug the vias. The thermal via array should
be arranged evenly with a pitch of 0.5 mm to 1.2 mm,
depending on the form factor of the package. For
the exposed region of the ground pad, if the plating
thickness is not sufficient to effectively plug the barrel
of the via when plated, solder, mask should be used
to cap the vias with minimum dimension equal to the
via diameter plug 0.1 mm. This will prevent solder
wicking through the thermal via during the soldering
process, resulting in voiding.
inner layer to GND. Microvias will go from the large
GND pad under the PA to the area on the inner layer
and buried or through vias will go the rest of the way
to the ground plane in the center for the board. See
Figure 12.
PA
components
signal
signal
GNd
power
GNd
signal
Keypad
Figure 10: Example of PCB Stack with Microvias on
Top and Bottom Layers, Buried Vias From Layers 2 to
7, and through Vias from Layers 1 to 8.
Another way to plug thermal vias uses solder mask
tenting on the bottom of the copper plane. Solder
mask tenting must completely cover the vias.
GROUNDING
Good grounding is crucial for best performance.
“Local ground planes” only connected to the board
GND plane using a few microvias is not adequate.
All GND planes must be connected to the main GND
layer (one designated inner layer of the PCB) using
a lot of through vias. Besides being the reference
for the all RF and other signals, the GND plane is
also used to distribute the heat dissipated by the PA
and should therefore be sufficient size and with many
through vias to spread the heat to other copper layers.
In order to establish a good ground connection for the
PA, it is necessary to assign an area on the first
Application Note - Rev 1
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11
WCDMA Power Amplifier Module
REFLOW SPECIFICATIONS
The reflow profile is a critical part of the PCB
assembly process. A proper reflow profile must
provide adequate time for flux volatilization, proper
peak temperature, time above liquidous, ramp up
and cool down rates. The profile used has a direct
bearing on manufacturing yield solder joint integrity,
and the reliability of the assembly [3]. A typical reflow
profile is made up of four distinct zones: the preheat
zone, the soak zone/flux activation zone, the reflow
zone, and the cooling zone.
Preheat Zone
Typically the heating rate in the preheat zone should
be 2 8C to 4 8C/second and the peak temperature in the
zone should be 100 8C to 125 8C. If the temperature
ramp is too fast, the solder paste may splatter and
cause solder balls. Also, to avoid thermal shock to
sensitive components such as ceramic chip resistors,
the maximum heating rate should be controlled.
Soak Zone
The soak zone is intended to allow the board
and components to reach a uniform temperature,
minimizing thermal gradients. The soak zone also
acts to activate the flux within the solder paste. The
ramp rate in this zone is very low and the temperature
is raised near the melting point of solder. The
consequences of being at too high a temperature
in the soak zone are solder balls due to insufficient
fluxing (when the ramp is too fast) and solder splatter
due to excessive oxidation of paste (when the ramp
rate is too slow).
resistance.
Additionally high temperature can
promote oxide growth, depending upon the furnace
atmosphere which can degrade solder wetting.
Cooling Zone
The cooling rate of the solder joint after reflow is
also important. For a given solder system, the
cooling rate is directly associated with the resulting
microstructure which in turn, affects the mechanical
behavior of solder joints. The faster the cooling rate,
the smaller the grain size of the solder will be, and
hence the higher the fatigue resistance of the solder
joint. Conversely, rapid cooling will result in residual
stresses between TCE mismatched components.
Therefore, the cooling rate needs to be optimized.
The profile of choice can affect any of the following
areas to a different degree by one of more of the
profile zones [3].
•Temperature distribution across the assembly
•Plastic IC package cracking
•Solder balling
•Solder beading
•Wetting ability
•Residue cleanability
•Residue appearance and characteristics
•Solder joint voids
•Metallurgical reactions between solder and substrate surface
•Board flatness
•Microstructure of solder joints
•Residual stress level of the assembly
Reflow Zone
In this zone the temperature is kept above the melting
point of the solder for 30 to 60 seconds. The peak
temperature in this zone should be high enough for
adequate flux action and to obtain good wetting.
The temperature, however, should not be so high
as to cause component damage, board damage,
discoloration or charring of the board. Extended
duration above the solder melting point will damage
temperature sensitive components and potentially
create excessive intermetallic growth between the
solder and the I/O pad metallization which makes the
solder joint brittle and reduces solder joint fatigue
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Application Note - Rev 1
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WCDMA Power Amplifier Module
REFLOW PROFILES
Table 2 provides a breakdown of the reflow conditions provided by the JEDEC standard J-STD-020C [5]
for leadfree solders. While this standard specifies a peak reflow temperature of 260 oC, the actual peak
temperature subjected to the part during reflow must not exceed 260 6 5 oC.
Table 2: Lead-free MSL Reflow Profile Breakdown
Jedec
specifications
Avg. Ramp-up (TL to TP)(1), (2)
3 8C/second max
Dwell Time (175 625 8C)
60-180 seconds
Ramp-up 200 8C to 217 8C
3 8C/second max
Time Above 217 8C
60-150 seconds
Time Within 5 8C of Peak
20-40 seconds max
Peak Temperature(3)
260 -5/+0 8C
Average Ramp-down
6 8C/second max
Notes:
(1) TL is the solder eutectic temperature
(2) TP is the peak temperature
(3) ANADIGICS recommended peak temperature
300
240 profile
260 profile
250 profile
250
temperature (c)
200
150
100
50
0
0:00:00
0:01:00
0:02:00
0:03:00
0:04:00
0:05:00
0:06:00
time (minutes)
Figure 11: Comparison of High Temperature Reflow Profiles
Application Note - Rev 1
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WCDMA Power Amplifier Module
REWORK GUIDELINE
The most common method of repairing surface mount
devices is by using hot air devices. During this rework
process care should be taken to prevent thermal
damage to adjacent component or substrates. The
following guidelines should be used to prevent
thermal damage and to produce an acceptable solder
joint after repair/rework [1]:
· Characterize the rework process carefully so as
not to overheat and damage the device.
· Keep the number of times a part is removed
and replaced to a maximum of two.
· Preheat the substrate for about 30 minutes to
about 95 °C.
· Use an appropriate attachment to direct the flow
of hot air to the component to be removed or
replaced.
· Minimize the heat time to reduce the device
exposure to high temperatures.
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WCDMA Power Amplifier Module
MSL (Moisture Sensitive Levels)
MSL levels are used to classify the sensitivity of a
microelectronic package to moisture. Packages can
be classified from level 1 (hermetic package) to level
6 (very sensitive). Knowledge of the MSL level of
a package is crucial during 2nd level solder reflow
for proper assembly of the product as these levels
dictate the duration that the package can be exposed
to the atmosphere before being exposed to solder
reflow temperatures. Once this time limit expires,
the package is at risk for catastrophic damage during
reflow. Table 3 summarizes the different MSL levels
as defined by JEDEC Standards J--STD-020B and
J-STD-020C [3,5].
The following flowchart shows the flow of the tests
performed to determine the MSL Rating:
Perform Pre-stress
electrical test and
Sonoscans
Pre-condition, Temp Cycle,
5 cycles
-40 8C to 60 8C
Dry bake for 24 hours at
125 8C
Table 3: Moisture Sensitive Levels
Soak Conditions
− 85 8C/85 RH for 168 hours (MSL-1) for leaded packages
− 85 8C/60 RH for 168 hours (MSL-2) for QFNs
− 30 8C/60 RH for 168 hours (MSL-3) for modules
level
Floor life
1
Unlimited
2
1 year
2a
4 weeks
3
168 hours (ANADIGICS product)
4
72 hours
5
48 hours
5a
24 hours
6
Time on Label
Reflow parts at peak
temperature relevant to
package
Perform Post-stress
electrical test and
Sonoscans
Application Note - Rev 1
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15
WCDMA Power Amplifier Module
Pin 1
Figure 12: Carrier Tape Drawing
10
0%
LL
FU
75
%
50
%
25
%
Ø177.8
MIN.
Ø50.8
±0.2 Ø54.2
±0.1
MADE IN USA
(2X)SLOT 3.0±.1
12.4±.
(3X)1.78±.25
Ø13.0±0.2
DIMENSIONS ARE IN MILLIMETERS
Ø20.6±0.13
CENTER HOLE DETAIL
ENLARGED FOR CLARITY
NOTES:
1. MATERIAL:
BLACK CARBON POLYSTYRENE
SURFACE RESISTIVITY:
1X10 4 TO 1X10 5 ohms/square
DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
Figure 13: Reel Drawing
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Application Note - Rev 1
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WCDMA Power Amplifier Module
ESD (Electro Static Discharge)
ESD or Electro Static Discharge is the leading cause
of electronic component failure during and after the
manufacturing process. High frequency and highly
miniaturized active components are especially prone
to damage by ESD. GaAs MMICs are not immune,
and deserve every possible ESD precaution.
neutralize the static charge. Because only air is
required for ionization to be effective, air ionizers
can and should be used wherever it is not possible
to ground everything. Ionizers should also be used
as a backup where grounding and other methods are
also employed.
ESD can damage all electronic parts, components
and subassemblies at all manufacturing and handling
stages. It affects production yields, manufacturing
costs, product quality, reliability, and profitability. And
while only a few components will be catastrophically
damaged to an extent where they fail completely,
many more may suffer damage that is not immediately
apparent. These latent failures will cause premature
failure in the field, with huge associated costs.
3. Wrist straps. Since the main cause of static is
people, the importance of wrist-straps in the fight
against ESD cannot be over-emphasized. A wriststrap, when properly grounded, keeps a person
wearing it near ground potential and static charges
do not accumulate. Wrist-straps should be worn
by all personnel in all ESD Protected Areas, that is,
where ESD susceptible devices and end products
containing them are assembled, manufactured,
handled and packaged.
Thus, ESD impacts productivity and product reliability
in all aspects of the electronic environment. In view
of all this, the importance of effective ESD prevention
cannot be overemphasized.
GENERAL ESD PRECAUTIONS
General ESD precautions center on measures
that can be taken to minimize electrostatic charge
building up. Reducing static generating processes
throughout the manufacturing flow should be the
goal. Contact and separation of dissimilar materials
and common plastics should be avoided as much as
possible in the work environment. In addition, general
measures to dissipate and neutralize charges should
be instituted.
Further ESD protection, similar to wrist-straps,
involves the use of ESD protective floors in conjunction
with ESD control footwear or foot-straps. Static
control garments (smocks) give additional protection
especially in clean room environments.
4. Work Areas. All areas where components that are
not in ESD protective packaging are handled should
be designated as ESD Protective Areas. Access to
such areas should be controlled, and only entered if
protective measures, such as wrist-straps and ESD
footwear are employed by all personnel. Workstations
in such areas should have a static-dissipative work
surface with a common ground for it and the worker’s
wrist-strap.
These include:
1. Humidity Control. Charge accumulation is
minimized if environmental humidity levels are
kept high.
Forty percent relative humidity is
recommended.
For instance, picking up a poly bag from a bench can
generate up to 20,000 Volts of charge at less than
25% Relative Humidity, but will generate less than
1,200 Volts if the Relative Humidity is kept between
65% and 90%.
2. Ionizers. In situations where we have to deal with
isolated conductors that cannot be grounded, and
with most common plastics, air ionization can
Application Note - Rev 1
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17
WCDMA Power Amplifier Module
REFERENCES
[1.] Ray P. Prasad; Surface Mount Technology - Principles and Practice; Van Nostrand Reinhold - New
York; 1989; Pages 311 -328.
[2] http://www.tutorialsweb.com/smt/smt.htm
[3] Charles Harper; Electronic Packaging and
Interconnect Handbook; “Solder Technologies for
Electronic Packaging Assembly”; McGraw-Hill 2000;
Pages 6.1 -6.83
[4] http://www.ecd.com/emfg/instruments/tech1.asp
[5] JDEC Standard J-STD-020C. Moisture/Reflow
Sensitivity Classification for non-hermetic Solid
State Surface Mount Devices. July 2004.
[6] ANADIGICS Application Note: Solder Reflow
Report. Revision 1.
[7] ANADIGICSApplication Note: High Temperature
Report Revision 2.
(8) ANADIGICS Application Note: Soldering Guidelines for Module PCB Mounting Revision 12.
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WCDMA Power Amplifier Module
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice.
The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to
change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed
to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers
to verify that the information they are using is current before placing orders.
warning
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product
in any such application without written consent is prohibited.
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Application Note - Rev 1
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