Application Note

Application Note
HELP3E Dual-band EGSM/IMT
WCDMA Power Amplifier Module
TM
Rev 1
Relevant products
•AWU6618
General Description
This ANADIGICS 3 mm x 5 mm power amplifier
module is designed for dual-band WCDMA/HSPA
EGSM/IMT handsets with operating frequency bands
from 880 MHz to 915 MHz (EGSM) and 1920 MHz
to 1980 MHz (IMT). This PA has built-in directional
couplers for each band with a common coupler output
part CPL_OUT. The amplifier inputs and outputs
are matched to provide optimum performance in a
50 V system, and minimal external components are
required for proper RF bypassing.
Table 1: Module Pin Description
PIN
Name
Description
PIN
Name
1
VEN_900
2
Enable Voltage for EGSM
Band
8
RFOUT_IMT
RFIN_900
RF Input for EGSM Band
9
GND
3
VMODE1
Mode Control Voltage for
EGSM and IMT bands
10
CPLOUT
Coupler OUT Port
4
VBATT
Battery Voltage
11
VCCA
Battery Voltage A
5
VMODE2
Mode Control Voltage for
EGSM and IMT band
12
VCC
6
RFIN_IMT
RF Input for IMT Band
13
RFOUT_900
7
VEN_IMT
Enable Voltage for IMT Band
14
GND
VEN_900
1
Description
RF Output for IMT Band
Ground
Supply Voltage
RF Output for EGSM Band
Ground
14
Bias Control
Voltage Regulation
RFIN_900
(1)
CPL
2
13
68 pF
12
3
VMODE1
RFOUT_900
VCC
1000 pF
VBATT
2.2 F
VMODE2
RFIN_IMT
VEN_IMT
(1)
68pF
4
11
68 pF
5
10
CPL
6
7
Bias Control
Voltage Regulation
GND at Slug (pad)
CPLOUT
9
8
33 pF
Figure 1: Evaluation Board Schematic
03/2012
2.2 F
RFOUT_IMT
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
REFERENCE DESIGN BOARD
The Evaluation Board shown in Figure 2 was designed on ROGERS (R04003) material with 8 mils
thickness.
Figure 2: Evaluation Board Layout
Notes:
1. Relative dielectric constant is 3.38 at 1 GHz.
2. Dielectric thicknes is 8.0 mills.
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Application Note - Rev 1
03/2012
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
Sig. Gen.
REF
Trig.
Power
Meter 1
4 CH Power
Supply
Vcc
RF
Ven Vm1
Vm2
Trig.
Ch A
Ch B
RFin
VMODE2
VEN
BP Filter
VCC
Isolator
VMODE1
Ch A RF Input Power
Ch B RF Output Power
RFout
DUT
-20 dB
Cpl_in
C pl _o ut
Directional Coupler
Power
Meter 2
Trig.
Ch A
50
Directional Coupler
50
Spectrum
Analyzer
Ch A RF input reflection
Ch B Cpl_out
Trig
RF
Ch B
Figure 3: Test Setup Diagram
Test Setup Notes:
1. Figure 3 shows minimum equipment required for proper power amplifier operation.
2. Depending upon the power sensor, 10 to 20 dB attenuator is sufficient to prevent overloading of the power meter or the
spectrum analyzer.
Test Equipment
The following test equipment is recommended for
testing of WCDMA EGSM/IMT evaluation boards.
•
•
•
•
•
•
One RF CDMA/WCDMA/CDMA 2000 signal
generator capable of delivering at least +5 dBm
of output power at the operating frequency band
(Agilent E4432B).
One RF power meter capable of measuring up
to +30 dBm at the operating frequency band
(Agilent E4419B).
One RF power sensor capable of measuring RF
power in the range from -50 dBm to +30 dBm at
the operating frequency band (Agilent E9301H).
One RF spectrum analyzer capable of measuring
ACP in operating frequency band and covering
up to the 3-rd harmonic of the highest frequency
in band (Rohde & Schwarz FSP).
One DC power supply capable of delivering 1.5 A
at +4 V and 500 mA at +3 V (Agilent 6624A)
One SMA 10 dB attenuator capable of handling
2 watts.
Test Equipment
1. With evaluation board dis-connected, set DC
power supply to +3.4 V (for VBATT and VCC) to
+1.8 V (for VEN), and to 0 V (for VMODE1 and
VMODE2)
3
2. Set power meter measured frequency to 897.5
MHz for EGSM band (1950 MHz for IMT band)
and its calibration factor to correspond to the
set frequency.
3. Set power meter offset value equal to the total
loss of the attenuator, directional coupler, and
connecting cables.
4. Set spectrum analyzer center frequency to
897.5 MHz for EGSM band (1950 MHz for IMT
band) and enable CDMA (3 GPPP) measuring
personality.
5. Select and enable CDMA digital signal on the
signal generator.
6. Set signal generator frequency to 897.5 MHz
for EGSM band (1950 MHz for IMT band) and
output power to -10 dBm.
7. Ensure DC power supply is disabled and RF
output of the signal generator is OFF.
8. Connect evaluation board to the test setup as
shown.
9. Turn RF output of the signal generator to ON.
10. Increase amplitude of the signal generator to
the desired output power level (according to the
corresponding data sheet).
11. Measure and record ACP, Gain (as a difference
between Input and Output power levels) and
total current consumption.
Application Note - Rev 1
03/2012
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
Test sequence (Recommeended PA turn-on
and turn-off sequences):
Turn-on sequence:
1. Connect DUT according to the setup shown
on Figure 3. Do not turn on DC power supply
before connecting DUT to RF input and output
cables (make sure that RF output of a signal
generator is OFF before connecting RF cables
to DUT).
2. Turn on VBATT and VCC first and then turn on VEN
and VMODE1,2..
3. Turn RF output of a signal generator ON and
make measurements.
Turn-off sequence:
1. Turn RF output of a signal generator OFF. Do not disconnect DUT from RF input and output
cables before turning off DC power supply.
2. Turn off VEN and VMODE1,2, and then VBATT
and VCC.
Layout Considerations
A sufficient number of vias (QTY 12 - 0.2 mm diameter plated through hole) should be placed under
the module in order to channel the heat properly. In
addition, contact should be made between the PA
slug located under the amplifier and the board. For
hand assembly of the board, place sufficient bonding
paste so that contact is made between the PA and
ground. For large volume assembly, please refer to
the solder profile recommendations application note.
For RFIN and RFOUT, provide 50 V transmission
lines.
Bias Modes
The power amplifier may be placed in either a Low
Medium or a High Bias mode by applying the appropriate logic level (see operating Ranges table)
to VMODE1,2. The Bias Control table lists the recommended modes of operation for various applications.
Three operating modes are available to optimize
current consumption. High Bias/ High power operating mode is for POUT levels > 16 dBm. At around
16 dBm output power, the PA should be “Mode
Switched” to Medium/Low power mode. For POUT
levels [ ~ 10 dBm the PA could be switched to Low
power mode for extremely low current consumption.
Output Power/VSWR Mandatory
Output Power at antenna port of the phone board
should not exceed the power level specified on
the data sheet (PA Max. output power - Front-end
loss). All VSWR value at PA output port toward the
antenna port should be lower than 8:1 under 28 dBm
Cellular (28 dBm IMT) POUT condition.
Application Information
To ensure proper performance, refer to all related
Application Notes on the ANADIGICS web site:
http://www.anadigics.com
Shutdown Mode
The power amplifier may be placed in a shutdown
mode by applying logic low levels (see Operating
Ranges table) to the VENABLE and VMODE1,2 voltages.
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Application Note - Rev 1
03/2012
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
Vcontrols
Venable/Vmode(s)
On Sequence Start
T_0N =0µ
Rise/Fall Max 1µS
Defined at 10% to 90%
of Min/Max Voltage
Off Sequence Start
T_0FF = 0µ
ON Sequence
OFF Sequence
RFIN_900, IMT
notes 1,2
VEN_900, IMT
VCC, VCCA
note 1
T_0N+1µS
T_0N+3µS
T_0FF+2µS T_0FF+3µS
Referenced After 90% of Rise
Time
Referenced Before10% of Fall
Time
Figure 4: Recommended ON/OFF Timing Sequence
Notes:
(1) Level might be changed after RF is ON.
(2) RF OFF defined as PIN ≤ -30 dBm.
(3) Switching simultaneously between VMODE and VEN is not recommended.
Table 2: Bias Control
POUT
LEVELS
BIAS
MODE
VEN
VMODE1
VMODE2
VCC
VBATT
WCDMA - low power
(Low Bias Mode)
< +8.5 dBm
Low
+1.8 V
+1.8
+1.8 V
3.2 - 4.2 V
> 3.2 V
WCDMA - med power
(Medium Bias Mode)
> 8 dBm
< +17 dBm
Low
+1.8 V
+1.8 V
0V
3.2 - 4.2 V
> 3.2 V
WCDMA - high power
(High Bias Mode)
> +16 dBm
High
+1.8 V
0V
0V
3.2 - 4.2 V
> 3.2 V
-
Shutdown
0V
0V
0V
3.2 - 4.2 V
> 3.2 V
APPLICATION
Shutdown
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Application Note - Rev 1
03/2012
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
PCB BOARD Design GuidELINES
Refer to Figure 4 for the recommended PCB metal
design, soldermask design, and stencil print patterns
when assembling with ANADIGICS modules [5].
It is important to note that the PCB metal design is
dependent upon several factors: the electrical and
thermal performance requirements of the product,
and the PCB-to-device interconnect pattern. The
PCB metal design recommendations primarily deal
with te PCB-to-device interconnection. Specific
board-level electrical and thermal performance requirements will be dictated by the physical geometry
of the specific application and are the responsibility
of the end product manufacturer.
Figure 5: PCB Board Design Guidelines
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Application Note - Rev 1
03/2012
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
Thermal Considerations
In PA module very little heat is dissipated to the air
through the top surface of the mold compound. The
major thermal path for heat dissipation from the heat
sources on the device is the path from the die to the
package substrate to the PCB, and through the PCB
surfaces to the air.
The efficiency of heat dissipation (measured by the
device junction temperature) is largely dependent on
the thermal resistance of the package and the PCB
(including the thermal resistance of the PCB to the
ambient air):
Tj = T ja + Ta = P (R Pkg + R PCB) + Ta
where,
-Tj is the junction temperature of the PA
-Tja is the temperature difference between the
junction and the ambient
-Ta is the ambient temperature
-P is the total power dissipation from the PA
-RPkg is the thermal resistance of the PA package
-RPCB is the thermal resistance of the PCB and PCB
to ambient air.
For a given maximum junction temperature, Tj max,
the maximum power that can be dissipated through
the package and the PCB to the ambient air is
determined by:
Pmax = Tj, max - Ta
RPkg + R PCB
This shows that in order to reduce the junction
temperature or to dissipate more power from the
device, the thermal resistance of the package, the
PCB, and the PCB to ambient air must be minimized.
Thermal resistance of the package is determined by
the package size, materials, and structures. High
thermal conductivity die attach materials are used.
Thermal vias and large metal pads are implemented
in the substrate to minimize the thermal resistance
and enhance the efficiency of the heat dissipation
from the device to the PCB.
When assembled onto a PCB, the package center
ground pad for an effective thermal path. Almost all
the heat generated from the package must eventually
dissipate through the PCB to the air.
7
Since the PCB-to-air thermal resistance is the major
portion of the overall thermal resistance, appropriate
design of the system PCB and proper assembly of the
package onto the PCB are crucial to overall system
thermal performance.
The following guidelines should be considered for
PCB designs and board level assembly:
Optimize the board level attachment process and
minimize the voids in the solder joints.
Maximize the common ground copper planes in the
PCB at the top and bottom surface. More copper
content in the inner layers of the PCB can also help
reduce the thermal resistance of the PCB.
Ensure sufficient thermal vias connect the top and
bottom ground copper planes in the PCB. These are
most effective when as many as possible are placed
under the PA ground pad. Effectiveness of thermal
vias diminishes the farther from the package ground
pad they are placed.
Minimize the interaction of the PA package with other
heat sources on the PCB. Heat sources near the
package can increase the PCB temperature and thus
increase the ambient temperature. This is especially
critical for the double-sided assembly where
placement of heat sources should be avoided in the
PCB area opposite to the PA. Conversely, passive
components on the PCB can increase the efficiency
of heat dissipation from the PCB to the air. Passive
components placed near the PA package on either
side of the PCB can improve the efficiency of heat
dissipation from the PA package.
Increase the contact areas between the PCB and the
case, such as the phone case. Heat transfer is much
more efficient via conduction than convection. More
contact area increases the heat dissipation to the
case and eventually to the air.
In general, a larger PCB area is better for heat
dissipation through the PCB to the ambient air. A
large PCB should be used to allowable by the system
design.
Application Note - Rev 1
03/2012
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
Thermal Vias
To improve thermal and electrical performance of a
mounted PA module, an array of thermal vias placed
on the ground pad should be connected to the internal
and bottom common ground copper planes of the
PCB. The number of vias is based on via configuration
and the thermal and electrical requirements of the
particular module under consideration. In general,
there is a direct correlation between the thermal via
cross-sectional area and the heat dissipation rate.
However, the heat dissipation rate through thermal
vias can be easily saturated once it is greater than
that of solder joint or package heat sink. Large and
excessive thermal vias may introduce more voids
in the solder joint and actually reduce overall heat
dissipation performance.
Recommended thermal vias are 0.30 mm to 0.33 mm
in diameter, via barrels should be plated with 1 oz. of
copper to plug the vias. The thermal via array should
be arranged evenly with a pitch of 0.5 mm to 1.2 mm,
depending on the form factor of the package. For
the exposed region of the ground pad, if the plating
thickness is not sufficient to effectively plug the barrel
of the via when plated, solder, mask should be used
to cap the vias with minimum dimension equal to the
via diameter plug 0.1 mm. This will prevent solder
wicking through the thermal via during the soldering
process, resulting in voiding.
inner layer to GND. Microvias will go from the large
GND pad under the PA to the area on the inner layer
and buried or through vias will go the rest of the way
to the ground plane in the center for the board. See
Figure 5.
PA
Components
Signal
Signal
GND
Power
GND
Signal
Keypad
Figure 6: Example of PCB Stack with Microvias on
Top and Bottom Layers, Buried Vias From Layers 2
to 7, and through Vias from Layers 1 to 8.
Another way to plug thermal vias uses solder mask
tenting on the bottom of the copper plane. Solder
mask tenting must completely cover the vias.
GROUNDING
Good grounding is crucial for best performance.
“Local ground planes” only connected to the board
GND plane using a few microvias is not adequate.
All GND planes must be connected to the main GND
layer (one designated inner layer of the PCB) using
a lot of through vias. Besides being the reference
for the all RF and other signals, the GND plane is
also used to distribute the heat dissipated by the PA
and should therefore be sufficient size and with many
through vias to spread the heat to other copper layers.
In order to establish a good ground connection for the
PA, it is necessary to assign an area on the first
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Application Note - Rev 1
03/2012
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
REFLOW SPECIFICATIONS
The reflow profile is a critical part of the PCB
assembly process. A proper reflow profile must
provide adequate time for flux volatilization, proper
peak temperature, time above liquidous, ramp up
and cool down rates. The profile used has a direct
bearing on manufacturing yield solder joint integrity,
and the reliability of the assembly [3]. A typical reflow
profile is made up of four distinct zones: the preheat
zone, the soak zone/flux activation zone, the reflow
zone, and the cooling zone [4].
Preheat Zone
Typically the heating rate in the preheat zone should
be 2 8C to 4 8C/second and the peak temperature in the
zone should be 100 8C to 125 8C. If the temperature
ramp is too fast, the solder paste may splatter and
cause solder balls. Also, to avoid thermal shock to
sensitive components such as ceramic chip resistors,
the maximum heating rate should be controlled.
Soak Zone
The soak zone is intended to allow the board
and components to reach a uniform temperature,
minimizing thermal gradients. The soak zone also
acts to activate the flux within the solder paste. The
ramp rate in this zone is very low and the temperature
is raised near the melting point of solder. The
consequences of being at too high a temperature in the
soak zone are solder balls due to insufficient fluxing
(when the ramp is too fast) and solder splatter due to
excessive oxidation of paste (when the ramp rate is
too slow). Typical soak times are usually around the
range of 130 - 180 8C for 60 to 90 seconds.
Reflow Zone
duration above the solder melting point will damage
temperature sensitive components and potentially
create excessive intermetallic growth between the
solder and the I/O pad metallization which makes
the solder joint brittle and reduces solder joint fatigue
resistance.
Additionally high temperature can
promote oxide growth, depending upon the furnace
atmosphere which can degrade solder wetting.
Cooling Zone
The cooling rate of the solder joint after reflow is
also important. For a given solder system, the
cooling rate is directly associated with the resulting
microstructure which in turn, affects the mechanical
behavior of solder joints. The faster the cooling rate,
the smaller the grain size of the solder will be, and
hence the higher the fatigue resistance of the solder
joint. Conversely, rapid cooling will result in residual
stresses between TCE mismatched components.
Therefore, the cooling rate needs to be optimized.
The profile of choice can affect any of the following
areas to a different degree by one of more of the
profile zones [3].
•Temperature distribution across the assembly
•Plastic IC package cracking
•Solder balling
•Solder beading
•Wetting ability
•Residue cleanability
•Residue appearance and characteristics
•Solder joint voids
•Metallurgical reactions between solder and substrate surface
•Board flatness
•Microstructure of solder joints
•Residual stress level of the assembly
In this zone the temperature is kept above the melting
point of the solder for 30 to 60 seconds. The peak
temperature in this zone should be high enough for
adequate flux action and to obtain good wetting. For
standard 63Sn37Pb solders, a peak temperature
range of 215 - 220 8C is generally considered
acceptable.
The temperature, however, should not be so high
as to cause component damage, board damage,
discoloration or charring of the board. Extended
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Application Note - Rev 1
03/2012
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
REFLOW PROFILES
Table 3 provides a breakdown of the reflow conditions
provided by the JEDEC standard J-STD-020C [4,5]
for leadfree solders. While this standard specifies a
peak reflow temperature of 260 oC, the actual peak
temperature subjected to the parts during qualification
will be dependant on the particular products’ high
temperature tolerating capabilities.
Table 3: Lead-free MSL Reflow Profile Breakdown
JEDEC
specifications
Avg. Ramp-up (TL to TP)(1)
3 C/second max
Dwell Time (175 25 C)
60-180 seconds
Ramp-up 200 C to 217 C
3 C/second max
Time Above 217 C
60-150 seconds
Time Within 5 C of Peak
20-40 seconds max
Peak Temperature(3)
260 -5/+0 C
Average Ramp-down
6 C/second max
Notes:
(1.)TL is the solder eutectic temperature.
(2.) TP is the peak temperature.
(3.) Actual peak temperature will be product independent.
300
240 Profile
260 Profile
250 Profile
250
Temperature (C)
200
150
100
50
0
0:00:00
0:01:00
0:02:00
0:03:00
0:04:00
0:05:00
Time (minutes)
Figure 7: Comparison of High Temperature Reflow Profiles
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Application Note - Rev 1
03/2012
0:06:00
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
REWORK GUIDELINE
The most common method of repairing surface mount
devices is by using hot air devices. During this rework
process care should be taken to prevent thermal
damage to adjacent component or substrates. The
following guidelines should be used to prevent
thermal damage and to produce an acceptable solder
joint after repair/rework [1]:
· Characterize the rework process carefully so as
not to overheat and damage the device.
· Keep the number of times a part is removed
and replaced to a maximum of two.
· Preheat the substrate for about 30 minutes to
about 95 °C.
· Use an appropriate attachment to direct the flow
of hot air to the component to be removed or
replaced.
· Minimize the heat time to reduce the device
exposure to high temperatures.
Table 4: Moisture Sensitive Levels
Level
Floor Life
1
Unlimited
2
1 year
2a
4 weeks
3
168 hours (ANADIGICS product)
4
72 hours
5
48 hours
5a
24 hours
6
Time on Label
The following flowchart shows the flow of the tests
performed to determine the MSL Rating:
MSL (Moisture Sensitive Levels)
MSL levels are used to classify the sensitivity of a
microelectronic package to moisture. Packages can
be classified from level 1 (hermetic package) to level
6 (very sensitive). Knowledge of the MSL level of
a package is crucial during 2nd level solder reflow
for proper assembly of the product as these levels
dictate the duration that the package can be exposed
to the atmosphere before being exposed to solder
reflow temperatures. Once this time limit expires,
the package is at risk for catastrophic damage during
reflow. Table 4 summarizes the different MSL levels
as defined by JEDEC Standards J--STD-020B and
J-STD-020C [3,5].
Perform Pre-stress
electrical test and
Sonoscans
Pre-condition, Temp Cycle,
5 cycles
-40 8C to 60 8C
Dry bake for 24 hours at
125 8C
Soak Conditions
− 85 8C/85 RH for 168 hours (MSL-1) for leaded packages
− 85 8C/60 RH for 168 hours (MSL-2) for QFNs
− 30 8C/60 RH for 168 hours (MSL-3) for modules
Reflow parts at peak
temperature relevant to
package
Perform Post-stress
electrical test and
Sonoscans
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Application Note - Rev 1
03/2012
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
ESD (Electro Static Discharge)
ESD or Electro Static Discharge is the leading cause
of electronic component failure during and after the
manufacturing process. High frequency and highly
miniaturized active components are especially prone
to damage by ESD. GaAs MMICs are not immune,
and deserve every possible ESD precaution.
neutralize the static charge. Because only air is
required for ionization to be effective, air ionizers
can and should be used wherever it is not possible
to ground everything. Ionizers should also be used
as a backup where grounding and other methods are
also employed.
ESD can damage all electronic parts, components
and subassemblies at all manufacturing and handling
stages. It affects production yields, manufacturing
costs, product quality, reliability, and profitability. And
while only a few components will be catastrophically
damaged to an extent where they fail completely,
many more may suffer damage that is not immediately
apparent. These latent failures will cause premature
failure in the field, with huge associated costs.
3. Wrist straps. Since the main cause of static is
people, the importance of wrist-straps in the fight
against ESD cannot be over-emphasized. A wriststrap, when properly grounded, keeps a person
wearing it near ground potential and static charges
do not accumulate. Wrist-straps should be worn
by all personnel in all ESD Protected Areas, that is,
where ESD susceptible devices and end products
containing them are assembled, manufactured,
handled and packaged.
Thus, ESD impacts productivity and product reliability
in all aspects of the electronic environment. In view
of all this, the importance of effective ESD prevention
cannot be overemphasized.
GENERAL ESD PRECAUTIONS
General ESD precautions center on measures
that can be taken to minimize electrostatic charge
building up. Reducing static generating processes
throughout the manufacturing flow should be the
goal. Contact and separation of dissimilar materials
and common plastics should be avoided as much as
possible in the work environment. In addition, general
measures to dissipate and neutralize charges should
be instituted.
Further ESD protection, similar to wrist-straps,
involves the use of ESD protective floors in conjunction
with ESD control footwear or foot-straps. Static
control garments (smocks) give additional protection
especially in clean room environments.
4. Work Areas. All areas where components that are
not in ESD protective packaging are handled should
be designated as ESD Protective Areas. Access to
such areas should be controlled, and only entered if
protective measures, such as wrist-straps and ESD
footwear are employed by all personnel. Workstations
in such areas should have a static-dissipative work
surface with a common ground for it and the worker’s
wrist-strap.
These include:
1. Humidity Control. Charge accumulation is
minimized if environmental humidity levels are
kept high.
Forty percent relative humidity is
recommended.
For instance, picking up a poly bag from a bench can
generate up to 20,000 Volts of charge at less than
25% Relative Humidity, but will generate less than
1,200 Volts if the Relative Humidity is kept between
65% and 90%.
2. Ionizers. In situations where we have to deal
with isolated conductors that cannot be grounded,
and with most common plastics, air ionization can
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Application Note - Rev 1
03/2012
HELP3ETM Dual-band EGSM/IMT WCDMA Power Amplifier Module
Figure 8: Carrier Tape Drawing
LL
0%
FU
10
75
%
50
%
25
%
Ø177.8
MIN.
Ø50.8
±0.2 Ø54.2
±0.1
MADE IN USA
(2X)SLOT 3.0±.1
12.4±.
(3X)1.78±.25
Ø13.0±0.2
DIMENSIONS ARE IN MILLIMETERS
Ø20.6±0.13
CENTER HOLE DETAIL
ENLARGED FOR CLARITY
NOTES:
1. MATERIAL:
BLACK CARBON POLYSTYRENE
SURFACE RESISTIVITY:
1X10 4 TO 1X10 5 ohms/square
DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
Figure 9: Reel Drawing
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Application Note - Rev 1
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WCDMA Power Amplifier Module
REFERENCES
[1] Ray P. Prasad; Surface Mount Technology - Principles and Practice; Van Nostrand Reinhold - New
York; 1989; Pages 311 -328.
[2] Charles Harper; Electronic Packaging and
Interconnect Handbook; “Solder Technologies for
Electronic Packaging Assembly”; McGraw-Hill 2000;
Pages 6.1 -6.83
[3] http://www.ecd.com/emfg/instruments/tech1.asp
[4] JDEC Standard J-STD-020C. Mositure/Reflow
Sensitivity Classification for non-hermetic Solid
State Surface Mount Devices. July 2004.
[5] ANADIGICS Application Note: Soldering Guidelines for Module PCB Mounting Revision 15.
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice.
The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to
change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed
to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers
to verify that the information they are using is current before placing orders.
warning
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product
in any such application without written consent is prohibited.
14
Application Note - Rev 1
03/2012