AP06N05A: Rad-Hard Solid State Relay with Buffered Inputs

Model # AP06N05A
Rad-Hard Solid State Relay with Buffered Inputs
60 Volt, 5 Amp SSR is Manufactured in a Certified Class-K Facility
Features
• >60 V Breakdown Voltage
• 5 Amp Design
• Neutron Fluence Level of 1.8E12 n/cm2
• Optically Coupled
• Total Dose Capability to 100 Krad (Si)
• Normally Open Contacts
• >1,000 VDC Input to Output Isolation
• Buffered Input Stage
• 3.3 V Compatible Logic Level Input
• Hermetically Sealed Package
Description
The AP06N05A is a radiation hardened dual solid-state relay in a hermetic package. It is configured as a dual, single-polesingle-throw (SPST) normally open relay with common input supply. This device is characterized for 100 Krad (Si) total
ionizing dose, and neutron fluence level of 1.8E12 n/cm2. The input and output FETs utilize advanced technology, and the
AP06N05A is optically coupled and actuated by standard logic inputs.
Table 1 – Absolute Maximum Ratings (Tc = +25oC Unless Otherwise Noted)
(Exceeding maximum ratings may damage the device.)
Symbol
Parameters / Test Conditions (Notes Page 3)
Value
Unit
VS
Output Voltage (5)
60
V
IO
Output Current (4) (5)
5
A
VIN
Input Buffer Voltage (Pin 4 & 6) (3)
± 7.0
V
VIN
Input Buffer Current
± 10
mA
VDD
Input Supply Voltage (Pin 5) (7)
10
V
IDD
Input Supply Current (7)
25
mA
PDISS
Power Dissipation (4) (5)
73
W
TJ
Operating Temperature Range
-55 to +150
oC
TS
Storage Temperature Range
-65 to +150
oC
TL
Lead Temperature
300
oC
Rev Date: 6/11/2015
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AP06N05A
Table 2 – General Characteristics per Channel @ -55°C < TC < +125°C
(Unless Otherwise Specified)
Group A
Subgroups
Test Conditions
Symbol
Min.
Typ.
Max.
Units
--
VDD = 5.0V, IO = 10A
VIN(TH)
-
--
3.0
V
Input-to-Output
Leakage Current (1)
--
VI-O = 1.0KVdc, dwell = 5.0s
TC = 25°C
II-O
--
--
1.0
mA
Output Capacitance (1)
--
VIN = 0.1V, f = 1.0MHz,
VS = 25V, TC = 25°C
COSS
--
340
--
pF
Thermal Resistance (1)
--
VIN = 3.3V, VDD = 5.0V (1, 4)
RTHJC
--
--
6
°C/W
MTBF (Per Channel)
--
MIL-HDBK-217F, [email protected]= 25°C
TBD
--
--
MHrs
Weight
--
--
--
--
25
grams
Units
Parameter
Input Buffer
Threshold Voltage (1) (3)
W
Table 3 – Pre-Irradiation Electrical Characteristics per Channel
@ -55°C < TC < +125°C (Unless Otherwise Specified)
Parameter
Group A
Subgroups
Test Conditions
1
Output On-Resistance
Output Leakage Current
Symbol
2
VIN = 3.3V
VDD = 5.0V, IO= 10A
1
VIN = 0.1V, VS = 200V
2
VIN = 0.1V, VS = 150V
RDS(ON)
IO
VDD = 5.0V, IO= 10A
Input Supply Current
Buffer Input Current
1, 2, 3
VDD = 10V, IO= 10A
1
2, 3
(1, 7)
IDD
Min.
Typ.
Max.
--
--
0.20
--
--
0.35
--
--
25
--
--
250
--
10
15
--
--
25
VIN = 3.3V
--
--
1.0
IIN
--
--
3.0
Turn-On Delay (6)
1, 2, 3
VIN = 3.3V, VDD = 5.0V, VS = 50V
RL = 5Ω, P.W. = 50ms
ton
--
--
TBD
Turn-Off Delay (6)
1, 2, 3
VIN = 0.1V, VDD = 5.0V, VS = 50V
RL = 5Ω, P.W. = 50ms
toff
--
--
TBD
Rise Time (2) (6)
1, 2, 3
VIN = 3.3V, VDD = 5.0V, VS = 50V
RL = 5Ω, P.W. = 50ms
tr
--
--
TBD
Fall Time (2) (6)
1, 2, 3
VIN = 0.1V, VDD = 5.0V, VS = 50V
RL = 5Ω, P.W. = 50ms
tf
--
--
TBD
uA
mA
mA
mS
Rev Date: 6/11/2015
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Ohms
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AP06N05A
Table 4 – Post Total Dose Irradiation (8, 9, 10)
Electrical Characteristics per Channel @ 25°C (unless otherwise specified)
Group A
Subgroups
Test Conditions
Symbol
Output On-Resistance
1
VIN = 3.3V, VDD = 5.0V, IO= 10A
RDS(ON)
Input Supply Current
1
VIN = 3.3V, VDD = 5.0V, IO= 10A
IDD
Output Leakage Current
1
VIN = 0.1V, VS = 100V
IO
25
Input Buffer Current
1
VIN = 3.3V
IIN
1.0
Turn-On Delay (6)
1
VIN = 3.3V, VDD = 5.0V, VS = 50V
RL = 5W, PW = 50ms
ton
TBD
1
VIN = 0.1V, VDD = 5.0V, VS = 50V
RL = 5W, PW = 50ms
toff
TBD
Rise Time (2) (6)
1
VIN = 3.3V, VDD = 5.0V, VS = 50V
RL = 5W, P.W. = 50ms
tr
TBD
(2) (6)
1
VIN = 0.1V, VDD = 5.0V, VS = 50V
RL = 5W, P.W. = 50ms
tf
TBD
Parameter
Turn-Off Delay
Fall Time
(6)
Min.
Typ.
10
Max.
Units
0.10
Ohms
15
mA
mA
ms
Notes for Maximum Ratings and Electrical Characteristic Tables
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Specification is guaranteed by design.
Rise and fall times are controlled internally.
Inputs protected for VIN < 1.0V and VIN > 7.0V.
Optically coupled Solid State Relays (in reality, a FET with isolated Gate drive) have relatively slow turn on
and turn off times. Care must be taken to insure that transient currents during these times do not cause
violation of SOA. If transient conditions are present, we recommends a complete simulation to be
performed by the end user to insure compliance with SOA requirements as specified in the data sheet of
the applicable switching transistor.
While the SSR design meets the design requirements specified in MIL-PRF-38534, the end user is
responsible for product derating, as required for the application.
Reference Figures 3 & 4 for Switching Test Circuits and Waveform; Output Voltage (VO) of Figure 4,
Switching Test waveform, is representative of the Output FET Drain-to-Source Voltage.
Input Supply voltage shall not exceed 6 V @ T c > 70°C.
Total Dose Irradiation with Input Bias. 10mA IDD applied and VDS = 0 during Irradiation.
Total Dose Irradiation with Output Bias. 100 Volts VDS applied and IDD = 0 during Irradiation.
API Technologies’ Marlborough Operations does not currently have a DLA certified Radiation Hardness
Assurance Program.
Radiation Performance
API’s Radiation Hardened Solid State Relays are tested to verify their hardness capability. The hardness assurance
program uses a Cobalt-60 (60 Co) Source and heavy ion irradiation. Both pre- and post-irradiation performance are
tested and specified using the same drive circuitry and test conditions to provide a direct comparison.
Rev Date: 6/11/2015
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AP06N05A
Table 5 - Ordering Information
AP
10
N
Breakdown Voltage
06 = 60 V
10 = 100 V
25 = 250 V
10
A
Max Output Current
01 = 1 A
05 = 5 A
10 = 10 A
12 = 12 A
Type
C = Normally Closed
N = Normally Open
D = SPDT
L = Latching
K
1
Screening Level
K = Class-K Compliant
H = Class-H Compliant
E = Engineering Model
C = Commercial
Lead Bend Options
1 = No Bend
2 = Surface Mount
3 = Pkg with backtab,
no leadbend
4 = Pkg with backtab,
SMT leadbend
Series
A = First Series
N = No set timing
MM = Make/Make
MB = Make/Break
BM = Break/Make
BB = Break/Break
Table 6 - Screening Options
Screening Levels
Tests
Mil-Std-883Method
H
K
Compliant- MIL-PRF-38534
100 % Non-Destruct Wire-Pull
Sample
100%
2023
Pre-Cap Visual
N/A
100%
2017
Temperature Cycle
100%
100%
1010
Constant Acceleration
100%
100%
2001
PIND
N/A
100%
2020
Pre-Burn-In Electrical (Ta= 25C)
100%
100%
Burn-In
100% (240 Hours)
100% (320 Hours)
1015
Final Electrical
100%
100%
(6)
Hermeticity (Fine & Gross Leak)
100%
100%
1014
X-Ray (5)
N/A
100%
2012
External Visual
100%
100%
2009
Rev Date: 6/11/2015
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AP06N05A
Figure 1 – Maximum Drain Current vs. Case Temperature per Channel
Figure 2 – Functional Block Diagram
Rev Date: 6/11/2015
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AP06N05A
Figure 3 – Switching Test Circuit (Only one channel shown)
Figure 4 – Switching Test Waveform
Rev Date: 6/11/2015
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AP06N05A
Figure 5 – 8-Pin Package, Dimensions with SMT Lead Bend
Figure 6 – 8-Pin Package, Dimensions with No Lead Bend
Rev Date: 6/11/2015
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AP06N05A
Table 7 – Pin Designations
Pin #
Pin Description
1
OUT 1 +
2
OUT 1 -
3
INPUT GND
4
INPUT 1
5
VDD (+5V)
6
INPUT 2
7
OUT 2 -
8
OUT 2 +
Case Outline Notes
1.- Dimensioning and Telebanking per ASME Y14.53M-1994
2.- Controlling Dimension: Inch
3.- Dimensions are shown in inches
4.- Tolerances are +/-0.005 UOS
5.- Lead Dimensions are prior to Hot Solder Dip (if used)
6.- Lead finish per MIL-PRF-38534, Finish A, hot solder dip (Sn 63/Pb37) only on SMT
lead bend option.
7.- For no leadbend, leads exit package as above and extend out 0.5” minimum.
Rev Date: 6/11/2015
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