LTC5599
30MHz to 1300MHz
Low Power
Direct Quadrature Modulator
Description
Features
n
n
n
n
n
Frequency Range: 30MHz to 1300MHz
Low Power: 2.7V to 3.6V Supply; 28mA
Low LO Carrier Leakage: –51.5dBm at 500MHz
Side-Band Suppression: –52.6dBc at 500MHz
Output IP3: 20.8dBm at 500MHz
Low RF Output Noise Floor: –156dBm/Hz at 6MHz
Offset, PRF = 3dBm
n Sine Wave or Square Wave LO Drive
n SPI Control:
Adjustable Gain: –19dB to 0dB in 1dB Steps
Effecting Supply Current from 8mA to 35mA
I/Q Offset Adjust: –65dBm LO Carrier Leakage
I/Q Gain/Phase Adjust: –60dBc Side-Band Suppressed
n24-Lead QFN 4mm × 4mm Package
n
Applications
n
Wireless Microphones
Battery Powered Radios
Ad-Hoc Wireless Infrastructure Networks
“White-Space” Transmitters
Software Defined Radios (SDR)
Military Radios
L, LT, LTC, LTM, Linear Technology, and the Linear logo are registered trademarks and
QuikEval is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
Typical Application
90MHz to 1300MHz Direct Conversion Transmitter Application
VCTRL
3.3V
EVM and Noise Floor vs RF Output
Power and Digital Gain Setting
with 1Ms/s 16-QAM Signal
10
1nF + 4.7µF
VCC
LTC5599
SPI
V
I-DAC
I
RF = 90MHz
to 1300MHz
I-CHANNEL
10nF
PA
0°
EN
90°
RMS EVM (%)
n
n
n
n
n
The LTC®5599 is a direct conversion I/Q modulator designed for low power wireless applications that enable
direct modulation of differential baseband I and Q signals
on an RF carrier. Single side-band modulation or side-band
suppressed upconversion can be achieved by applying
90° phase-shifted signals to the I and Q inputs. The I/Q
baseband input ports can be either AC or DC coupled to a
source with a common mode voltage level of about 1.4V.
The SPI interface controls the supply current, modulator
gain, and allows optimization of the LO carrier feedthrough
and side-band suppression, with sine wave or square
wave LO drive. A fixed LC network on the LO and RF ports
covers a continuous 90MHz to 1300MHz operation. An
on-chip thermometer can be activated to compensate for
gain-temperature variations. More accurate temperature
measurements can be made using an on-chip diode. In
addition, a continuous analog gain control (VCTRL) pin
can be used for fast power control.
9
8
7
6
5
4
3
2
1
0
DG = –19
DG = –16
DG = –12
DG = –8
DG = –4
DG = 0
–105
–115
–125
–135
–145
–155
Q-DAC
BASEBAND
GENERATOR
V
I
Q-CHANNEL
THERMOMETER
TTCK
–15
–10
–5
0
RF OUTPUT POWER (dBm)
5
–165
5599 TA01b
39nH
VCO/SYNTHESIZER
15pF
5599 TA01a
5599f
For more information www.linear.com/LTC5599
1
LTC5599
Absolute Maximum Ratings
Pin Configuration
(Note 1)
CSB
SCLK
SDI
SDO
VCC
EN
TOP VIEW
Supply Voltage..........................................................3.8V
Common Mode Level of BBPI, BBMI,
and BBPQ, BBMQ.........................................................2V
LOL, LOC DC Voltage.............................................. ±0.1V
LOL, LOC Input Power (Note 15)...........................20dBm
Current Sink of TEMP, SDO.....................................10mA
Voltage on Any Pin (Note 16)............–0.3V to VCC + 0.3V
TJMAX..................................................................... 150°C
Case Operating Temperature Range........–40°C to 105°C
Storage Temperature Range................... –65°C to 150°C
24 23 22 21 20 19
VCTRL 1
18 GNDRF
GND 2
17 GNDRF
GND
25
LOL 3
LOC 4
16 RF
15 GNDRF
13 GNDRF
GND
BBMQ
9 10 11 12
BBPQ
8
BBMI
7
BBPI
14 GNDRF
TTCK 6
TEMP
GND 5
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 150°C, θJA = 43°C/W, θJC = 4.5°C/W (AT EXPOSED PAD)
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
CASE TEMPERATURE RANGE
LTC5599IUF#PBF
LTC5599IUF#TRPBF
5599
24-Lead (4mm × 4mm) Plastic QFN
–40°C to 105°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Please refer to: http://www.linear.com/designtools/packaging/ for the most recent package drawings.
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TC = 25°C. VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, PLO = 0dBm, BBPI, BBMI, BBPQ,
BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz, 2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90°
shifted, lower sideband selection, all registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fLO = 150MHz, fRF1 = 147.9MHz, fRF2 = 148MHz, Register 0x00 = 0x62
S22(ON)
RF Port Return Loss
fLO(MATCH)
LO Match Frequency Range
S11 < –10dB
–26
Gain
Conversion Voltage Gain
20 • Log (VRF(OUT)(50Ω)/VIN(DIFF)(I or Q))
–7.5
dB
POUT
Absolute Output Power
1VP-P(DIFF) CW Signal, I and Q
–3.5
dBm
OP1dB
Output 1dB Compression
5
dBm
OIP2
Output 2nd Order Intercept
(Note 5)
70.5
dBm
OIP3
Output 3rd Order Intercept
(Note 6)
21.7
dBm
NFloor
RF Output Noise Floor
No Baseband AC Input Signal (Note 3)
–155.3
SB
Side-Band Suppression
(Note 7)
–61.4
dBc
LOFT
Carrier Leakage (LO Feedthrough)
(Note 7)
EN = Low (Note 7)
–52.8
–84.8
dBm
dBm
2LOFT
LO Feedthrough at 2xLO
–59
dBm
116 to 272
dB
MHz
dBm/Hz
5599f
2
For more information www.linear.com/LTC5599
LTC5599
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TC = 25°C. VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, PLO = 0dBm, BBPI, BBMI, BBPQ,
BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz, 2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90°
shifted, lower sideband selection, all registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
SYMBOL
PARAMETER
CONDITIONS
2LO
Signal Powers at 2xLO
Maximum of 2fLO – 2fBB; 2fLO – fBB; 2fLO + fBB,
2fLO + 2fBB
MIN
TYP
MAX
UNITS
–51
dBc
–57
dBm
–10.7
dBc
RSOURCE = 50Ω, Differential
15
MHz
RSOURCE = 50Ω, Differential
28
MHz
3LOFT
LO Feedthrough at 3xLO
3LO
Signal Powers at 3xLO
Maximum of 3fLO – fBB; 3fLO + fBB
BW1dBBB
–1dB Baseband Bandwidth
BW3dBBB
–3dB Baseband Bandwidth
fLO = 500MHz, fRF1 = 497.9MHz, fRF2 = 498MHz, Register 0x00 = 0x2D
S22(ON)
RF Port Return Loss
fLO(MATCH)
LO Match Frequency Range
S11 < –10dB
–26
180 to 1900
dB
MHz
Gain
Conversion Voltage Gain
20 • Log (VRF(OUT)(50Ω)/VIN(DIFF)(I or Q))
–7.7
dB
POUT
Absolute Output Power
1VP-P(DIFF) CW Signal, I and Q
–3.7
dBm
OP1dB
Output 1dB Compression
5.0
dBm
OIP2
Output 2nd Order Intercept
(Note 5)
63.6
dBm
OIP3
Output 3rd Order Intercept
(Note 6)
20.8
dBm
NFloor
RF Output Noise Floor
No Baseband AC Input Signal (Note 3)
POUT = 3dBm (Note 3)
–156.7
–156.0
dBm/Hz
dBm/Hz
SB
Side-Band Suppression
(Note 7)
–52.6
dBc
LOFT
Carrier Leakage (LO Feedthrough)
(Note 7)
EN = Low (Note 7)
–51.5
–67.5
dBm
dBm
–61
dBm
–51
dBc
–62
dBm
–11.8
dBc
2LOFT
LO Feedthrough at 2xLO
2LO
Signal Powers at 2xLO
3LOFT
LO Feedthrough at 3xLO
3LO
Signal Powers at 3xLO
Maximum of 3fLO – fBB; 3fLO + fBB
BW1dBBB
–1dB Baseband Bandwidth
RSOURCE = 50Ω, Differential
29
MHz
BW3dBBB
–3dB Baseband Bandwidth
RSOURCE = 50Ω, Differential
57
MHz
Maximum of 2fLO – 2fBB; 2fLO – fBB; 2fLO + fBB,
2fLO + 2fBB
fLO = 900MHz, fRF1 = 897.9MHz, fRF2 = 898MHz, Register 0x00 = 0x12
S22(ON)
RF Port Return Loss
fLO(MATCH)
LO Match Frequency Range
S11 < –10dB
–28
223 to 1902
dB
MHz
Gain
Conversion Voltage Gain
20 • Log (VRF(OUT)(50Ω)/VIN(DIFF)(I or Q))
–8.9
dB
POUT
Absolute Output Power
1VP-P(DIFF) CW Signal, I and Q
–4.9
dBm
OP1dB
Output 1dB Compression
4.1
dBm
OIP2
Output 2nd Order Intercept
(Note 5)
63.5
dBm
OIP3
Output 3rd Order Intercept
(Note 6)
18.4
dBm
NFloor
RF Output Noise Floor
No Baseband AC Input Signal (Note 3)
–155.6
dBm/Hz
SB
Side-Band Suppression
(Note 7)
–61.3
dBc
LOFT
Carrier Leakage (LO Feedthrough)
(Note 7)
EN = Low (Note 7)
–58.6
–62.3
dBm
dBm
2LOFT
LO Feedthrough at 2xLO
–59
dBm
2LO
Signal Powers at 2xLO
–51
dBc
Maximum of 2fLO – 2fBB; 2fLO – fBB; 2fLO + fBB,
2fLO + 2fBB
5599f
For more information www.linear.com/LTC5599
3
LTC5599
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TC = 25°C. VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, PLO = 0dBm, BBPI, BBMI, BBPQ,
BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz, 2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90°
shifted, lower sideband selection, all registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
SYMBOL
PARAMETER
3LOFT
LO Feedthrough at 3xLO
CONDITIONS
MIN
TYP
MAX
3LO
Signal Powers at 3xLO
Maximum of 3fLO – fBB; 3fLO + fBB
–19.2
dBc
BW1dBBB
–1dB Baseband Bandwidth
RSOURCE = 50Ω, Differential
37
MHz
BW3dBBB
–3dB Baseband Bandwidth
RSOURCE = 50Ω, Differential
69
MHz
–60
UNITS
dBm
Variable Gain Control (VCTRL)
VCTRLR
Gain Control Voltage Range
Set Bit 6 in Register 0x01
0.9 to 3.3
V
tCTRL
Gain Control Response Time
Set Bit 6 in Register 0x01 (Note 8)
20
ns
ZCTRL
Gain Control Input Impedance
Set Bit 6 in Register 0x01
10
pF
ICTRL
DC Input Current
Set Bit 6 in Register 0x01
Clear Bit 6 in Register 0x01
2.58
0
mA
mA
Internally Generated
Differential
Four Baseband Pins Shorted
Four Baseband Pins Shorted, EN = Low
No Hard Clipping, Single-Ended, Digital Gain
(DG) = –10
1.42
1.8
350
1.3
1.2
V
kΩ
Ω
nA
VP-P
Baseband Inputs (BBPI, BBMI, BBPQ, BBMQ)
VCMBB
RIN(DIFF)
RIN(CM)
IBB(OFF)
VSWING
DC Common Mode Voltage
Input Resistance
Common Mode Input Resistance
Baseband Leakage Current
Amplitude Swing
Power Supply (VCC)
VCC
VRET(MIN)
ICC(ON)
ICC(RANGE)
ICC(OFF)
tON
tOFF
tSB
tLO
Supply Voltage
Minimum Data Retention Voltage
Supply Current
Supply Current Range
Supply Current, Sleep Mode
Turn-On Time
Turn-Off Time
Side-Band Suppression Settling
LO Suppression Settling
2.7
1.6
20
(Note 14)
EN = High
EN = High, Register 0x01 from 0x00 to 0x13
EN = 0V
EN = Low to High (Notes 8, 12)
EN = High to Low (Notes 9, 12)
Register 0x00 Change, <–50dBc (Note 12)
Register 0x02 Change, <–60dBm (Note 12)
3.3
1.3
28
8 to 36
0.7
167
53
500
90
3.6
37
9
V
V
mA
mA
µA
ns
ns
ns
ns
Serial Port (CSB, SCLK, SDI, SDO), Enable (EN) and TTCK, SCLK = 20MHz
VIH
Input High Voltage
l
VIL
Input Low Voltage
l
IIH
Input High Current
0.02
nA
IIL
Input Low Current
–0.4
nA
VOH
Output High Voltage
(Note 13)
l
VOL
Output Low Voltage
ISINK = 8mA (Note 10)
l
IOH
SDO Leakage Current
for SDO = High
VHYS
Input Trip Point Hysteresis
tCKH
SCLK High Time
l
1.1
V
0.2
VCC_L – 0.2
V
0.7
22.5
V
V
0.5
nA
110
mV
25
ns
5599f
4
For more information www.linear.com/LTC5599
LTC5599
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TC = 25°C. VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, PLO = 0dBm, BBPI, BBMI, BBPQ,
BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz, 2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90°
shifted, lower sideband selection, all registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
SYMBOL
PARAMETER
tCSS
CSB Setup Time
CONDITIONS
l
MIN
20
ns
tCSH
CSB High Time
l
30
ns
tCS
SDI to SCLK Setup Time
l
20
ns
tCH
SDI to SCLK Hold Time
l
10
ns
tDO
SCLK to SDO Time
l
45
tC%
SCLK Duty Cycle
l
45
fCLK
Maximum SCLK Frequency
l
20
VTEMP
Temperature Diode Voltage
Temperature Slope
ITEMP = 100µA
ITEMP = 100µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC5599 is guaranteed functional over the operating case
temperature range from –40°C to 105°C.
Note 3: At 6MHz offset from the LO signal frequency. 100nF between BBPI
and BBMI, 100nF between BBPQ and BBMQ.
Note 4: The Default Register Settings are listed in Table 1.
Note 5: IM2 is measured at fLO – 4.1MHz.
Note 6: IM3 is measured at fLO – 2.2MHz and fLO – 1.9MHz. OIP3 = lowest
of (1.5 • P{fLO – 2.1MHz} – 0.5 • P{fLO – 2.2MHz}) and (1.5 • P{fLO – 2MHz}
– 0.5 • P{fLO – 1.9MHz}).
Note 7: Without side-band or LO feedthrough nulling (unadjusted).
Note 8: RF power is within 10% of final value.
Note 9: RF power is at least 30dB down from its ON state.
Note 10: VOL voltage scales linear with current sink. For example for
RPULL-UP = 1kΩ, VCC_L = 3.3V the SDO sink current is about (3.3 – 0.2)
/1kΩ = 3.1mA. Max VOL = 0.7 • 3.1/8 = 0.271V, with RPULL-UP the SDO
TYP
MAX
UNITS
ns
50
55
%
MHz
763
1.6
mV
mV/°C
pull-up resistor and VCC_L the digital supply voltage to which RPULL-UP is
connected to.
Note 11: I and Q baseband Input signal = 2MHz CW, 0.8VP-P, DIFF each,
I and Q 0° shifted.
Note 12: fLO = 500MHz, PLO = 0dBm, C4 = 1.5nF
Note 13: Maximum VOH is derated for capacitive load using the following
formula: VCC_L • exp (–0.5 • TCLK/(RPULL-UP • CLOAD), with TCLK the
time of one SCLK cycle, RPULL-UP the SDO pull-up resistor, VCC_L the
digital supply voltage to which RPULL-UP is connected to, and CLOAD the
capacitive load at the SDO pin. For example for TCLK = 100ns (10MHz
SCLK), RPULL-UP = 1kΩ, CLOAD = 10pF and VCC_L = 3.3V the derating is 3.3
• exp(–5) = 22.2mV, thus maximum VOH = 3.3V – 0.1 – 0.0222 = 3.177V.
Note 14: Minimum VCC in order to retain register data content.
Note 15: Guaranteed by design and characterization. This parameter is not
tested.
Note 16: RF pin guaranteed by design while using a 10nF coupling
capacitor. The RF pin is not tested.
5599f
For more information www.linear.com/LTC5599
5
LTC5599
Typical
Performance Characteristics
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm, fLO = 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Supply Current vs Digital
Gain Setting
36
–40°C
–10°C
25°C
85°C
105°C
32
40
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
34
30
28
26
24
30
Gain vs RF Frequency and
Digital Gain Setting
0
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
–5
–10
–15
20
–20
10
–25
22
3
3.3
SUPPLY VOLTAGE (V)
0
–19 –17 –15 –13 –11 –9 –7 –5 –3
DIGITAL GAIN SETTING
3.6
5599 G01
5
250
450
650
850 1050
RF FREQUENCY (MHz)
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
70
1250
60
50
40
50
250
450
650
850 1050
RF FREQUENCY (MHz)
5599 G04
–40
–50
–60
–70
50
250
450
650 850 1050
RF FREQUENCY (MHz)
1250
5599 G07
–30
SIDE-BAND SUPPRESSION (dBc)
SIDE-BAND SUPPRESSION (dBc)
–30
–50
–60
–70
–80
50
1250
250
450
650 850 1050
RF FREQUENCY (MHz)
3.3V, 25°C
2.7V, 25°C
3.3V, 105°C
3.3V, –40°C
–40
3.6V, 25°C
3.3V, 85°C
3.3V, –10°C
–50
–60
TEMPUPDT = 1
–70
50
250
450
650
850 1050
LO FREQUENCY (MHz)
1250
5599 G06
Side-Band Suppression vs LO
Frequency for Gain TempComp Off
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
–20
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
5599 G05
Side-Band Suppression vs RF
Frequency and Digital Gain Setting
–10
1250
–40
LO LEAKAGE (dBm)
OIP3 (dBm)
10
450
650
850 1050
RF FREQUENCY (MHz)
LO Leakage vs RF Frequency and
Digital Gain Setting
80
OIP2 (dBm)
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
15
250
5599 G03
Output IP2 vs RF Frequency and
Digital Gain Setting
20
DIGITAL GAIN SETTING (DG) = –19
(REGISTER 0x01 = 0x13)
5599 G02
Output IP3 vs RF Frequency and
Digital Gain Setting
0
50
–30
50
–1
1250
5599 G08
Side-Band Suppression vs LO
Frequency for Gain TempComp On
–30
SIDE-BAND SUPPRESSION (dBc)
20
2.7
DIGITAL GAIN SETTING (DG) = 0
(REGISTER 0x01 = 0x00)
GAIN (dB)
Supply Current vs Supply Voltage
3.3V, 25°C
2.7V, 25°C
3.3V, 105°C
3.3V, –40°C
–40
3.6V, 25°C
3.3V, 85°C
3.3V, –10°C
–50
–60
–70
50
250
450
650
850 1050
LO FREQUENCY (MHz)
1250
5599 G09
5599f
6
For more information www.linear.com/LTC5599
LTC5599
Typical
Performance Characteristics
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm, fLO = 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting and 3.6V Supply
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting and 3.3V Supply
–140
DIGITAL GAIN SETTING = 0
(REGISTER 0x01 = 0x00)
–150
OP1dB (dBm)
–155
–160
–2
–6
–165
DIGITAL GAIN SETTING = –19
(REGISTER 0x01 = 0x13)
250
450
650
850 1050
RF FREQUENCY (MHz)
1250
–10
50
250
450
650
850 1050
RF FREQUENCY (MHz)
–6
–10
50
250
450
650
850 1050
RF FREQUENCY (MHz)
1250
2
–2
–6
–10
50
250
450
650
850 1050
RF FREQUENCY (MHz)
–6
–10
50
250
450
650
850 1050
RF FREQUENCY (MHz)
1250
5599 G16
1250
2
–2
–6
–10
50
250
450
650
850 1050
RF FREQUENCY (MHz)
Gain vs RF Frequency and VCTRL
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
2
–2
–6
–10
50
250
450
650
850 1050
RF FREQUENCY (MHz)
1250
5599 G15
6
OP1dB (dBm)
OP1dB (dBm)
–2
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting at 105°C
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
1250
6
5599 G14
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting at 85°C
2
450
650
850 1050
RF FREQUENCY (MHz)
5599 G12
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
5599 G13
6
250
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting at –40°C
6
OP1dB (dBm)
OP1dB (dBm)
–2
–10
50
1250
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting at –10°C
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
2
–2
5599 G11
5599 G10
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting and 2.7V Supply
6
2
–6
OP1dB (dBm)
–170
50
2
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
6
1250
5599 G17
0
–20
GAIN (dB)
RF NOISE FLOOR (dBm/Hz)
–145
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
6
OP1dB (dBm)
Noise Floor vs RF Frequency and
Digital Gain Setting
3.3V
1.45V
–40
1.35V
–60
1.25V
1.15V
1V
–80
–100
50
1.8V
1.6V
AGCTRL = 1
250
450
650
850 1050
RF FREQUENCY (MHz)
1250
5599 G18
5599f
For more information www.linear.com/LTC5599
7
LTC5599
Typical Performance Characteristics
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm, fLO = 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Input IP2 vs RF Frequency
and VCTRL
40
80
1.8V
1.8V
3.3V
1.45V
20
1.35V
1.25V
10
1V
0
50
1.35V
40
1.25V
1.15V
20
AGCTRL = 1
250
1.45V
50
30
1.15V
450
650
850 1050
RF FREQUENCY (MHz)
1V
10
50
1250
AGCTRL = 1
250
450
650
850 1050
RF FREQUENCY (MHz)
5599 G19
–162
–166
50
1250
–156
450
650
850 1050
RF FREQUENCY (MHz)
3.3V, 25°C
3.6V, 25°C
2.7V, 25°C
3.3V, 85°C
3.3V, 105°C
3.3V, –10°C
3.3V, –40°C
DG = 0
DG = –4
–156
DG = –8
–158
DG = –12
–160
DG = –16
–154
–158
–162
–162
DG = –19
250
450
650
850 1050
RF FREQUENCY (MHz)
1250
–164
–10
–8
–6
–4 –2
2
0
RF POWER (dBm)
4
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
–7
–8
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
21
–15
20
–20
19
OIP3 (dBm)
–9
–10
–11
18
17
–12
–13
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
16
–14
–15
20
25
30
35
40
RF FREQUENCY (MHz)
45
50
5599 G25
–70
15
20
25
30
35
40
RF FREQUENCY (MHz)
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
45
–60
–50 –40 –30
VCTRL GAIN (dB)
–20
–10
5599 G24
Side-Band Suppression vs RF
Frequency for 30MHz LO Match
Output IP3 vs RF Frequency for
30MHz LO Match
Gain vs RF Frequency for 30MHz
LO Match
–5
AGCTRL = 1
5599 G23
5599 G22
–6
6
–166
–80
SIDE-BAND SUPPRESSION (dBc)
–160
50
GAIN (dB)
1250
Noise Floor vs VCTRL Gain
–150
–154
–152
250
5599 G21
Noise Floor vs RF Power
RF NOISE FLOOR (dBm/Hz)
–148
–158
–152
3.3V, 25°C
3.6V, 25°C
2.7V, 25°C
3.3V, 85°C
3.3V, 105°C
3.3V, –10°C
3.3V, –40°C
–144
–154
5599 G20
Noise Floor vs RF Frequency
–140
RF NOISE FLOOR (dBm/Hz)
1.6V
RF NOISE FLOOR (dBm/Hz)
1.6V
3.3V
2V
1.9V
1.85V
1.8V
1.75
1.65
1.6V
1.55V
1.5V
1.45V
1.4V
1.3V
1V
–150
60
IIP2 (dBm)
IIP3 (dBm)
3.3V
70
30
Noise Floor vs RF Frequency and
VCTRL
RF NOISE FLOOR (dBm/Hz)
Input IP3 vs RF Frequency and
VCTRL
50
5599 G26
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
–25
–30
–35
–40
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
–45
–50
20
25
30
35
40
RF FREQUENCY (MHz)
45
50
5599 G27
5599f
8
For more information www.linear.com/LTC5599
LTC5599
Typical Performance Characteristics
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm, fLO = 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Output IP3 vs RF Frequency for
70MHz LO Match
Gain vs RF Frequency for 70MHz
LO Match
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
–10
22
–7
OIP3 (dBm)
GAIN (dB)
–6
23
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
–8
–9
21
20
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
19
–10
50
60
70
80
90 100
RF FREQUENCY (MHz)
110
18
50
120
60
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
70
80
90 100
RF FREQUENCY (MHz)
110
5599 G28
Gain vs LO Power at fLO = 150MHz
–6
–4 –2
0
2
LO POWER (dBm)
GAIN (dB)
GAIN (dB)
GAIN (dB)
–14
4
3.3V
3.6V
2.7V
–22
–10
6
–8
–6
4
DIGITAL GAIN = –10
4
6
5599 G34
3.3V
3.6V
2.7V
–22
–10
6
–8
–6
–4 –2
0
2
LO POWER (dBm)
–6
6
5599 G33
DIGITAL GAIN = –4
15
DIGITAL GAIN = –10
3.3V
3.6V
2.7V
–8
4
19
DIGITAL GAIN = –10
7
–10
85°C
105°C
–10°C
–40°C
Output IP3 vs LO Power
at fLO = 500MHz
15
DIGITAL GAIN = –10
–4 –2
0
2
LO POWER (dBm)
–4 –2
0
2
LO POWER (dBm)
DIGITAL GAIN = –4
11
–6
120
DIGITAL GAIN = –4
23
19
–18
–8
110
Gain vs LO Power at fLO = 900MHz
–18
85°C
105°C
–10°C
–40°C
23
3.3V
DIGITAL GAIN = –4
3.6V
2.7V
–14
–22
–10
70
90 100
80
RF FREQUENCY (MHz)
–14
Output IP3 vs LO Power
at fLO = 150MHz
OIP3 (dBm)
–10
60
5599 G32
Gain vs LO Power
at fLO = 1260MHz
85°C
105°C
–10°C
–40°C
–60
DIGITAL GAIN = –10
–18
85°C
105°C
–10°C
–40°C
5599 G31
–6
–50
–10
OIP3 (dBm)
–8
–40
DIGITAL GAIN = –4
DIGITAL GAIN = –10
–22
–10
–30
–6
–10
–14
3.3V
3.6V
2.7V
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
5599 G30
Gain vs LO Power at fLO = 500MHz
DIGITAL GAIN = –4
–18
–20
–70
50
120
–6
–10
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
5599 G29
–6
GAIN (dB)
SIDE-BAND SUPPRESSION (dBc)
–5
Side-Band Suppression vs RF
Frequency for 70MHz LO Match
–4 –2
0
2
LO POWER (dBm)
11
85°C
105°C
–10°C
–40°C
4
6
5599 G35
7
–10
3.3V
3.6V
2.7V
–8
–6
–4 –2
0
2
LO POWER (dBm)
85°C
105°C
–10°C
–40°C
4
6
5599 G36
5599f
For more information www.linear.com/LTC5599
9
LTC5599
Typical Performance Characteristics
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm, fLO = 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Output IP3 vs LO Power at
fLO = 900MHz
3.3V
3.6V
2.7V
DIGITAL GAIN = –10
7
–10
–8
–6
–4 –2
0
2
LO POWER (dBm)
70
65
15
11
12
DIGITAL GAIN = –10
8
3.3V
3.6V
2.7V
4
4
0
–10
6
–6
–8
–4 –2
0
2
LO POWER (dBm)
5599 G37
75
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
70
40
–10
6
55
50
3.3V
3.6V
2.7V
45
40
–10
–8
–6
–4 –2
0
2
LO POWER (dBm)
75
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
70
60
55
45
40
–10
6
85°C
105°C
–10°C
–40°C
–6
–8
–45
DIGITAL GAIN = –4
3.3V
3.6V
2.7V
45
–4 –2
0
2
LO POWER (dBm)
4
40
–10
6
–8
–6
–4 –2
0
2
LO POWER (dBm)
–45
DIGITAL GAIN = –4
–8
–6
–4 –2
0
2
LO POWER (dBm)
85°C
105°C
–10°C
–40°C
4
6
5599 G43
LO LEAKAGE (dBm)
LO LEAKAGE (dBm)
–65
–10
3.3V
3.6V
2.7V
–50
DIGITAL GAIN = –10
–55
–60
–10
3.3V
3.6V
2.7V
–8
–6
–4 –2
0
2
LO POWER (dBm)
6
LO Leakage vs LO Power at
fLO = 900MHz
3.3V
3.6V
2.7V
–50
DIGITAL
GAIN = –10
4
5599 G42
–50
–55
6
55
LO Leakage vs LO Power at
fLO = 500MHz
–45
4
50
85°C
105°C
–10°C
–40°C
3.3V
3.6V
2.7V
60
5599 G41
LO Leakage vs LO Power at
fLO = 150MHz
LO LEAKAGE (dBm)
–4 –2
0
2
LO POWER (dBm)
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
65
5599 G40
–60
–6
Output IP2 vs LO Power at
fLO = 1260MHz
Output IP2 vs LO Power at
fLO = 900MHz
50
85°C
105°C
–10°C
–40°C
4
–8
85°C
105°C
–10°C
–40°C
5599 G39
65
OIP2 (dBm)
OIP2 (dBm)
65
60
3.3V
3.6V
2.7V
45
OIP2 (dBm)
70
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
55
50
85°C
105°C
–10°C
–40°C
4
60
5599 G38
Output IP2 vs LO Power at
fLO = 500MHz
75
75
DIGITAL GAIN = –4
16
OIP3 (dBm)
OIP3 (dBm)
19
20
85°C
DIGITAL GAIN = –4
105°C
–10°C
–40°C
OIP2 (dBm)
23
Output IP2 vs LO Power at
fLO = 150MHz
Output IP3 vs LO Power at
fLO = 1260MHz
85°C
105°C
–10°C
–40°C
4
85°C
105°C
–10°C
–40°C
–55 DIGITAL GAIN = –4
–60
DIGITAL GAIN = –10
–65
6
5599 G44
–70
–10
–8
–6
–4 –2
0
2
LO POWER (dBm)
4
6
5599 G45
5599f
10
For more information www.linear.com/LTC5599
LTC5599
Typical Performance Characteristics
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm, fLO = 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Side-Band Suppression vs
LO Power at fLO = 150MHz
–44
–40
SIDE-BAND SUPPRESSION (dBc)
–56
–60
DIGITAL
GAIN = –10
–64
–68
85°C
105°C
–10°C
–40°C
3.3V
3.6V
2.7V
–72
–76
–80
–10
–8
–6
–4 –2
0
2
LO POWER (dBm)
4
–45
85°C
105°C
–10°C
–40°C
3.3V
3.6V
2.7V
–50
–55
–60
–65
–10
6
–8
–6
–4 –2
0
2
LO POWER (dBm)
5599 G46
SIDE-BAND SUPPRESSION (dBc)
SIDE-BAND SUPPRESSION (dBc)
–55
–8
–6
3.3V
3.6V
2.7V
–4 –2
0
2
LO POWER (dBm)
–55
–60
4
85°C
105°C
–10°C
–40°C
–8
3.3V
3.6V
2.7V
–6
–4 –2
0
2
LO POWER (dBm)
4
6
5599 G48
Supply Current vs VCTRL Voltage
40
–41
–50
–65
–10
–50
–65
–10
6
–40
–45
85°C
105°C
–10°C
–40°C
–45
Side-Band Suppression vs
LO Power at fLO = 1260MHz
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
–60
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
5599 G47
Side-Band Suppression vs
LO Power at fLO = 900MHz
–40
4
6
–42
SUPPLY CURRENT (mA)
LO LEAKAGE (dBm)
–52
–40
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
DIGITAL GAIN = –4
–48
Side-Band Suppression vs
LO Power at fLO = 500MHz
SIDE-BAND SUPPRESSION (dBc)
LO Leakage vs LO Power at
fLO = 1260MHz
–43
–44
–45
–46 DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
–47
85°C
–48
105°C
3.3V
–10°C
3.6V
–49
–40°C
2.7V
–50
–10 –8 –6 –4 –2
0
2
LO POWER (dBm)
5599 G49
4
30
20
10
AGCTRL = 1
0
0.9 1.2 1.5
6
5599 G50
VCTRL Current vs VCTRL Voltage
Gain vs VCTRL Voltage
3.0
0
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
1.8 2.1 2.4 2.7
VCTRL VOLTAGE (V)
3
3.3
5599 G51
Output IP3 vs VCTRL Gain
25
AGCTRL = 1
AGCTRL = 1
20
–20
15
2.0
1.5
0.9
1.2
1.5
1.8 2.1 2.4
VCTRL (V)
2.7
3
3.3
5599 G52
–40
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
–60
–80
0.9
1.2
1.5
1.8
2.1 2.4 2.7
VCTRL VOLTAGE (V)
3
3.3
5599 G53
OIP3 (dBm)
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
GAIN (dB)
ICTRL (mA)
2.5
10
5
0
–5
–10
–27
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
–23
–19
–15
–11
GAIN SET BY VCTRL (dB)
–7
5599 G54
5599f
For more information www.linear.com/LTC5599
11
LTC5599
Typical Performance Characteristics
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm, fLO = 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Output IP2 vs VCTRL Gain
–30
65
LO LEAKAGE (dBm)
–40
OIP2 (dBm)
60
55
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
50
45
40
–17
–15
–13
–11
–9
GAIN SET BY VCTRL (dB)
–50
–60
–70
–80
–77
–7
5599 G55
GAIN – DIGITAL GAIN (dB)
GAIN (dB)
–13
–17
–21
–25
–19
–57 –47 –37 –27
GAIN SET BY VCTRL (dB)
–17
–11
–7
DIGITAL GAIN SETTING
–35
–40
–45
–50
–55
–7
–3
–4
–5
–6
–19
–3
5599 G58
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
–15
–11
–7
DIGITAL GAIN SETTING
–67
AGCTRL = 1
–57 –47 –37 –27
GAIN SET BY VCTRL (dB)
–17
–7
5599 G57
PRF, IM2, IM3 vs Baseband
Amplitude
PRF FOR DG = 0, –4, –8, –12, –16, –19,
–10
–30
IM3 FOR DG = 0, –19,
–50 –16, –4, –12, –8
–70
–90
0.1
–3
5599 G59
IM2 FOR DG = 0, –4, –8, –19, –12, –16
1
BASEBAND AMPLITUDE (VPEAK(DIFF))
5599 G60
LO Leakage vs LO Frequency for
Gain TempComp Off
Output IP2 vs Baseband Amplitude
Output IP3 vs Baseband Amplitude
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
5599 G56
10
AGCTRL = 1
–15
–67
–30
–60
–77
–2
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
–9
AGCTRL = 1
–25
Gain Minus Digital Gain vs Digital
Gain Setting
Gain vs Digital Gain Setting
–5
–20
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
SIDE-BAND SUPPRESSION (dBc)
AGCTRL = 1
PRF PER TONE (dBm), IM2, IM3 (dBc)
70
Side-Band Suppression vs
VCTRL Gain
LO Leakage vs VCTRL Gain
–40
70
20
TEMPUPDT = 1
–45
OIP2 (dBm)
OIP3 (dBm)
15
10
5
0
–5
0.1
LO LEAKAGE (dBm)
60
50
–50
–55
–60
40
DG = 0
DG = –8
DG = –16
DG = –4
DG = –12
DG = –19
1
BASEBAND AMPLITUDE (VPEAK(DIFF))
5599 G61
30
0.1
DG = 0
DG = –8
DG = –16
DG = –4
DG = –12
DG = –19
–65
1
BASEBAND AMPLITUDE (VPEAK(DIFF))
5599 G62
–70
50
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, 105°C
250
3.3V, –10°C
3.3V, –40°C
450
650
850 1050
LO FREQUENCY (MHz)
1250
5599 G63
5599f
12
For more information www.linear.com/LTC5599
LTC5599
Typical Performance Characteristics
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm, fLO = 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Worst-Case LO Leakage Over Five
Parts vs LO Frequency After 25°C
Calibration for Gain TempComp Off
–45
LO LEAKAGE (dBm)
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, 105°C
3.3V, –10°C
3.3V, –40°C
–50
–55
–60
–40
–40
3.3V, 25°C; 3.3V, 85°C; 3.3V, 105°C;
3.3V, –10°C; 3.3V, –40°C; 2.7V, 25°C AND
3.6V, 25°C BETWEEN WORST-CASE AND
BEST-CASE
–50
LO LEAKAGE (dBm)
–40
Worst-Case LO Leakage Over Five
Parts vs LO Frequency After 25°C
Calibration for Gain TempComp On
WORST-CASE: 3.3V, 105°C
–60
–70
450
650
850 1050
LO FREQUENCY (MHz)
–80
50
1250
BEST-CASE: 3.3V, 25°C
TEMPUPDT = 1
250
450
650
850 1050
LO FREQUENCY (MHz)
–40
BEST-CASE: 3.3V, 25°C
–50
–60
–70
50
TEMPUPDT = 1
250
450
650
850 1050
LO FREQUENCY (MHz)
1250
–30
3.3V, 25°C; 3.3V, 85°C; 3.3V, 105°C;
3.3V, –10°C; 3.3V, –40°C; 2.7V, 25°C AND
3.6V, 25°C BETWEEN WORST-CASE AND
BEST-CASE
WORST-CASE: 3.3V, 105°C
–40
BEST-CASE: 3.3V, 25°C
–50
5599 G66
–40
DG = –19
–70
50
–80
50
5599 G67
DG = 0
DG = –8
–60
–70
450
650
850 1050
LO FREQUENCY (MHz)
DG = –3
–50
–60
250
1250
DG = –17
DG = –4
450 650 850 1050 1250
RF FREQUENCY (MHz)
250
5599 G68
Side-Band Suppression vs LO
Frequency and Digital Gain Setting
After Calibration at DG = –4
1250
LO Leakage vs LO Frequency
and Digital Gain Setting After
Calibration at DG = –4
Worst-Case Side-Band Suppression Over
Five Parts vs LO Frequency After 25°C
Calibration for Gain TempComp On
SIDE-BAND SUPPRESSION (dBc)
3.3V, 25°C; 3.3V, 85°C; 3.3V, 105°C;
3.3V, –10°C; 3.3V, –40°C; 2.7V, 25°C AND
3.6V, 25°C BETWEEN WORST-CASE AND
BEST-CASE
WORST-CASE: 3.3V, 105°C
450
650
850 1050
LO FREQUENCY (MHz)
250
5599 G65
5599 G64
–30
–80
50
1250
LO LEAKAGE (dBm)
250
Worst-Case Side-Band Suppression Over
Five Parts vs LO Frequency After 25°C
Calibration for Gain TempComp Off
5599 G69
Temperature Sensing Diode
Voltage Cumulative Distribution
Supply Current Cumulative
Distribution
100
100
80
80
–30
–40
DG = –19
PERCENTAGE (%)
–20
DG = 0
DG = –12
–50
–60
60
25°C
40
–40°C
20
–70
–80
50
–40°C
105°C
PERCENTAGE (%)
SIDE-BAND SUPPRESSION (dBc)
–60
BEST-CASE: 3.3V, 25°C
–70
50
SIDE-BAND SUPPRESSION (dBc)
WORST-CASE: 3.3V, 105°C
–70
–65
–10
3.3V, 25°C; 3.3V, 85°C; 3.3V, 105°C;
3.3V, –10°C; 3.3V, –40°C; 2.7V, 25°C AND
3.6V, 25°C BETWEEN WORST-CASE AND
BEST-CASE
–50
LO LEAKAGE (dBm)
LO Leakage vs LO Frequency for
Gain TempComp On
DG = –4
250
DG = –3
450 650 850 1050 1250
RF FREQUENCY (MHz)
5599 G70
0
0.6
105°C
60
25°C
40
20
0.65
0.7
0.75
0.8
0.85
DIODE VOLTAGE FOR 100µA (V)
0.9
5599 G71
0
24
26
28
32
30
SUPPLY CURRENT (mA)
34
5599 G72
5599f
For more information www.linear.com/LTC5599
13
LTC5599
Typical Performance Characteristics
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm, fLO = 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Sleep Current Cumulative
Distribution
Gain Cumulative Distribution for
Gain TempComp Off
100
Gain Cumulative Distribution for
Gain TempComp On
100
100
80
80
PERCENTAGE (%)
PERCENTAGE (%)
80
60
105°C
40
PERCENTAGE (%)
25°C
60
25°C
130°C
–40°C
40
20
20
–40°C
60
105°C
40
25°C
20
–40°C
0
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
SLEEP CURRENT (µA)
0
–8.4
2
–8
TEMPUPDT = 1
5599 G73
Gain Cumulative Distribution for
VCTRL = 1.75V
0
–8.4
–6.4
–6.8
–7.2
–7.6
GAIN (dB)
–8
5599 G74
Gain Cumulative Distribution for
VCTRL = 1V
–6.8
–7.2
–7.6
GAIN (dB)
–6.4
5599 G75
Output IP3 Cumulative Distribution
100
100
100
80
80
80
NOTE 11
60
25°C
105°C
40
20
25°C
60
105°C
40
20
AGCTRL = 1
–16
–12
–14
GAIN (dB)
0
–80
–10
5599 G76
–40°C
PERCENTAGE (%)
25°C
60
105°C
40
0
50
–60
54
70
58 62
66
OUTPUT IP2 (dBm)
74
78
5599 G79
25°C
0
15
–50
100
80
80
105°C
60
40
0
–160
21
19
OUTPUT IP3 (dBm)
23
5599 G78
LO Leakage Cumulative Distribution
for Floating Baseband Pins
100
–40°C
17
5599 G77
25°C
20
20
–40°C
40
Noise Floor Cumulative
Distribution
NOTE 11
80
AGCTRL = 1
–70
GAIN (dB)
Output IP2 Cumulative
Distribution
100
60
20
PERCENTAGE (%)
0
–18
PERCENTAGE (%)
–40°C
PERCENTAGE (%)
–40°C
PERCENTAGE (%)
PERCENTAGE (%)
105°C
–40°C
60
105°C
40
25°C
20
–158
–156
–154
NOISE FLOOR (dBm/Hz)
–152
5599 G80
0
–60
–55
–50
–40
–45
LO LEAKAGE (dBm)
–35
5599 G81
5599f
14
For more information www.linear.com/LTC5599
LTC5599
Typical Performance Characteristics
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm, fLO = 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
LO Leakage Cumulative
Distribution for VCTRL = 1.75V
LO Leakage Cumulative
Distribution
100
100
60
25°C
40
20
80
105°C
PERCENTAGE (%)
PERCENTAGE (%)
105°C
60
25°C
40
–40°C
20
–55
–50
–40
–45
LO LEAKAGE (dBm)
0
–60 –55 –50 –45 –40 –35 –30 –25 –20
LO LEAKAGE (dBm)
–35
5599 G82
100
105°C
60
40
0
–60
5599 G83
25°C
–55
–40
–45
–50
SIDE-BAND SUPPRESSION (dBc)
–35
5599 G84
RF Return Loss
0
AGCTRL = 1
25°C
RESONANCE FREQUENCY WITH C4 = 10nF
–5
80
DG = –19
S22 (dB)
–10
60
–40°C
20
Side-Band Suppression Cumulative
Distribution for VCTRL = 1.75V
PERCENTAGE (%)
105°C
40
DG = –18
–15
DG = –17
–20
–25
–40°C
20
–30
DG = 0
0
–60
–55
–40
–45
–50
SIDE-BAND SUPPRESSION (dBc)
–35
–35
LO Return Loss for 30MHz and
70MHz Match, Schematic in Figure 3
0
REGISTER 0x00 SET
ACCORDING TO LO
FREQUENCY TABLE 5
–5
100
1000
RF FREQUENCY (MHz)
5599 G86
LO Return Loss
0
10
5599 G85
–5
–10
–10
–15
–15
70MHz
S11 (dB)
0
–60
100
AGCTRL = 1
80
–40°C
S11 (dB)
PERCENTAGE (%)
80
Side-Band Suppression
Cumulative Distribution
–20
30MHz
–20
–25
–25
–30
–30
–35
–35
10
100
1000
LO FREQUENCY (MHz)
REGISTER 0x00
SET TO 0x7F
10
5599 G87
100
LO FREQUENCY (MHz)
5599 G88
5599f
For more information www.linear.com/LTC5599
15
LTC5599
Typical Performance Characteristics
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm, fLO = 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
0
10
STANDARD REG 0x00 = 0x0A, L1 = 39nH, C5 = 15pF
900MHz REG 0x00 = 0x12, L1 = 8.2nH, C5 = 3.3pF
–5 1260MHz REG 0x00 = 0x01, L1 = 5.6nH, C5 = 3pF
–15
–20
–25
1260MHz
5
4
3
SOLID: EN = HIGH; DASHED: EN = LOW
700 900 1100 1300 1500 1700 1900
LO FREQUENCY (MHz)
5599 G89
1
0
–20
DG = –4
–16
–12
–8
–4
RF POWER (dBm)
10
DG = –19
5
DG = –19
2
–30
–35
500
6
DG = –8
DG = –10
DG = 0
DG = –12
DG = –16
15
DG = 0
DG = –8
DG = –10
DG = –12
DG = –16
7
900MHz
DG = –6
DG = –2
DG = –6
8
STANDARD
20
DG = –2
9
RMS EVM (%)
S11 (dB)
–10
Peak EVM vs RF Output Power
with 1Ms/s 16-QAM Signal
RMS EVM vs RF Output Power
with 1Ms/s 16-QAM Signal
EVMPEAK (%)
LO Return Loss for Standard,
900MHz and 1260MHz Match
0
4
5599 G90
0
–20
DG = –4
–16
–12
–8
–4
RF POWER (dBm)
0
4
5599 G91
5599f
16
For more information www.linear.com/LTC5599
LTC5599
Pin Functions
VCTRL (Pin 1): Variable Gain Control Input. This analog
control pin sets the gain. Write a “1” to bit 6 in register
0x01 (AGCTRL = 1) to activate this pin, resulting in about
2.58mA current draw from a positive supply. Typical VCTRL
voltage range is 0.9V to 3.3V. Gain transfer function is
not linear-in-dB. Tie to VCC when not used.
GND (Pins 2, 5, 12, Exposed Pad 25): Ground. All these
pins are connected together internally. For best RF performance all ground pins should be connected to RF ground.
LOL, LOC (Pins 3, 4): LO Inputs. This is not a differential input. Both pins are 50Ω inputs. An LC diplexer is
recommended to be used at these pins (see Figure 13).
AC-coupling capacitors are required at these pins if the
applied DC level is higher than ±100mV.
TTCK (Pin 6): Temperature Update. When the TTCK temperature update mode is selected in register 0x01 (bit 7
= High, TEMPUPDT = 1), the temperature readout and
digital gain compensation vs temperature can be updated
through a logic low to logic high transition at this pin. Do
not float.
BBPQ, BBMQ (Pins 10, 11): Baseband Inputs of the
Q-Channel. The input impedance of each input is about
1kΩ. It should be externally biased to a 1.4V common
mode level, or AC-coupled. Do not apply common mode
voltage beyond 2VDC. Float if Q-channel is disabled.
GNDRF (Pins 13, 14, 15, 17, 18): RF Ground. These pins
are connected together internally. For best RF performance
all ground pins should be connected to RF ground.
RF (Pin 16): RF Output. The output impedance at RF
frequencies is 50Ω. Its DC output voltage is about 1.7V
if enabled. An AC-coupling capacitor should be used at
this pin with a recommended value of 10nF.
CSB (Pin 19): Serial Port Chip Select. This CMOS input
initiates a serial port transaction when driven low, ending
the transaction when driven back high. Do not float.
SCLK (Pin 20): Serial Port Clock. This CMOS input clocks
serial port input data on its rising edge. Do not float.
SDI (Pin 21): Serial Port Data Input. The serial port uses
this CMOS input for data. Do not float.
TEMP (Pin 7): Temperature Sensing Diode. This pin is
connected to the anode of a diode that may be used to
measure the die temperature, by forcing a current and
measuring the voltage. This diode is not part of the onchip thermometer.
SDO (Pin 22): Serial Port Data Output. This NMOS output
presents data from the serial port during a read transaction.
Connect this pin to the digital supply voltage through a
pull-up resistor of sufficiently large value, to ensure that
the current does not exceed 10mA when pulled low.
BBPI, BBMI (Pins 8, 9): Baseband Inputs of the I-Channel.
The input impedance of each input is about 1kΩ. It should
be externally biased to a 1.4V common mode level, or ACcoupled. Do not apply common mode voltage beyond 2VDC.
EN (Pin 23): Enable Pin. The chip is completely turned
on when a logic high voltage is applied to this pin, and
completely turned off for a logic low voltage. Do not float.
VCC (Pin 24): Power Supply. It is recommended to use 1nF
and 4.7µF capacitors for decoupling to ground on this pin.
5599f
For more information www.linear.com/LTC5599
17
LTC5599
Block Diagram
CSB
19
SCLK SDI SDO
21
20
22
EN
VCC
23
24
SPI
BBPI 8
V
BBMI 9
I
I-CHANNEL
16 RF
0°
VCTRL 1
90°
BBPQ 10
V
BBMQ 11
2
I
5
THERMOMETER
Q-CHANNEL
12
GND
25
7
3
TEMP LOL
4
13
14
LOC
15
17
GNDRF
6 TTCK
18
5599 BD
5599f
18
For more information www.linear.com/LTC5599
LTC5599
Applications Information
The LTC5599 consists of I and Q input differential voltageto-current converters, I and Q upconverting mixers, an
RF output buffer and an LO quadrature phase generator.
An SPI bus addresses nine control registers, enabling
optimization of side-band suppression, LO leakage, and
adjustment of the modulator gain. See Table 1 for a summary of the writable registers and their default values.
A full map of all the registers in the LTC5599 is listed in
Table 10 and Table 11 in the Appendix.
Table 1. SPI Writable Registers and Default Register Values.
DEFAULT
VALUE
SETTING
REGISTER FUNCTION
0x00
0x2E
490MHz
LO Frequency Tuning
0x01
0x84
DG = –4
Gain
0x02
0x80
0mV
Offset I-Channel
0x03
0x80
0mV
Offset Q-Channel
0x04
0x80
0dB
I/Q Gain Ratio
ADDRESS
0x05
0x10
0°
I/Q Phase Balance
0x06
0x50
OFF
LO Port Matching Override
0x07
0x06
OFF
Temperature Correction
Override
0x08
0x00
NORMAL
Operating Mode
Without using the SPI the registers will use the default
values which may not result in the optimum side-band
suppression (SB). For example: for LO frequency from
about 400MHz to about 580MHz, the SB is about –45dBc;
from 380MHz to 400MHz and 580MHz to 630MHz it falls
to about –40dBc; from 350MHz to 380MHz and 630MHz
to 690MHz the SB falls to about –35dBc.
Aside of powering up the LTC5599, the register values can
be reset to the default values by setting SRESET = 1 (bit 3,
register 0x08). After about 50ns SRESET is automatically
set back to 0.
External I and Q baseband signals are applied to the differential baseband input pins: BBPI, BBMI and BBPQ,
BBMQ. These voltage signals are converted to currents and
translated to RF frequency by means of double-balanced
upconverting mixers. The mixer outputs are combined at
the inputs of the RF output buffer, which also transforms
the output impedance to 50Ω. The center frequency of the
resulting RF signal is equal to the LO signal frequency.
The LO inputs drive a phase shifter which splits the LO
signal into in-phase and quadrature signals which drive the
upconverting mixers. In most applications, the LOL input
is driven by the LO source via a 39nH inductor, while the
LOC input is driven by the LO source via a 15pF capacitor.
This inductor and capacitor form a diplexer circuit tuned
to 200MHz. The RF output is single-ended and internally
50Ω matched across a wide RF frequency range from
0.6MHz to 6GHz with better than 10dB return loss using
C4 = 10nF. See Figure 13.
Baseband Interface
The baseband inputs (BBPI, BBMI, BBPQ, BBMQ) present
a differential input impedance of about 1.8kΩ, as depicted
in Figure 1. The baseband bandwidth depends on the
source impedance and the frequency setting (register
0x00). It is recommended to compensate the baseband
input impedance in the baseband lowpass filter design in
order to achieve best gain flatness vs baseband frequency.
The S-parameters for (each of) the baseband inputs are
given in Table 2 for various LO frequency and gain settings.
VCC = 3.3V
+
1.4V
1
EN
VCTRL
2.5mA
1kΩ
8
9
1kΩ
BBPI
VCM = 1.4V
BBMI
35Ω
10pF
40Ω
3pF
40Ω
3pF
5599 F01
Figure 1. Simplified Circuit Schematic of the Base Band Input
Interface (Only One Channel Is Shown).
5599f
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19
LTC5599
Applications Information
Table 2. Differential Baseband (BB) Input Impedance vs
Table 2. Differential Baseband (BB) Input Impedance vs
Frequency for EN = High and VCMBB = 1.4V (continued)
Frequency for EN = High and VCMBB = 1.4V
BB
INPUT IMPEDANCE (W)
FREQUENCY
(MHz)
REAL*
IMAG* (CAP)
REFL
COEFFICIENT
MAG
ANGLE
LO FREQUENCY = 92MHz (REGISTER 0x00 = 0x79), DIGITAL GAIN = –4dB
1
1.90k
–7.17k (22.2pF)
0.900
–1.6
4
1.76k
–1.82k (21.9pF)
0.893
–6.3
10
1.25k
–751 (21.2pF)
0.854
–15
20
678
–429 (18.6pF)
0.755
–27
40
342
–308 (12.9pF)
0.585
–39
LO FREQUENCY = 150MHz (REGISTER 0x00 = 0x62), DIGITAL GAIN = –4dB
1
1.90k
–9.11k (17.5pF)
0.900
–1.3
4
1.82k
–2.30k (17.3pF)
0.896
–5.0
10
1.45k
–935 (17.0pF)
0.872
–12
20
887
–507 (15.7pF)
0.804
–23
40
441
–325 (12.2pF)
0.658
–36
100
226
–252 (6.3pF)
0.457
–51
LO FREQUENCY = 500MHz (REGISTER 0x00 = 0x2D), DIGITAL GAIN = –4dB
1
1.91k
–14.7k (10.6pF)
0.900
–0.8
4
1.89k
–3.74k (10.7pF)
0.899
–3.0
10
1.72k
–1.50k (10.7pF)
0.891
–7.7
20
1.35k
–769 (10.4pF)
0.864
–15
40
786
–426 (9.4pF)
0.785
–27
100
323
–251 (6.4pF)
0.583
–47
200
212
–190 (4.2pF)
0.478
–65
LO FREQUENCY = 500MHz (REGISTER 0x00 = 0x2D), DIGITAL GAIN = 0dB
1
1.56k
–15.0k (10.6pF)
0.879
–0.8
4
1.56k
–3.84k (10.4pF)
0.880
–3.0
10
1.48k
–1.52k (10.4pF)
0.874
–7.5
20
1.21k
–784 (10.2pF)
0.849
–15
40
753
–432 (9.2pF)
0.776
–27
100
323
–251 (6.3pF)
0.582
–47
200
213
–190 (4.2pF)
0.478
–65
LO FREQUENCY = 900MHz (REGISTER 0x00 = 0x12), DIGITAL GAIN = –4dB
1
1.91k
–17.0k (9.4pF)
0.901
–0.7
2
1.90k
–4.3k (9.3pF)
0.900
–2.7
10
1.77k
–1.72k (9.3pF)
0.893
–6.7
20
1.46k
–878 (9.1pF)
0.873
–13
40
915
–475 (8.4pF)
0.811
–24
0.622
–45
100
371
–261 (6.1pF)
200
233
–193 (4.1pF)
0.506
–62
BB
INPUT IMPEDANCE (W)
FREQUENCY
(MHz)
REAL*
IMAG* (CAP)
REFL
COEFFICIENT
MAG
EN = Low (Chip Disabled, REGISTER 0X00 = 0x2E)
1
2.04k
–18.2k (8.8pF)
0.906
2
2.02k
–4.59k (8.7pF)
0.906
10
1.91k
–1.84k (8.7pF)
0.901
20
1.59k
–935 (8.5pF)
0.893
40
1.01k
–502 (7.9pF)
0.826
100
402
–269 (5.9pF)
0.644
200
246
–197 (4.0pF)
0.522
*Parallel Equivalent
ANGLE
–0.6
–2.5
–6.3
–12
–23
–43
–60
The circuit is optimized for a common mode voltage of 1.4V
which can be internally or externally applied. In case of ACcoupling to the baseband pins (1.4V internally generated
bias) make sure that the high pass filter corner is not
affecting the low frequency components of the baseband
signal. Even a small error for low baseband frequencies
can result in degraded EVM.
The baseband input offset voltage depends on the source
resistance. In case of AC-coupling the 1 sigma offset is
about 1.1mV, resulting in about –46.6dBm LO leakage.
For shorted baseband pins (0Ω source resistance), the
LO leakage improves to about –50.1dBm. In case of ACcoupling the LO leakage can be reduced by connecting a
resistor in parallel with the baseband inputs, thus lowering baseband input impedance and offset. Further, the
low combined baseband input leakage current of 1.3nA
in shutdown mode retains the voltage over the coupling
capacitors, which helps to settle faster when the part is
enabled again. It is recommended to drive the baseband
inputs differentially to improve the linearity. When a DAC is
used as the signal source, a reconstruction filter should be
placed between the DAC output and the LTC5599 baseband
inputs to avoid aliasing.
Internal Gain Trim DACs
Four internal gain trim DACs (one for each baseband pin)
are configured as 11-bit each. The usable DAC input value
range is integer continuous from 64 to 2047 and 0 for
shutdown. The DACs are not intended for baseband signal
5599f
20
For more information www.linear.com/LTC5599
LTC5599
Applications Information
generation but for gain and offset setting only, because
there are no reconstruction filters between the DACs and
the mixer core, and there is only indirect access between
the DAC values and the register settings. The following
functions are implemented in this way:
• Coarse digital gain control with 1dB steps
• Fine digital gain control with 0.1dB steps
• Gain-temperature correction
• DC offset adjustment in the I-channel
• DC offset adjustment in the Q-channel
• I/Q gain balance control
• Disable Q-channel
• Continuous variable gain control
Coarse Digital Gain Control (DG) with 1dB Steps
(Register 0x01)
Twenty digital gain positions 1dB apart are implemented
by hardwiring a corresponding DAC code for all four
DACs. The coarse digital gain is set by writing to the five
least-significant bits in register 0x01, see Table 10 and 11.
The gain is the highest for code 00000 (code 0 = 0dB, DG
= 0) and the lowest for code 10011 (code 19 = –19dB,
DG = –19). Note that the gain 0dB set by the digital gain
control is not the same as the voltage gain of the part.
The remaining 12 codes (decimal 20 to 31) are reserved.
The digital gain in dB equals minus the decimal value written into the 5 least-significant bits of the gain register. The
formula relating the modulator gain G(in V/V) relative to
the maximum conversion gain therefore equals:
G(V/V) = 10(DG/20)
Fine Digital Gain Control(FDG) with 0.1dB Steps and
Gain-Temperature Correction (Register 0x07)
Sixteen digital gain positions about 0.1dB apart can be set
directly using the four least-significant bits in register 0x07
combined with bit 2 = 1 in register 0x08 (TEMPCORR = 1).
For coarse digital gain settings code 9 and higher some or
more subsequent codes of the fine digital gain positions
may be the same due to the limited resolution of the 11bit DACs. The main purpose of these 0.1dB gain steps is
to implement an automatic gain/temperature correction
which can be activated by setting TEMPCORR = 1. In that
case, the input of the fine digital gain control will be the
on-chip thermometer. The on-chip thermometer generates
a 4-bit digital code with code 0 corresponding to –30°C
and code 15 corresponding to 120°C and 10°C spacing
between the codes. The on-chip thermometer output code
can be updated continuous (by clearing TEMPUPDT, bit 7
in register 0x01, see Table 10) or can be updated by bringing the external pin TTCK from low to high (and setting
TEMPUPTD = 1). In case of continuous update the code
will be an asynchronous update whenever the temperature
crosses a certain threshold. In some cases it is desired to
prevent a gain update to happen in the middle of a data
frame. In that case, the gain/temperature update can be
synchronized using the TTCK pin for example at the beginning or end of a data frame. The on-chip temperature can
be read back by reading register 0x1F (TEMP[3:0]).The
decimal value of TEMP[3:0] is given by:
TEMP[3:0] = round(T/10) + 3
with T the actual on-chip temperature in °C. It’s accuracy
is about ±10°C. TEMP[3:0] defaults to 7 after an EN low
to high transition with TEMPUPDT = 1. Switching from
TEMPUPDT = 0 to TEMPTUPDT = 1, TEMP[3:0] indicates
the temperature during the last time TTCK went from low
to high. Note that the actual on-chip temperature cannot
be read if TEMPCORR = 1 or when TEMPUPDT = 1 without
toggling TTCK.
Analog Gain Control
The LTC5599 supports analog control of the conversion
gain through a voltage applied to VCTRL (pin 1). The gain
can be controlled downward from the digital gain setting
(DG) programmed in register 0x01. In order to minimize
distortion in the RF output signal the AGCTRL bit (bit 6 in
register 0x01) should be set to 1. If analog gain control is
not used, VCTRL should be connected to VCC and AGCTRL
set to 0; this saves about 2.58mA of supply current. The
typical usable gain control range is from 0.9V to 3.3V.
Setting VCTRL to a voltage lower than VCC with AGCTRL
= 0 significantly impairs the linearity of the RF output
signal and lowers the VCTRL response time. A simplified
schematic is shown in Figure 1.
5599f
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21
LTC5599
Applications Information
I/Q DC Offset Adjustment (Registers 0x02 and 0x03)
and LO Leakage
Offsets in the I- and Q-channel translates into LO leakage
at the RF port. This offset can either be caused by the
I/Q modulator or, in case the baseband connections are
DC-coupled, applied externally. Registers 0x02 and 0x03
(I-offset and Q-offset) can be set to cancel this offset
and hence lower the LO leakage. To adjust the offset in
the I-channel, the BBPI DAC is set to a (slightly) different
value than the BBMI DAC, introducing an offset. These
8-bit registers defaults are 128 and represents 0 offset.
The register value can be set from 1 to 255. The value 0
represents an unsupported code and should not be used.
Since the input referred offset depends on the gain the
input offset value (VOS) can be calculated as:
VOS = 1260/((3632 • G)/(NOS – 128) – (NOS – 128)
/(3632 • G))
and Vos = 0 for Nos =128. G represents the gain from Table 3.
Table 3. Coarse Digital Gain (DG) Register Settings.
A positive offset means that the voltage of the positive
input terminal (BBPI or BBPQ) is increased relative to the
negative input terminal (BBMI or BBMQ).
I/Q Gain Ratio (Register 0x04) and Side-Band
Suppression
The 8-bit I/Q gain ratio register 0x04 controls the ratio of
the I-channel mixer conversion gain GI and the Q-channel
mixer conversion gain GQ. Together with the quadrature
phase imbalance register 0x05, register 0x04 allows further
optimization of the modulator side-band suppression.
The expression relating the gain ratio GI/GQ to the contents
of the 8-bit register 0x04, represented by decimal NIQ and
the nominal conversion gain G equals:
20 log (GI/GQ) = 20 log ((3632 • G – (NIQ – 128))/
(3632 • G +(NIQ –128))) (dB)
The step size of the gain ratio trim in dB vs NIQ is approximately constant for the same digital gain setting.
For digital gain setting = –4, for example, the step size
is about 7.6mdB. Table 4 lists the gain step size for each
digital gain setting that follows from the formula above.
DG (dB)
G(V/V)
DEC
BINARY
HEX
0
1.000
0
00000
0x00
–1
0.891
1
00001
0x01
–2
0.794
2
00010
0x02
–3
0.708
3
00011
0x03
DG (dB)
G (V/V)
–4
0.631
4
00100
0x04
∆GI/GQ (mdB)
0
1.000
4.8
–5
0.562
5
00101
0x05
–1
0.891
5.4
–6
0.501
6
00110
0x06
–2
0.794
6.0
–7
0.447
7
00111
0x07
–3
0.708
6.8
–8
0.398
8
01000
0x08
–4
0.631
7.6
–9
0.355
9
01001
0x09
–5
0.562
8.5
Table 4. I/Q Gain Ratio Step Size vs Digital Gain
Setting
–10
0.316
10
01010
0x0A
–6
0.501
9.6
–11
0.282
11
01011
0x0B
–7
0.447
10.7
–12
0.251
12
01100
0x0C
–8
0.398
12.0
–13
0.224
13
01101
0x0D
–9
0.355
13.5
–14
0.200
14
01110
0x0E
–10
0.316
15.1
–15
0.178
15
01111
0x0F
–11
0.282
17.1
–16
0.158
16
10000
0x10
–12
0.251
19.2
–17
0.141
17
10001
0x11
–13
0.224
21.5
–18
0.126
18
10010
0x12
–14
0.200
24.2
–19
0.112
19
10011
0x13
–15
0.178
27.3
5599f
22
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LTC5599
Applications Information
Table 5. Register 0x00 Setting vs LO Frequency (continued)
Table 4. I/Q Gain Ratio Step Size vs Digital Gain
Setting (continued)
DG (dB)
G (V/V)
∆GI/GQ (mdB)
–16
0.158
30.7
–17
0.141
34.6
–18
0.126
39.0
–19
0.112
44.1
REGISTER VALUE
LO FREQUENCY RANGE (MHz)
DECIMAL
BINARY
HEX
LOWER BOUND
UPPER BOUND
15
0001111
0F
961.8
988.2
16
0010000
10
941.3
961.7
17
0010001
11
921.5
941.2
18
0010010
12
895.2
921.4
19
0010011
13
877.6
895.1
20
0010100
14
863.6
877.5
21
0010101
15
843.2
863.5
22
0010110
16
826.9
843.1
23
0010111
17
807.0
826.8
24
0011000
18
792.3
806.9
25
0011001
19
772.2
792.2
26
0011010
1A
752.7
772.1
27
0011011
1B
734.0
752.6
28
0011100
1C
724.2
739.9
29
0011101
1D
704.6
724.1
30
0011110
1E
688.7
704.5
The internal LO chain consists of a poly-phase filter which
generates the I and Q signals for the image-reject doublebalanced mixer. The center frequency of the poly-phase
filter is set by the lower seven bits of register 0x00. The
recommended settings vs LO frequency are given in Table 5
(see the QuikEval™ GUI).
31
0011111
1F
673.2
688.6
32
0100000
20
655.2
673.1
33
0100001
21
638.1
655.1
34
0100010
22
624.6
638.0
35
0100011
23
611.9
624.5
36
0100100
24
598.4
611.8
Table 5. Register 0x00 Setting vs LO Frequency
37
0100101
25
585.1
598.3
38
0100110
26
573.9
585.0
39
0100111
27
563.1
573.8
40
0101000
28
548.1
563.0
41
0101001
29
538.1
548.0
42
0101010
2A
529.1
538.0
43
0101011
2B
518.5
529.0
44
0101100
2C
507.0
518.4
45
0101101
2D
497.7
506.9
46
0101110
2E
488.0
497.6
47
0101111
2F
471.5
487.9
48
0110000
30
457.7
471.4
49
0110001
31
448.7
457.6
50
0110010
32
437.4
448.6
51
0110011
33
426.6
437.3
52
0110100
34
417.5
426.5
53
0110101
35
407.5
417.4
54
0110110
36
398.0
407.4
The conversion gain of the I-channel and Q-channel are
equal for NIQ = 128. The I-channel gain is larger than the
Q-channel gain for NIQ > 128.
Disable Q-Channel
If bit 5 in register 0x01 (QDISABLE) is set, the Q-channel
is switched off, turning the I/Q modulator into an upconversion mixer. It is recommended to float the BBPQ and
BBMQ pins in this mode. The default mode is Q-channel
is on (QDISABLE = 0).
LO Section (Register 0x00)
REGISTER VALUE
LO FREQUENCY RANGE (MHz)
DECIMAL
BINARY
HEX
LOWER BOUND
UPPER BOUND
0
0000000
00
N/A
N/A
1
0000001
01
1249.1
1300.0
2
0000010
02
1248.6
1249.0
3
0000011
03
1238.1
1248.5
4
0000100
04
1214.1
1238.0
5
0000101
05
1191.2
1214.0
6
0000110
06
1165.6
1191.1
7
0000111
07
1141.0
1165.5
8
0001000
08
1120.6
1140.9
9
0001001
09
1100.5
1120.5
10
0001010
0A
1069.5
1100.4
11
0001011
0B
1039.6
1069.4
12
0001100
0C
1023.1
1039.5
13
0001101
0D
1007.1
1023.0
14
0001110
0E
988.3
1007.0
5599f
For more information www.linear.com/LTC5599
23
LTC5599
Applications Information
Table 5. Register 0x00 Setting vs LO Frequency (continued)
REGISTER VALUE
DECIMAL
BINARY
Table 5. Register 0x00 Setting vs LO Frequency (continued)
LO FREQUENCY RANGE (MHz)
HEX
REGISTER VALUE
LO FREQUENCY RANGE (MHz)
LOWER BOUND
UPPER BOUND
DECIMAL
BINARY
HEX
LOWER BOUND
UPPER BOUND
55
0110111
37
390.1
397.9
96
1100000
60
153.6
156.6
56
0111000
38
382.8
390.0
97
1100001
61
151.1
153.5
57
0111001
39
376.6
382.7
98
1100010
62
148.6
151.0
58
0111010
3A
369.8
376.5
99
1100011
63
142.5
148.5
59
0111011
3B
353.1
369.7
100
1100100
64
139.6
142.4
60
0111100
3C
339.0
353.0
101
1100101
65
136.5
139.5
61
0111101
3D
332.6
338.9
102
1100110
66
134.3
136.4
62
0111110
3E
327.2
332.5
103
1100111
67
131.2
134.2
63
0111111
3F
320.6
327.1
104
1101000
68
128.1
131.1
64
1000000
40
313.7
320.5
105
1101001
69
126.0
128.0
65
1000001
41
309.1
313.6
106
1101010
6A
123.8
125.9
66
1000010
42
304.5
309.0
107
1101011
6B
121.3
123.7
67
1000011
43
288.1
304.4
108
1101100
6C
118.3
121.2
68
1000100
44
278.3
288.0
109
1101101
6D
115.7
118.2
69
1000101
45
274.2
278.2
110
1101110
6E
113.5
115.6
70
1000110
46
270.3
274.1
111
1101111
6F
111.3
113.4
71
1000111
47
266.0
270.2
112
1110000
70
109.5
111.2
72
1001000
48
261.9
265.9
113
1110001
71
107.6
109.4
73
1001001
49
258.2
261.8
114
1110010
72
105.6
107.5
74
1001010
4A
254.1
258.1
115
1110011
73
103.0
105.5
75
1001011
4B
243.6
254.0
116
1110100
74
100.3
102.9
76
1001100
4C
233.8
243.5
117
1110101
75
98.5
100.2
77
1001101
4D
230.8
233.7
118
1110110
76
96.6
98.4
78
1001110
4E
228.0
230.7
119
1110111
77
94.7
96.5
79
1001111
4F
220.2
227.9
120
1111000
78
93.0
94.6
80
1010000
50
212.6
220.1
121
1111001
79
30.0
92.9
81
1010001
51
210.0
212.5
122
1111010
7A
N/A
N/A
82
1010010
52
207.6
209.9
123
1111011
7B
N/A
N/A
83
1010011
53
202.1
207.5
124
1111100
7C
N/A
N/A
84
1010100
54
196.2
202.0
125
1111101
7D
N/A
N/A
85
1010101
55
193.7
196.1
126
1111110
7E
N/A
N/A
86
1010110
56
191.2
193.6
127
1111111
7F
N/A
N/A
87
1010111
57
186.6
191.1
88
1011000
58
182.0
186.5
89
1011001
59
179.4
181.9
90
1011010
5A
176.0
179.3
91
1011011
5B
170.1
175.9
92
1011100
5C
165.0
170.0
93
1011101
5D
162.5
164.9
94
1011110
5E
160.0
162.4
95
1011111
5F
156.7
159.9
A simplified circuit schematic of the LOL and LOC interfaces is depicted in Figure 2. The LOL and LOC inputs are
not differential LO inputs. They are 50Ω inputs and are
intended to be driven with an inductor going to the LOL
input and a capacitor to the LOC input. Do not switch the
capacitor and inductor, as this will result in very poor
performance. For a wideband LO range an inductor value
of 39nH and a capacitor value of 15pF (standard LO match)
5599f
24
For more information www.linear.com/LTC5599
LTC5599
Applications Information
is recommended at these pins, forming a diplexer circuit
with center frequency of 200MHz. This diplexer helps to
improve the uncalibrated side-band suppression significantly around 200MHz. Even for LO frequencies far from
200MHz the diplexer performs better than a single-ended
LO drive or a differential drive. Due to factory calibration
of the poly-phase filter the typical side-band suppression
is about 50dBc for frequencies from 100MHz to 700MHz
and 45dBc from 700MHz to 1300MHz. For narrow-band
applications far from 200MHz it may help to tune the
diplexer to a different frequency which can improve the
uncalibrated side-band suppression and the gain vs LO
drive level. The Typical Performance Characteristics section
shows the return loss for a 900MHz match (L1 = 8.2nH,
C5 = 3.3pF) and a 1260MHz match (L1 = 5.6nH, C5 = 3pF).
To get a performance with the standard 200MHz match
equivalent to the 900MHz and 1260MHz match, the LO
power should be increased by 1.5dB and 2dB respectively.
Register 0x00 values of Table 5 may have to be adjusted
as well, in case the standard match is not used.
3
4
LOL
LOC
5599 F02
Figure 2. Simplified Circuit Schematic for the LOL and LOC Inputs
Below 100MHz the matching network of Figure 3 can be
used.The side-band suppression in that case is largely
defined by the diplexer L1, C5 and the (temperature dependent) LOL and LOC input impedance. See measured
performance in the Typical Performance Characteristics
section.
30MHz/70MHz
LO
L2
120nH/51nH
C19
180pF/47pF
L1
47nH/43nH
C5
560pF/120pF
C20
270pF/100pF
C21
270pF/100pF
3 LOL
4 LOC
5599 F03
Figure 3. Impedance Matching Network for LOL and LOC
Interfaces Matched at 30MHz/70MHz
Table 6 lists LOL and LOC port input impedance vs frequency
at EN = High and PLO = 0dBm. The other LO port (LOC or
LOL) is terminated in a 50Ω.
Table 6. LOL, LOC Port Input Impedance vs Frequency for EN
= High and PLO = 0dBm (Other LO Port Terminated with 50Ω to
Ground)
FREQ
(MHz)
REG
0x00
20
30
LOL/LOC PORT IMPEDANCE (W) REFL COEFFICIENT
REAL*
IMAG* (IND)
MAG
ANGLE
79
7.9
24.3 (194nH)
0.750
175
79
9.1
19.0 (101nH)
0.743
172
40
79
10.8
17.4 (69nH)
0.732
169
50
79
13.0
17.6 (56nH)
0.716
165
60
79
15.7
18.9 (50nH)
0.693
162
70
79
18.6
21.4 (49nH))
0.661
158
80
79
21.6
25.0 (50nH)
0.618
154
90
79
24.4
30.3 (54nH)
0.564
151
100
75
27.0
38.3 (61nH))
0.497
148
110
70
29.0
51.4 (74nH)
0.419
146
120
6C
30.3
76.1 (101nH)
0.338
149
130
68
32.3
109.3 (134nH)
0.276
150
140
64
34.3
121.6 (138nH)
0.247
148
150
62
36.2
119.4 (127nH)
0.234
142
160
5E
37.4
149.1 (148nH))
0.201
143
170
5C
37.1
357.5 (335nH)
0.160
162
180
59
39.6
188.6 (167nH)
0.164
141
190
57
41.4
192.0 (161nH))
0.150
135
200
54
40.7
418.6 (333nH)
0.116
156
*Parallel Equivalent
The circuit schematic of the demo board is shown in
Figure 13.
I/Q Phase Balance Adjustment Register 0x05 and
Side-Band Suppression
Ideally the I-channel LO phase is exactly 90° ahead of the
Q-channel LO phase, so called quadrature. In practice however, the I/Q phase difference differs from exact quadrature
by a small error due to component parameter variations
and harmonic content in the LO signal (see below).
The I/Q phase imbalance register (0x05) allows adjustment of the I/Q phase shift to compensate for such errors.
Together with gain ratio register 0x04, it can thus be used
to optimize the side-band suppression of the modulator.
5599f
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25
LTC5599
Applications Information
Register 0x05 contains two parts (see Table 11); the five
least significant bits IQPHF realize a fine phase adjustment,
while the three most significant bits IQPHE are used for
coarse adjustments. The fine phase adjustment realized
by IQPHF can be approximated as:
jIQ = –((Nph –16)/15) • ln(fLO/50) (degrees)
for 30MHz < fLO < 1300MHz
where Nph is the decimal value of IQPHF and fLO is the
frequency of the LO signal in MHz. A positive value for
jIQ means that the I-channel LO phase is more than 90°
ahead of the Q-channel LO phase. Notice from the expression that the phase adjustment range and resolution are
coupled, and dependent on the LO frequency. At low LO
frequencies the the smallest adjustment range and highest
resolution is achieved, while high LO frequencies exhibit
the largest range and lowest resolution.
The extension bits IQPHE provide a larger phase adjustment range, particularly useful at lower LO frequencies,
and overcome another trade-off; between phase adjustment
range and the maximum center frequency of the polyphase filter. The latter trade-off is due to the fact that the
capacitances in the I-channel, CppI, and Q-channel, CppQ, of
the poly-phase filter control both these parameters. Their
difference sets the phase shift, while their sum determines
the center frequency of the filter.
The extension bits IQPHE introduce a large phase offset in
addition to the fine adjustment realized by the IQPHF bits.
The sign of this large offset can be positive or negative,
controlled by IQPHSIGN (bit 7 in register 0x00). Including
these bits, the total phase shift from quadrature can be
expressed as:
As a side effect, the extension bits slightly detune the
center frequency of the poly-phase filter, after crossing the
boundary to a new NCOARSE value. This can be observed
as a large step in the actual phase shift. A solution for this
is to decrease the value in the frequency register 0x00
(increase the poly-phase filter center frequency) at the
NCOARSE value boundaries. The result is a smooth phase
adjustment. In the demo board QuikEval GUI, this LO frequency register adjustment is automatically taken care of.
Whenever the poly-phase filter center frequency is adjusted
to improve the smoothness of the phase adjustment, it is
recommended to manually program the LO port impedance
match using the CLOO bits in register 0x06. By default,
changing the filter center frequency also automatically
adjusts the matching of the LO port (when CLOEN, bit 4
in register 0x06 is set). However, since the LO carrier
frequency does not change, automatic adjustment of the
LO match is undesirable in this case; it may add another
large step to the phase adjustment. Instead, the LO match
should remain unchanged while the filter center frequency
is adjusted. This can be achieved as follows. First, the
current LO matching configuration is read from the CLO
bits in register 0x1D, and written to the CLOO override
bits in register 0x06. Subsequently, the CLOEN bit (bit 4,
register 0x06) is cleared to disable automatic LO match
adjustment. As a result the center frequency can be adjusted in register 0x00 without changing the LO match.
At 100MHz the maximum phase shift is about ±9.8°, while
at 1GHz it is about ±3°. The extension bits are not useful
above 988.2MHz since the poly-phase center frequency
register 0x00 value cannot be adjusted low enough to
ensure a smooth transition to a new NCOARSE value.
jIQ = –(MPH/15) • ln(fLO/50) (degrees) with
Square Wave LO Drive
MPH = NCOARSE + NPH –16 and
Harmonic content of the LO signal adversely affects
quadrature phase error and gain accuracy, whenever a
poly-phase filter is used for quadrature generation. The
LTC5599 can correct for phase and gain errors due to harmonics in the LO carrier (e.g. in a square wave) by setting
appropriate values in the I/Q gain and I/Q phase registers.
Such adjustments are typically needed when the 3rd-order
harmonic of the LO signal exceeds the desirable side-band
suppression minus 13dB. Although the poly-phase filter
is less sensitive to the second harmonic content of the LO
NCOARSE = 32 • (–1)IQPHSIGN + 1 • NEXT
where Next equals the decimal value of the IQPHE bits. The
valid range of values for (Nph –16) is thus expanded from
{–16, –15, ... , +15} to {–240, –239, ... , +239}. Table 9 in
the Appendix lists all the possible combinations. The coding ranges for IQPHSIGN = 0 and IQPHSIGN = 1 overlap
between Mph = –16 and Mph = +15, such that IQPHSIGN
only needs to be changed for larger phase shifts.
5599f
26
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LTC5599
Applications Information
carrier, it’s influence can still be significant. For –15dBc
second harmonic content, the side-band suppression can
degrade to –45dBc; for –20dBc it is –54dBc, assuming no
I/Q gain and phase adjustments are made.
Table 7. RF Output Impedance vs Frequency and Digital Gain
Setting (DG) for EN = High (continued)
OUTPUT IMPEDANCE (W)
REFL
COEFFICIENT
FREQUENCY
(MHz)
DG
(dB)
REAL*
IMAG* (CAP)
MAG
ANGLE
RF Output
600
–16
58
–1.77k (0.15pF)
0.078
–12
After upconversion, the RF outputs of the I and Q mixers
are combined. An on-chip buffer performs internal differential to single-ended conversion, while transforming
the output signal to 50Ω as shown in Figure 4.
600
–18
62
–1.44k (0.18pF)
0.109
–11
600
–19
77
–680 (0.39pF)
0.217
–14
VCC
1300
0
48
–802 (0.15pF)
0.035
–119
1300
–12
51
–807 (0.15pF)
0.034
–68
1300
–16
55
–709 (0.17pF)
0.059
–41
1300
–18
59
–526 (0.23pF)
0.098
–35
1300
–19
73
–280 (0.44pF)
0.215
–36
*Parallel Equivalent
The RF port output impedance for EN = Low is given in
Table 8.
50Ω
RF
16
Table 8. RF Output Impedance vs Frequency for EN = Low
5599 F04
OUTPUT IMPEDANCE (W)
REFL
COEFFICIENT
FREQUENCY
(MHz)
REAL*
IMAG* (CAP)
MAG
ANGLE
Table 7 shows the RF port output impedance vs frequency
and digital gain setting for EN = High.
30
16.1k
–7.76k (0.68pF)
0.994
–0.7
40
16.2k
–5.24k (0.76pF)
0.994
–1.1
50
15.7k
–3.96k (0.80pF)
0.994
–1.4
Table 7. RF Output Impedance vs Frequency and Digital Gain
Setting (DG) for EN = High
60
16.5k
–3.18k (0.83pF)
0.994
–1.8
70
16.8k
–2.66k (0.86pF)
0.994
–2.2
80
16.4k
–2.29k (0.87pF)
0.994
–2.5
Figure 4. Simplified Circuit Schematic for the RF Output Port
FREQUENCY
(MHz)
DG
(dB)
OUTPUT IMPEDANCE (W)
REFL
COEFFICIENT
REAL*
IMAG* (CAP)
MAG
ANGLE
30
0
59
–413 (12.8pF)
0.104
–43
30
–12
61
–465 (11.4pF)
0.114
–35
30
–16
64
–529 (10.0pF)
0.133
–27
30
–18
69
–623 (8.5pF)
0.166
–19
30
–19
83
–902 (5.9pF)
0.249
–10
50
0
56
–671 (4.7pF)
0.068
–38
50
–12
58
–762 (4.2pF)
0.082
–27
50
–16
61
–859 (3.7pF)
0.107
–19
50
–18
67
–972 (3.3pF)
0.146
–13
50
–19
81
–1.21k (2.6pF)
0.239
–8
100
0
55
–1.08k (1.5pF)
0.050
–30
100
–12
57
–1.32k (1.2pF)
0.066
–19
100
–16
60
–1.55k (1.0pF)
0.096
–12
100
–18
66
–1.75k (0.91pF)
0.142
–8
100
–19
82
–1.98k (0.80pF)
0.246
–5
600
0
54
–1.35k (0.20pF)
0.040
–30
600
–12
56
–1.75k (0.15pF)
0.057
–16
90
17.1k
–2.01k (0.88pF)
0.994
–2.9
100
17.9k
–1.79k (0.89pF)
0.994
–3.2
200
14.7k
–856 (0.93pF)
0.993
–6.7
250
11.1k
–679 (0.94pF)
0.991
–8.4
300
8.55k
–563 (0.94pF)
0.988
–10
350
7.97k
–481 (0.94pF)
0.988
–12
400
6.42k
–420 (0.95pF)
0.985
–14
450
5.27k
–373 (0.95pF)
0.982
–15
500
4.26k
–336 (0.95pF)
0.977
–17
600
3.05k
–281 (0.94pF)
0.969
–20
700
2.32k
–241 (0.94pF)
0.959
–23
800
1.85k
–211 (0.94pF)
0.950
–27
900
1.54k
–188 (0.94pF)
0.941
–30
1000
1.30k
–169 (0.94pF)
0.932
–33
1100
1.12k
–154 (0.94pF)
0.923
–36
1200
991
–141 (0.94pF)
0.914
–39
1300
881
–129 (0.95pF)
0.906
–42
*Parallel Equivalent
5599f
For more information www.linear.com/LTC5599
27
LTC5599
Applications Information
serial bus master device first taking CSB low to enable
the LTC5599’s port. Input data applied on SDI is clocked
on the rising edge of SCLK, with all transfers MSB first.
The communication burst is terminated by the serial bus
master returning CSB high. See Figure 6 for details.
For VCC = 3.3V and EN = High the RF pin voltage is about
1.68V. For VCC = 3.3V and EN = Low the RF pin voltage
is about 3.1V.
Enable Interface
Figure 5 shows a simplified schematic of the EN pin
interface. The voltage necessary to turn on the LTC5599 is
1.1V. To disable (shut down) the chip, the enable voltage
must be below 0.2V.
Data is read from the part during a communication burst
using SDO. Readback may be multidrop (more than one
LTC5599 connected in parallel on the serial bus), as SDO
is high impedance (Hi-Z) when CSB = 1, or when data is
not being read from the part. If the LTC5599 is not used
in a multidrop configuration, or if the serial port master
is not capable of setting the SDO line level between read
sequences, it is recommended to attach a resistor between
SDO and VCC_L to ensure the line returns to VCC_L during
Hi-Z states. The resistor value should be large enough
to ensure that the SDO output current does not exceed
10mA. See Figure 7 for details.
VCC
23
INTERNAL
ENABLE
CIRCUIT
EN
5599 F05
Figure 5. Simplified Circuit Schematic of the EN interface
Single Byte Transfers
SERIAL PORT
The serial port is arranged as a simple memory map, with
status and control available in 9 read/write and 23 readonly byte-wide registers. All data bursts are comprised of
at least two bytes. The 7 most significant bits of the first
byte are the register address, with an LSB of 1 indicating
a read from the part, and LSB of 0 indicating a write to the
part. The subsequent byte, or bytes, is data from/to the
The SPI-compatible serial port provides control and
monitoring functionality.
Communication Sequence
The serial bus is comprised of CSB, SCLK, SDI and
SDO. Data transfers to the part are accomplished by the
MASTER–CSB
tCSS
tCKL
tCKH
tCSS
tCSH
MASTER–SCLK
tCS
MASTER–SDI
tCH
DATA
DATA
5599 F06
Figure 6. Serial Port Write Timing Diagram
MASTER–CSB
8TH CLOCK
MASTER–SCLK
tDO
LTC5599–SDO
tDO
tDO
tDO
DATA
DATA
5599 F07
Figure 7. Serial Port Read Timing Diagram
5599f
28
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LTC5599
Applications Information
specified register address. See Figure 8 for an example of a
detailed write sequence, and Figure 9 for a read sequence.
byte of the second burst contains the destination register
address (Addr1) and an LSB indicating a write. The next
byte on SDI is the data intended for the register at address
Addr1. CSB is then taken high to terminate the transfer.
Figure 10 shows an example of two write communication
bursts. The first byte of the first burst sent from the serial
bus master on SDI contains the destination register address (Addr0) and an LSB of 0 indicating a write. The next
byte is the data intended for the register at address Addr0.
CSB is then taken high to terminate the transfer. The first
Note that the written data is transferred to the internal
register at the falling edge of the 16th clock cycle (parallel load).
MASTER–CSB
16 CLOCKS
MASTER–SCLK
7-BIT REGISTER ADDRESS
MASTER–SDI
8 BITS OF DATA
PARALLEL LOAD
A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0
0 = WRITE
LTC5599–SD0
5599 F08
Figure 8. Serial Port Write Sequence
MASTER–CSB
16 CLOCKS
MASTER–SCLK
7-BIT REGISTER ADDRESS
MASTER–SDI
1 = READ
A6 A5 A4 A3 A2 A1 A0 1
8 BITS OF DATA
LTC5599–SDO
X D7 D6 D5 D4 D3 D2 D1 D0 DX
5599 F09
Figure 9. Serial Port Read Sequence
MASTER–CSB
MASTER–SDI
ADDR0 + WR
BYTE 0
ADDR1 + WR
LTC5599–SDO
BYTE 1
5599 F10
Figure 10. Serial Port Single Byte Writes
5599f
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29
LTC5599
Applications Information
Multiple Byte Transfers
Multidrop Configuration
More efficient data transfer of multiple bytes is accomplished by using the LTC5599’s register address autoincrement feature as shown in Figure 11. The serial port
master sends the destination register address in the first
byte and its data in the second byte as before, but continues
sending bytes destined for subsequent registers. Byte 1’s
address is Addr0+1, Byte 2’s address is Addr0+2, and so
on. If the resister address pointer attempts to increment
past 31 (0x1F), it is automatically reset to 0.
Several LTC5599s may share the serial bus. In this
multidrop configuration, SCLK, SDI, and SDO are common
between all parts. The serial bus master must use a separate
CSB for each LTC5599 and ensure that only one device has
CSB asserted at any time. It is recommended to attach a
high value resistor to SDO to ensure the line returns to a
known level (VCC_L) during Hi-Z states.
An example of an auto-increment read from the part is
shown in Figure 12. The first byte of the burst sent from
the serial bus master on SDI contains the destination register address (Addr0) and an LSB of 1 indicating a read.
Once the LTC5599 detects a read burst, it takes SDO out
of the Hi-Z condition and sends data bytes sequentially,
beginning with data from register Addr0. The part ignores
all other data on SDI until the end of the burst.
The memory map of the LTC5599 may be found in the
Appendix in Table 10, with detailed bit descriptions found
in Table 11. The register address shown in hexadecimal
format under the ADDR column is used to specify each
register. Each register is denoted as either read-only (R)
or read-write (R/W). The register’s default value on device
power-up or after a reset (bit 3, register 0x08, SRESET)
is shown at the right.
Serial Port Registers
MASTER–CSB
MASTER–SDI
ADDR0 + WR
BYTE 0
BYTE 1
BYTE 2
LTC5599–SDO
5599 F11
Figure 11. Serial Port Auto-Increment Write
MASTER–CSB
MASTER–SDI
LTC5599–SDO
ADDR0 + RD
DON’T CARE
BYTE 0
BYTE 1
BYTE 2
5599 F12
Figure 12. Serial Port Auto-Increment Read
5599f
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LTC5599
Applications Information
SPI Signal Levels
is not done properly, the RF performance will degrade.
Figures 14 and 15 show the component side and bottom
side of the evaluation board.
The SPI bus supports signal levels from a digital VCC_L
from 1.2V to 3.6V. The CSB = 1.2V condition creates an
additional static input sleep current of 0.2µA. For CSB =
1.8V the extra sleep current can be neglected.
Ferrite bead FB1 limits the supply voltage ramping speed
in case VCC is abruptly connected to a voltage source. In
the application, limit the VCC ramp speed to a maximum
of 1V/µs.
Evaluation Board
Figure 13 shows the evaluation board schematic. A good
ground connection is required for the exposed pad. If this
VCC_L
1.2V TO 3.6V
VCC
2.7V TO 3.6V
C17
100nF
FB1
FERRITE BEAD
TDK, MPZ1608S331AT
R18
1k
(RPULL-UP)
R19, 1k
C1
4.7µF
R23, 1k
C18
2.2pF
R1, 1Ω
1
2
L1, 39nH
C5, 15pF
VCTRL
GNDRF
GND
GNDRF
3 LOL
LTC5599IUF
4 LOC
5 GND
RF
GNDRF
GNDRF
GNDRF
6 TTCK
TTCK
C13
2.2pF
C12
2.2pF
C10
2.2pF
SCLK
CSB
25
24 23 22 21 20 19
GND VCC EN SDO SDI SCLK CSB
C3
100nF
LO
SDI
R25, 1k
C2
1nF
EN
VCTRL
SDO
R26, 1k
18
C4
10nF
17
16
RF
15
14
13
TEMP BBPI BBMI BBPQ BBMQ GND
8
7
9
10
12
11
TEMP
BBPQ
BBPI
BBPQ
BBMQ
R9
49.9Ω
R8
49.9Ω
C7
100nF
R10
49.9Ω
C6
100nF
C8
100nF
BOARD NUMBER: DC2091A
R11
49.9Ω
C9
100nF
5599 F13
Figure 13. Evaluation Circuit Schematic
5599f
For more information www.linear.com/LTC5599
31
LTC5599
Applications Information
Figure 14. Evaluation Board Component Side
Figure 15. Evaluation Board Bottom Side
5599f
32
For more information www.linear.com/LTC5599
LTC5599
Appendix
Phase Shift Register (0x05) Map
This appendix summarizes the detailed value assignments
for the phase shift register, including the extension bits
and sign bit (bit 7 in register 0x00).
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00)
MPH
NCOARSE
NPH
BPH
–240
–224
0
011100000
–239
–224
1
011100001
–238
–224
2
011100010
–237
–224
3
011100011
–236
–224
4
011100100
–235
–224
5
011100101
–234
–224
6
011100110
–233
–224
7
011100111
–232
–224
8
011101000
–231
–224
9
011101001
–230
–224
10
011101010
–229
–224
11
011101011
–228
–224
12
011101100
–227
–224
13
011101101
–226
–224
14
011101110
–225
–224
15
011101111
–224
–224
16
011110000
–223
–224
17
011110001
–222
–224
18
011110010
–221
–224
19
011110011
–220
–224
20
011110100
–219
–224
21
011110101
–218
–224
22
011110110
–217
–224
23
011110111
–216
–224
24
011111000
–215
–224
25
011111001
–214
–224
26
011111010
–213
–224
27
011111011
–212
–224
28
011111100
–211
–224
29
011111101
–210
–224
30
011111110
–209
–224
31
011111111
–208
–192
0
011000000
–207
–192
1
011000001
–206
–192
2
011000010
–205
–192
3
011000011
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
MPH
NCOARSE
NPH
BPH
–204
–192
4
011000100
–203
–192
5
011000101
–202
–192
6
011000110
–201
–192
7
011000111
–200
–192
8
011001000
–199
–192
9
011001001
–198
–192
10
011001010
–197
–192
11
011001011
–196
–192
12
011001100
–195
–192
13
011001101
–194
–192
14
011001110
–193
–192
15
011001111
–192
–192
16
011010000
–191
–192
17
011010001
–190
–192
18
011010010
–189
–192
19
011010011
–188
–192
20
011010100
–187
–192
21
011010101
–186
–192
22
011010110
–185
–192
23
011010111
–184
–192
24
011011000
–183
–192
25
011011001
–182
–192
26
011011010
–181
–192
27
011011011
–180
–192
28
011011100
–179
–192
29
011011101
–178
–192
30
011011110
–177
–192
31
011011111
–176
–160
0
010100000
–175
–160
1
010100001
–174
–160
2
010100010
–173
–160
3
010100011
–172
–160
4
010100100
–171
–160
5
010100101
–170
–160
6
010100110
–169
–160
7
010100111
–168
–160
8
010101000
–167
–160
9
010101001
–166
–160
10
010101010
–165
–160
11
010101011
–164
–160
12
010101100
5599f
For more information www.linear.com/LTC5599
33
LTC5599
Appendix
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
MPH
NCOARSE
NPH
BPH
MPH
NCOARSE
NPH
BPH
–163
–160
13
010101101
–122
–128
22
010010110
–162
–160
14
010101110
–121
–128
23
010010111
–161
–160
15
010101111
–120
–128
24
010011000
–160
–160
16
010110000
–119
–128
25
010011001
–159
–160
17
010110001
–118
–128
26
010011010
–158
–160
18
010110010
–117
–128
27
010011011
–157
–160
19
010110011
–116
–128
28
010011100
–156
–160
20
010110100
–115
–128
29
010011101
–155
–160
21
010110101
–114
–128
30
010011110
–154
–160
22
010110110
–113
–128
31
010011111
–153
–160
23
010110111
–112
–96
0
001100000
–152
–160
24
010111000
–111
–96
1
001100001
–151
–160
25
010111001
–110
–96
2
001100010
–150
–160
26
010111010
–109
–96
3
001100011
–149
–160
27
010111011
–108
–96
4
001100100
–148
–160
28
010111100
–107
–96
5
001100101
–147
–160
29
010111101
–106
–96
6
001100110
–146
–160
30
010111110
–105
–96
7
001100111
–145
–160
31
010111111
–104
–96
8
001101000
–144
–128
0
010000000
–103
–96
9
001101001
–143
–128
1
010000001
–102
–96
10
001101010
–142
–128
2
010000010
–101
–96
11
001101011
–141
–128
3
010000011
–100
–96
12
001101100
–140
–128
4
010000100
–99
–96
13
001101101
–139
–128
5
010000101
–98
–96
14
001101110
–138
–128
6
010000110
–97
–96
15
001101111
–137
–128
7
010000111
–96
–96
16
001110000
–136
–128
8
010001000
–95
–96
17
001110001
–135
–128
9
010001001
–94
–96
18
001110010
–134
–128
10
010001010
–93
–96
19
001110011
–133
–128
11
010001011
–92
–96
20
001110100
–132
–128
12
010001100
–91
–96
21
001110101
–131
–128
13
010001101
–90
–96
22
001110110
–130
–128
14
010001110
–89
–96
23
001110111
–129
–128
15
010001111
–88
–96
24
001111000
–128
–128
16
010010000
–87
–96
25
001111001
–127
–128
17
010010001
–86
–96
26
001111010
–126
–128
18
010010010
–85
–96
27
001111011
–125
–128
19
010010011
–84
–96
28
001111100
–124
–128
20
010010100
–83
–96
29
001111101
–123
–128
21
010010101
–82
–96
30
001111110
5599f
34
For more information www.linear.com/LTC5599
LTC5599
Appendix
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
MPH
NCOARSE
NPH
BPH
MPH
NCOARSE
NPH
BPH
–81
–96
31
001111111
–40
–32
8
000101000
–80
–64
0
001000000
–39
–32
9
000101001
–79
–64
1
001000001
–38
–32
10
000101010
–78
–64
2
001000010
–37
–32
11
000101011
–77
–64
3
001000011
–36
–32
12
000101100
–76
–64
4
001000100
–35
–32
13
000101101
–75
–64
5
001000101
–34
–32
14
000101110
–74
–64
6
001000110
–33
–32
15
000101111
–73
–64
7
001000111
–32
–32
16
000110000
–72
–64
8
001001000
–31
–32
17
000110001
–71
–64
9
001001001
–30
–32
18
000110010
–70
–64
10
001001010
–29
–32
19
000110011
–69
–64
11
001001011
–28
–32
20
000110100
–68
–64
12
001001100
–27
–32
21
000110101
–67
–64
13
001001101
–26
–32
22
000110110
–66
–64
14
001001110
–25
–32
23
000110111
–65
–64
15
001001111
–24
–32
24
000111000
–64
–64
16
001010000
–23
–32
25
000111001
–63
–64
17
001010001
–22
–32
26
000111010
–62
–64
18
001010010
–21
–32
27
000111011
–61
–64
19
001010011
–20
–32
28
000111100
–60
–64
20
001010100
–19
–32
29
000111101
–59
–64
21
001010101
–18
–32
30
000111110
000111111
–58
–64
22
001010110
–17
–32
31
–57
–64
23
001010111
–16
0
0
x00000000
–56
–64
24
001011000
–15
0
1
x00000001
–55
–64
25
001011001
–14
0
2
x00000010
–54
–64
26
001011010
–13
0
3
x00000011
–53
–64
27
001011011
–12
0
4
x00000100
–52
–64
28
001011100
–11
0
5
x00000101
–51
–64
29
001011101
–10
0
6
x00000110
–50
–64
30
001011110
–9
0
7
x00000111
–49
–64
31
001011111
–8
0
8
x00001000
–48
–32
0
000100000
–7
0
9
x00001001
–47
–32
1
000100001
–6
0
10
x00001010
–46
–32
2
000100010
–5
0
11
x00001011
–45
–32
3
000100011
–4
0
12
x00001100
–44
–32
4
000100100
–3
0
13
x00001101
–43
–32
5
000100101
–2
0
14
x00001110
–42
–32
6
000100110
–1
0
15
x00001111
–41
–32
7
000100111
0
0
16
x00010000
5599f
For more information www.linear.com/LTC5599
35
LTC5599
Appendix
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
MPH
NCOARSE
NPH
BPH
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
MPH
NCOARSE
NPH
BPH
1
0
17
x00010001
42
32
26
100111010
2
0
18
x00010010
43
32
27
100111011
3
0
19
x00010011
44
32
28
100111100
4
0
20
x00010100
45
32
29
100111101
5
0
21
x00010101
46
32
30
100111110
6
0
22
x00010110
47
32
31
100111111
7
0
23
x00010111
48
64
0
101000000
8
0
24
x00011000
49
64
1
101000001
9
0
25
x00011001
50
64
2
101000010
10
0
26
x00011010
51
64
3
101000011
11
0
27
x00011011
52
64
4
101000100
12
0
28
x00011100
53
64
5
101000101
13
0
29
x00011101
54
64
6
101000110
14
0
30
x00011110
55
64
7
101000111
15
0
31
x00011111
56
64
8
101001000
16
32
0
100100000
57
64
9
101001001
17
32
1
100100001
58
64
10
101001010
18
32
2
100100010
59
64
11
101001011
19
32
3
100100011
60
64
12
101001100
20
32
4
100100100
61
64
13
101001101
21
32
5
100100101
62
64
14
101001110
22
32
6
100100110
63
64
15
101001111
23
32
7
100100111
64
64
16
101010000
24
32
8
100101000
65
64
17
101010001
25
32
9
100101001
66
64
18
101010010
26
32
10
100101010
67
64
19
101010011
27
32
11
100101011
68
64
20
101010100
28
32
12
100101100
69
64
21
101010101
29
32
13
100101101
70
64
22
101010110
30
32
14
100101110
71
64
23
101010111
31
32
15
100101111
72
64
24
101011000
32
32
16
100110000
73
64
25
101011001
33
32
17
100110001
74
64
26
101011010
34
32
18
100110010
75
64
27
101011011
35
32
19
100110011
76
64
28
101011100
36
32
20
100110100
77
64
29
101011101
37
32
21
100110101
78
64
30
101011110
38
32
22
100110110
79
64
31
101011111
39
32
23
100110111
80
96
0
101100000
40
32
24
100111000
81
96
1
101100001
41
32
25
100111001
82
96
2
101100010
5599f
36
For more information www.linear.com/LTC5599
LTC5599
Appendix
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
MPH
NCOARSE
NPH
BPH
MPH
NCOARSE
NPH
BPH
83
96
3
101100011
124
128
12
110001100
128
13
110001101
128
14
110001110
84
96
4
101100100
125
85
96
5
101100101
126
86
96
6
101100110
127
128
15
110001111
87
96
7
101100111
128
128
16
110010000
88
96
8
101101000
129
128
17
110010001
89
96
9
101101001
130
128
18
110010010
90
96
10
101101010
131
128
19
110010011
91
96
11
101101011
132
128
20
110010100
92
96
12
101101100
133
128
21
110010101
93
96
13
101101101
134
128
22
110010110
94
96
14
101101110
135
128
23
110010111
95
96
15
101101111
136
128
24
110011000
96
96
16
101110000
137
128
25
110011001
97
96
17
101110001
138
128
26
110011010
98
96
18
101110010
139
128
27
110011011
99
96
19
101110011
140
128
28
110011100
100
96
20
101110100
141
128
29
110011101
101
96
21
101110101
142
128
30
110011110
102
96
22
101110110
143
128
31
110011111
103
96
23
101110111
144
160
0
110100000
104
96
24
101111000
145
160
1
110100001
105
96
25
101111001
146
160
2
110100010
106
96
26
101111010
147
160
3
110100011
107
96
27
101111011
148
160
4
110100100
108
96
28
101111100
149
160
5
110100101
109
96
29
101111101
150
160
6
110100110
110
96
30
101111110
151
160
7
110100111
111
96
31
101111111
152
160
8
110101000
112
128
0
110000000
153
160
9
110101001
154
160
10
110101010
113
128
1
110000001
114
128
2
110000010
155
160
11
110101011
156
160
12
110101100
115
128
3
110000011
116
128
4
110000100
157
160
13
110101101
158
160
14
110101110
117
128
5
110000101
118
128
6
110000110
159
160
15
110101111
160
16
110110000
160
17
110110001
119
128
7
110000111
160
120
128
8
110001000
161
121
128
9
110001001
162
160
18
110110010
122
128
10
110001010
163
160
19
110110011
123
128
11
110001011
164
160
20
110110100
5599f
For more information www.linear.com/LTC5599
37
LTC5599
Appendix
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
MPH
NCOARSE
NPH
BPH
MPH
NCOARSE
NPH
BPH
165
160
21
110110101
205
192
29
111011101
166
160
22
110110110
206
192
30
111011110
167
160
23
110110111
207
192
31
111011111
168
160
24
110111000
208
224
0
111100000
169
160
25
110111001
209
224
1
111100001
170
160
26
110111010
210
224
2
111100010
171
160
27
110111011
211
224
3
111100011
172
160
28
110111100
212
224
4
111100100
173
160
29
110111101
213
224
5
111100101
174
160
30
110111110
214
224
6
111100110
175
160
31
110111111
215
224
7
111100111
176
192
0
111000000
216
224
8
111101000
177
192
1
111000001
217
224
9
111101001
178
192
2
111000010
218
224
10
111101010
179
192
3
111000011
219
224
11
111101011
180
192
4
111000100
220
224
12
111101100
181
192
5
111000101
221
224
13
111101101
182
192
6
111000110
222
224
14
111101110
183
192
7
111000111
223
224
15
111101111
184
192
8
111001000
224
224
16
111110000
185
192
9
111001001
225
224
17
111110001
186
192
10
111001010
226
224
18
111110010
187
192
11
111001011
227
224
19
111110011
188
192
12
111001100
228
224
20
111110100
189
192
13
111001101
229
224
21
111110101
190
192
14
111001110
230
224
22
111110110
191
192
15
111001111
231
224
23
111110111
192
192
16
111010000
232
224
24
111111000
193
192
17
111010001
233
224
25
111111001
194
192
18
111010010
234
224
26
111111010
195
192
19
111010011
235
224
27
111111011
196
192
20
111000100
236
224
28
111111100
237
224
29
111111101
197
192
21
111010101
198
192
22
111010110
238
224
30
111111110
199
192
23
111010111
239
224
31
111111111
200
192
24
111011000
201
192
25
111011001
202
192
26
111011010
203
192
27
111011011
204
192
28
111011100
5599f
38
For more information www.linear.com/LTC5599
LTC5599
appendix
Table 10. Serial Port Register Contents
ADDR
MSB
[6]
[5]
[4]
[3]
[2]
[1]
LSB
R/W
DEFAULT
0x00
IQPHSIGN
FREQ[6]
FREQ[5]
FREQ[4]
FREQ[3]
FREQ[2]
FREQ[1]
FREQ[0]
R/W
0x2E
0x01
TEMPUPDT
AGCTRL
QDISABLE
GAIN[4]
GAIN[3]
GAIN[2]
GAIN[1]
GAIN[0]
R/W
0x84
0x02
OFFSETI[7] OFFSETI[6] OFFSETI[5] OFFSETI[4] OFFSETI[3] OFFSETI[2] OFFSETI[1] OFFSETI[0]
R/W
0x80
0x03
OFFSETQ[7] OFFSETQ[6] OFFSETQ[5] OFFSETQ[4] OFFSETQ[3] OFFSETQ[2] OFFSETQ[1] OFFSETQ[0]
R/W
0x80
R/W
0x80
0x04
IQGR[7]
IQGR[6]
IQGR[5]
IQGR[4]
IQGR[3]
IQGR[2]
IQGR[1]
IQGR[0]
0x05
IQPHE[2]
IQPHE[1]
IQPHE[0]
IQPHF[4]
IQPHF[3]
IQPHF[2]
IQPHF[1]
IQPHF[0]
R/W
0x10
CLOO[3]
CLOO[2]
CLOO[1]
CLOO[0]
R/W
0x50
GAINF[2]
GAINF[1]
GAINF[0]
R/W
0x06
0x06
0x07
*
0†
*
0†
*
0†
CLOEN
0†
GAINF[3]
0x08
0†
0†
0†
0†
SRESET
0x00
0†
0†
0†
0†
0†
0†
0†
*
0†
R/W
0x09
R
0x00
0x0A
CHIPID[7]
CHIPID[6]
CHIPID[5]
CHIPID[4]
CHIPID[3]
CHIPID[2]
CHIPID[1]
CHIPID[0]
R
0x01
0x0B
0†
0†
0†
0†
FUSE[3]
FUSE[2]
FUSE[1]
FUSE[0]
R
0x0X
0x0C
0†
0†
CPPP0[5]
CPPP0[4]
CPPP0[3]
CPPP0[2]
CPPP0[1]
CPPP0[0]
R
0xXX
0x0D
0†
CPPP1[6]
CPPP1[5]
CPPP1[4]
CPPP1[3]
CPPP1[2]
CPPP1[1]
CPPP1[0]
R
0x0X
0x0E
0†
0†
CPPM0[5]
CPPM0[4]
CPPM0[3]
CPPM0[2]
CPPM0[1]
CPPM0[0]
R
0xXX
0x0F
0†
CPPM1[6]
CPPM1[5]
CPPM1[4]
CPPM1[3]
CPPM1[2]
CPPM1[1]
CPPM1[0]
R
0x0X
0x10
0†
GPI0[6]
GPI0[5]
GPI0[4]
GPI0[3]
GPI0[2]
GPI0[1]
GPI0[0]
R
0x08
0x11
GPI1[7]
GPI1[6]
GPI1[5]
GPI1[4]
GPI1[3]
GPI1[2]
GPI1[1]
GPI1[0]
R
0xFF
0x12
0†
GPI2[6]
GPI2[5]
GPI2[4]
GPI2[3]
GPI2[2]
GPI2[1]
GPI2[0]
R
0x01
0x13
0†
GMI0[6]
GMI0[5]
GMI0[4]
GMI0[3]
GMI0[2]
GMI0[1]
GMI0[0]
R
0x08
0x14
GMI1[7]
GMI1[6]
GMI1[5]
GMI1[4]
GMI1[3]
GMI1[2]
GMI1[1]
GMI1[0]
R
0xFF
0x15
0†
GMI2[6]
GMI2[5]
GMI2[4]
GMI2[3]
GMI2[2]
GMI2[1]
GMI2[0]
R
0x01
0x16
0†
GPQ0[6]
GPQ0[5]
GPQ0[4]
GPQ0[3]
GPQ0[2]
GPQ0[1]
GPQ0[0]
R
0x08
0x17
GPQ1[7]
GPQ1[6]
GPQ1[5]
GPQ1[4]
GPQ1[3]
GPQ1[2]
GPQ1[1]
GPQ1[0]
R
0xFF
0x18
0†
GPQ2[6]
GPQ2[5]
GPQ2[4]
GPQ2[3]
GPQ2[2]
GPQ2[1]
GPQ2[0]
R
0x01
0x19
0†
GMQ0[6]
GMQ0[5]
GMQ0[4]
GMQ0[3]
GMQ0[2]
GMQ0[1]
GMQ0[0]
R
0x08
TEMPCORR THERMINP
0x1A
GMQ1[7]
GMQ1[6]
GMQ1[5]
GMQ1[4]
GMQ1[3]
GMQ1[2]
GMQ1[1]
GMQ1[0]
R
0xFF
0x1B
0†
GMQ2[6]
GMQ2[5]
GMQ2[4]
GMQ2[3]
GMQ2[2]
GMQ2[1]
GMQ2[0]
R
0x01
0x1C
0†
0†
0†
0†
0†
0†
0†
0†
R
0x00
0x1D
0†
0†
0†
0†
CLO[3]
CLO[2]
CLO[1]
CLO[0]
R
0x00
0x1E
0†
0†
0†
GOR
IDT[3]
IDT[2]
IDT[1]
IDT[0]
R
0x04
0x1F
0†
0†
0†
0†
TEMP[3]
TEMP[2]
TEMP[1]
TEMP[0]
R
0x0Y
*unused †read-only; values written are disregarded, X = production dependent, Y = resets to 7 after EN from Low to High with TEMPUPDT = 1, for EN =
Low all read-only (R) registers default to 0x00.
5599f
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39
LTC5599
appendix
Table 11. Serial Port Register Bit Field Summary
FUNCTION
DESCRIPTION
AGCTRL
CHIPID[7:0]
CLO[3:0]
CLOO[3:0]
CLOEN
BITS
Analog Gain Control Enable
Chip ID
LO Port Match Cap Array
LO Port Cap Array Override
Automatic LO Match Enable
Enables analog control through VCTRL (Pin 1) when AGCTRL = 1.
CPPM0[5:0]
CPPM1[6:0]
CPPP0[5:0]
CPPP1[6:0]
FREQ[6:0]
FUSE[3:0]
GAIN[4:0]
GAINF[3:0]
GMI0[6:0]
GMI1[7:0]
GMI2[6:0]
GMQ0[6:0]
GMQ1[7:0]
GMQ2[6:0]
GOR
GPI0[6:0]
GPI1[7:0]
GPI2[6:0]
GPQ0[6:0]
GPQ1[7:0]
GPQ2[6:0]
IDT[3:0]
IQGR[7:0]
IQPHE[2:0]
IQPHF[4:0]
IQPHSIGN
CppQ Fine Control
CppQ Coarse Control
CppI Fine Control
CppI Coarse Control
Poly-Phase Filter Frequency
Fuse Read Out
Coarse Digital Gain Control
Fine Digital Gain Control
Fine GMI DAC Read-Out
Coarse GMI DAC Read-Out1
Coarse GMI DAC Read-Out2
Fine GMQ DAC Read-Out
Coarse GMQ DAC Read-Out1
Coarse GMQ DAC Read-Out2
Gain Out of Range
Fine GPI DAC Read-Out
Coarse GPI DAC Read-Out1
Coarse GPI DAC Read-Out2
Fine GPQ DAC Read-Out
Coarse GPQ DAC Read-Out1
Coarse GPQ DAC Read-Out2
RF Buffer Bias
I/Q Gain Ratio Control
I/Q Phase Extension Bits
Fine I/Q Phase Balance
Control
Sign IQ Phase Extension Bits
OFFSETI[7:0]
OFFSETQ[7:0]
QDISABLE
I-Channel Offset Control
Q-Channel Offset Control
Disable Q-Channel
SRESET
TEMP[3:0]
TEMPCORR
Soft Reset
Thermometer Output
Temperature Correction
Disable
Temperature Correction
Update
TEMPUPDT
THERMINP
Thermometer Input Select
LO port match, automatically adjusted through programming FREQ[6:0]
Programs LO port match capacitor array when CLOEN = 0
Automatic LO port impedance matching enabled when CLOEN = 1. Override
bits CLOO[3:0] control LO port match when CLOEN = 0.
CppQ = CPPM0[5:0] + number of 1’s in CPPM1[6:0] × 64
CppI = CPPP0[5:0] + number of 1’s in CPPP1[6:0] × 64
Programs the center frequency of the poly-phase filter, according to Table 5.
Programs the conversion gain in 1dB steps, according to Table 3.
Conversion gain control in approximately 0.1dB steps, when TEMPCORR = 1.
BBMI input stage gain GmI.
GmI = GMI0[6:0] + (number of 1’s in GMI1[7:0] and GMI2[6:0]) × 128
BBMQ input stage gain GmQ.
GmQ = GMQ0[6:0] + (number of 1’s in GMQ1[7:0] and GMQ2[6:0]) × 128
For DG < –19 GOR = 1; Else GOR = 0
BBPI input stage gain GpI.
GpI = GPI0[6:0] + (number of 1’s in GPI1[7:0] and GPI2[6:0]) × 128
BBPQ input stage gain GpQ.
GpQ = GPQ0[6:0] + (number of 1’s in GPQ1[7:0] and GPQ2[6:0]) × 128
Adjust the gain difference in approximate constant steps in dB. See Table 4.
Extend the IQ phase adjustment range. See Table 9.
Fine adjustment of IQ LO phase difference. See Table 9. Zero phase shift for
0x10.
Encodes the sign of the IQ phase extension bits IQPHE[2:0]. Positive for
IQPHSIGN = 1.
Adjusts DC offset in the I-channel. Zero offset for 0x80. See page 19.
Adjusts DC offset in the Q-channel. Zero offset for 0x80. See page 19.
QDISABLE = 1 shuts down the Q-channel, turning the LTC5599 into an
upconversion mixer.
Writing 1 to this bit resets all registers to their default values.
Digital representation of die temperature. Step size about 10°C.
TEMPCORR = 1 disables temperature correction of the gain, and enables
manual fine-adjustment using bits GAINF[3:0].
TEMPUPDT = 1 synchronizes temperature correction of the gain to a LOW
- HIGH transition on the TTCK pin. Asynchronous correction for TEMPUPDT
= 0.
For test purposes only. Should be set to 0.
VALID VALUES DEFAULT
0, 1
1
0x00 to 0x0F
0x00 to 0x0F
0, 1
1
1
0x00
0x00
1
0x00 to 0x5F
0x00 to 0x7F
0x00 to 0x5F
0x00 to 0x7F
0x00 to 0x79
0x00 to 0x0F
0x00 to 0x13
0x00 to 0x0F
0x00 to 0x7F
0x00 to 0x07
0x00 to 0x07
0x00 to 0x7F
0x00 to 0x07
0x00 to 0x07
0, 1
0x00 to 0x7F
0x00 to 0x07
0x00 to 0x07
0x00 to 0x7F
0x00 to 0x07
0x00 to 0x07
0x00 to 0x0D
0x00 to 0xFF
0x00 to 0x07
0x00 to 0x1F
0xXX
0x0X
0xXX
0x0X
0x2E
0x0X
0x04
0x00
0x08
0xFF
0x01
0x08
0xFF
0x01
0
0x08
0xFF
0x01
0x08
0xFF
0x01
0x04
0x80
0x00
0x10
0, 1
0
0x01 to 0xFF
0x01 to 0xFF
0, 1
0x80
0x80
0
0, 1
0x00 to 0x07
0, 1
0
0x07
0
0, 1
1
0
0
5599f
40
For more information www.linear.com/LTC5599
LTC5599
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
0.70 ±0.05
4.50 ±0.05
2.45 ±0.05
3.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ±0.05
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
2.45 ±0.10
(4-SIDES)
(UF24) QFN 0105 REV B
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
5599f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
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41
LTC5599
Typical Application
VCTRL
3.3V
22, 21, 20, 19
24
1nF + 4.7µF
VCC
LTC5599
SPI
RF = 90MHz
to 1300MHz
8
I-DAC
9
V
I
16
1
10nF
PA
0°
23
EN
I-CHANNEL
90°
13, 14, 15, 17, 18
10
Q-DAC
11
V
I
BASEBAND
GENERATOR
Q-CHANNEL
39nH
3
4
THERMOMETER
2, 5, 12
6
TTCK
5599 TA01a
VCO/SYNTHESIZER
15pF
Figure 16. 90MHz to 1300MHz Direct Conversion Transmitter Application
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5599f
42 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC5599
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC5599
LT 0814 • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2014