CYPRESS CY62147CV18

CY62147CV18 MoBL2™
256K x 16 Static RAM
Features
• High speed
— 55 ns and 70 ns availability
• Low voltage range:
— 1.65V−1.95V
• Pin-compatible w/ CY62147BV18
• Ultra-low active power
— Typical Active Current: 0.5 mA @ f = 1 MHz
•
•
•
•
— Typical Active Current: 2 mA @ f = fmax (70 ns speed)
Low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The CY62147CV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when: deselected (CE HIGH), outputs
are disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the Truth Table at the back of this data sheet for a complete
description of read and write modes.
The CY62147CV18 is available in a 48-ball FBGA package.
Logic Block Diagram
DATA IN DRIVERS
A6
A5
A4
A3
A2
A1
A0
256K x 16
RAM Array
2048 X 2048
SENSE AMPS
A8
A7
ROW DECODER
A10
A9
I/O0–I/O7
I/O8–I/O15
Power-down
Circuit
Cypress Semiconductor Corporation
Document #: 38-05011 Rev. *C
•
BHE
WE
CE
OE
BLE
A15
A16
A17
A12
A13
A14
A11
COLUMN DECODER
CE
3901 North First Street
BHE
BLE
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 28, 2002
CY62147CV18 MoBL2™
Pin Configuration[1, 2]
FBGA
Top View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11 A17
A7
I/O3
Vccq
D
VCC
I/O12 DNU
A16
I/O4
Vssq
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
DC Input Voltage[3] ................................ –0.2V to VCC + 0.2V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.2V to +2.4V
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.2V to VCC + 0.2V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Device
Ambient
Temperature
Range
VCC
CY62147CV18 Industrial −40°C to +85°C 1.65V to 1.95V
Product Portfolio
Power Dissipation (Industrial)
Operating (ICC)
VCC Range
VCC(min.) VCC(typ.)[4]
Product
CY62147CV18
1.65V
1.80V
f = 1 MHz
VCC(max.)
1.95V
Speed
Typ.[4]
f = fmax
Max.
Typ.[4]
Standby (ISB2)
Max.
Typ.[4]
Max.
1 µA
10 µA
55 ns
0.5 mA
3 mA
2.5 mA
7 mA
70 ns
0.5 mA
3 mA
2 mA
6 mA
Electrical Characteristics Over the Operating Range
CY62147CV18-55
Parameter
Description
Test Conditions
Min.
Typ.[4]
Max.
VOH
Output HIGH Voltage
IOH = -0.1 mA
VCC = 1.65V
VOL
Output LOW Voltage
IOL = 0.1 mA
VCC = 1.65V
1.4
VIH
Input HIGH Voltage
1.4
VCC +
0.2V
VIL
Input LOW Voltage
–0.2
IIX
Input Leakage Current GND < VI < VCC
–1
CY62147CV18-70
Min.
Typ.[4]
Max. Unit
1.4
0.2
V
0.2
V
1.4
VCC +
0.2V
V
0.4
–0.2
0.4
V
+1
–1
+1
µA
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or VSS to ensure proper application.
3. VIL(min) = −2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ) Typ, TA = 25°C.
Document #: 38-05011 Rev. *C
Page 2 of 11
CY62147CV18 MoBL2™
Electrical Characteristics Over the Operating Range (continued)
CY62147CV18-55
Parameter
Description
Test Conditions
Min.
–1
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
Typ.[4]
VCC = 1.95V
IOUT = 0 mA
CMOS levels
ISB1
Automatic CE
CE > VCC − 0.2V, VIN > VCC − 0.2V,
Power-down Current— VIN < 0.2V, f = fMAX (Address and
Data Only), f = 0 (OE, WE, BHE,
CMOS Inputs
and BLE)
ISB2
Automatic CE
CE > VCC − 0.2V VIN > VCC − 0.2V
Power-down Current— or VIN < 0.2V, f = 0, VCC = 1.95V
CMOS Inputs
CY62147CV18-70
Max.
Min.
+1
–1
Typ.[4]
Max. Unit
µA
+1
2.5
7
2
6
mA
0.5
3
0.5
3
mA
1
10
1
10
µA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max.
Unit
6
pF
8
pF
Thermal Resistance
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)[5]
ΘJC
Thermal Resistance
(Junction to Case)[5]
Test Conditions
BGA
Unit
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board
55
°C/W
16
°C/W
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC Typ
OUTPUT
90%
10%
90%
10%
GND
30 pF
INCLUDING
JIG AND
SCOPE
R2
Fall Time:
1 V/ns
Rise Time:
1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
1.8V
Unit
R1
13500
Ohms
R2
10800
Ohms
RTH
6000
Ohms
VTH
0.80
Volts
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Conditions
Min.
Typ.[4]
1.0
VCC = 1.0V, CE > VCC − 0.2V, VIN > VCC − 0.2V
or VIN < 0.2V
1
Max.
Unit
1.95
V
8
µA
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05011 Rev. *C
Page 3 of 11
CY62147CV18 MoBL2™
Data Retention Characteristics (Over the Operating Range) (continued)
Parameter
Description
Conditions
tCDR[5]
Chip Deselect to Data Retention Time
tR[6]
Operation Recovery Time
Data Retention
Min.
Typ.[4]
Max.
Unit
0
ns
tRC
ns
Waveform[7]
DATA RETENTION MODE
VCC(min.)
VCC
VCC(min.)
VDR > 1.0 V
tR
tCDR
CE or
BHE,BHE
Switching Characteristics Over the Operating Range
[8]
55 ns
Parameter
Description
Min.
70 ns
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
55
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
Low-Z[9]
tLZOE
OE LOW to
tHZOE
OE HIGH to High-Z[9, 10]
Low-Z[9]
tLZCE
CE LOW to
tHZCE
CE HIGH to High-Z[9, 10]
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
tDBE
BLE/BHE LOW to Data Valid
tLZBE
BLE/BHE LOW to Low-Z[9]
tHZBE
BLE/BHE HIGH to
70
55
10
70
10
5
5
ns
25
10
20
0
0
55
5
ns
ns
70
ns
70
ns
5
20
ns
ns
25
55
ns
ns
5
20
High-Z[9, 10]
ns
ns
25
ns
Write Cycle[11]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
40
60
ns
tAW
Address Set-up to Write End
40
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
50
ns
tBW
BLE/BHE LOW to Write End
40
60
ns
tSD
Data Set-up to Write End
25
30
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High-Z[9, 10]
tLZWE
WE HIGH to
Low-Z[9]
0
15
5
ns
25
10
ns
ns
Notes:
6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
8. Test conditions assume signal transition time of 3ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05011 Rev. *C
Page 4 of 11
CY62147CV18 MoBL2™
Switching Waveforms
[12, 13]
Read Cycle No. 1 (Address Transition Controlled)
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
[13, 14]
Read Cycle No. 2 (OE Controlled)
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
BHE/BLE
tLZOE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
ICC
50%
50%
ISB
Notes:
12. Device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE, BHE, BLE, transition LOW.
Document #: 38-05011 Rev. *C
Page 5 of 11
CY62147CV18 MoBL2™
Switching Waveforms
Write Cycle No. 1(WE Controlled)
[11, 15, 16]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 17
tHZOE
Write Cycle No. 2 (CE Controlled) [11, 15, 16]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 17
tHZOE
Notes:
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05011 Rev. *C
Page 6 of 11
CY62147CV18 MoBL2™
Switching Waveforms
[16]
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tHD
tSD
DATAI/O
NOTE 17
DATAIN VALID
tLZWE
tHZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[16]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 17
Document #: 38-05011 Rev. *C
tHD
DATAIN VALID
Page 7 of 11
CY62147CV18 MoBL2™
Typical DC and AC Characteristics (Typical values are included for reference only and are not guaranteed or tested.
Typical values are measured at VCC = VCC Typ, TA = 25°C.)
Standby Current vs. Supply Voltage
Operating Current
vs. Supply Voltage
MoBL2
(f = fmax, 55 ns)
3.5
(f = fmax, 70 ns)
3.0
2.4
ISB (µA)
ICC (mA)
2.0
1.6
1.2
MoBL2
2.0
1.5
1.0
0.8
(f = 1 MHz)
0.4
0.5
0
0.0
1.65
1.80
SUPPLY VOLTAGE (V)
1.65
1.95
1.80
1.95
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
40
MoBL2
35
TAA (ns)
30
25
20
15
10
1.65
1.8
1.95
SUPPLY VOLTAGE (V)
Truth Table
CE
WE
OE
BHE
BLE
H
X
X
X
X
High-Z
Deselect/Power-down
Standby (ISB)
X
X
X
H
H
High-Z
Deselect/Power-down
Standby (ISB)
L
H
L
L
L
Data Out (I/OO–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High-Z
Output Disabled
Active (ICC)
L
H
H
H
L
High-Z
Output Disabled
Active (ICC)
L
H
H
L
H
High-Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (I/OO–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/OO–I/O7);
I/O8–I/O15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0 –I/O7 in High-Z
Write
Active (ICC)
Document #: 38-05011 Rev. *C
Inputs/Outputs
Mode
Power
Page 8 of 11
CY62147CV18 MoBL2™
Ordering Information
Speed
(ns)
70
55
Ordering Code
CY62147CV18LL-70BAI
Package
Name
BA48B
Operating
Range
Package Type
48-ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
CY62147CV18LL-70BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62147CV18LL-55BAI
BA48B
48-ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
CY62147CV18LL-55BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Industrial
Package Diagrams
48-Ball (7.00 mm x 8.5 mm x 1.2 mm) Thin BGA BA48B
51-8 510 6-*C
Document #: 38-05011 Rev. *C
Page 9 of 11
CY62147CV18 MoBL2™
Package Diagrams (continued)
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05011 Rev. *C
Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62147CV18 MoBL2™
Document Title: CY62147CV18 MoBL2™ 256K x 16 Static RAM
Document Number: 38-05011
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
106265
5/7/01
*A
108941
08/24/01
MGN
From Preliminary to Final
*B
110573
11/02/01
MGN
Improved ISB Typ. from 1.5 µA to 1 µA.
Improved Typical DC and AC Characteristics graphs.
Improved Switching Characteristics: tOHA, tLZCE.
Added preliminary package diagram of BV48A.
Format standardization
*C
115864
09/04/02
MGN
Removed Preliminary status for BV package
Document #: 38-05011 Rev. *C
HRT/MGN New Data Sheet
Page 11 of 11