Model # AP10NP01LL8E Rad-Hard Solid State SPST N.O. Latching Relay Manufactured in a Certified Class-K Facility Features • 100 V Breakdown Voltage (N.O. contact) • >1,000 VDC Input to Output Isolation • 1 Amp Design • Buffered Input Stage • Neutron Fluence Level >1.8E12 n/cm2 • 2.0 V Compatible Logic Level Input • Optically Coupled • AC version available (higher “on” resistance) • Total Dose Capability >100 Krad (Si) Description The AP10NP01LL8E is a radiation hardened SPST normally open solid-state latching relay in a hermetic package. It is configured as one contact which is open in the “reset state,” and closed in the “set” state. This device is characterized for >100 Krad (Si) total ionizing dose, and neutron fluence level of >1.8E12 n/cm2. The output FETs utilize advanced technology, and the device is actuated by standard inputs (i.e. 3.3 V and higher logic levels). Table 1 – Absolute Maximum Ratings (Tc = +25oC Unless Otherwise Noted) (Exceeding maximum ratings may damage the device.) Symbol Parameters / Test Conditions (Notes Page 3) Value Unit 100 V 1 A VS Output N.O. Switch Voltage (5) IO Output N.O. Switch Current (4) (5) VS Output N.C. Switch Voltage (5) N/A V IO Output N.C. Switch Current (4) (5) N/A A Vset or reset Input Actuation Voltage (Pin 1 & 3) (3) 48 V Vset or reset Input Actuation Current 2.5 mA VR Input Supply Voltage (Pin 6) (7) 40 V IR Input Supply Current (7) 12 mA PDISS Power Dissipation (4) (5) 2.5 W TJ Operating Temperature Range -55 to +125 oC TS Storage Temperature Range -65 to +150 oC TL Lead Temperature 300 oC Rev Date: 6/12/2015 © API Technologies Corp. Proprietary Information Page # 1 | www.apitech.com | micro.apitech.com | +1.888.553.7531 | [email protected] AP10NP01LL8E Table 2 – General Characteristics per Channel @ -55°C < TC < +125°C (Unless Otherwise Specified) Group A Subgroups Test Conditions Symbol Min. Typ. Max. Units -- VR = 12 V, IO = 1 A VIN(TH) - -- 2.5 V Input-to-Output Leakage Current (1) -- VI-O = 1.0KVdc, dwell = 5.0s TC = 25°C II-O -- -- 1.0 mA Output Capacitance (1) -- VIN = 0.1V, f = 1.0MHz, VS = 25V, TC = 25°C COSS -- 110 -- pF Thermal Resistance (1) -- VIN = 3.3V, VDD = 5.0V (1, 4) RTHJC -- -- 20 °C/W MTBF (Per Channel) -- MIL-HDBK-217F, SF@Tc= 25°C 6.0 -- -- MHrs Weight -- -- -- -- 25 grams Units Parameter Input Latch Threshold Voltage (1) (3) W Table 3 – Pre-Irradiation Electrical Characteristics per Channel @ -55°C < TC < +125°C (Unless Otherwise Specified) Parameter Output On-Resistance Output Leakage Current N.O. output Group A Subgroups Test Conditions 1 2 VR = 12 V IO= 1A 1 VS = 100V 2 VS = 80V Symbol RDS(ON) IO VR = 12.0V Input Supply Current IDD 1, 2, 3 Min. Typ. Max. -- -- 0.4 -- -- 0.8 -- -- 25 -- -- 250 -- 10 15 -- -- -- -- 1.0 2, 3 IIN -- -- 1.5 Turn-On Delay (6) 1, 2, 3 VIN = 3.3V, VR = 12V, VS = 50V RL = 5Ω, P.W. = 50ms ton -- -- TBD Turn-Off Delay (6) 1, 2, 3 VIN = 0.1V, VR = 12V, VS = 50V RL = 5Ω, P.W. = 50ms toff -- -- TBD Rise Time (2) (6) 1, 2, 3 VIN = 3.3V, VR = 12V, VS = 50V RL = 5Ω, P.W. = 50ms tr -- -- TBD Fall Time (2) (6) 1, 2, 3 VIN = 0.1V, VDD = 12V, VS = 50V RL = 5Ω, P.W. = 50ms tf -- -- TBD mA mS Rev Date: 6/12/2015 © API Technologies Corp. Proprietary Information uA mA Vin = 10V 1 Input Set/Reset Current Ohms Page # 2 | www.apitech.com | micro.apitech.com | +1.888.553.7531 | [email protected] AP10NP01LL8E Table 4 – Post Total Dose Irradiation (8, 9) Electrical Characteristics per Channel @ 25°C (unless otherwise specified) Group A Subgroups Test Conditions Symbol Output On-Resistance 1 VR = 12 V, IO= 1 A RDS(ON) Input Supply Current 1 VR= 12V IDD Output Leakage Current 1 VR = 0.1V, VS = 100V IO 25 Input Set/Reset Current 1 VIN = 10V IIN 1.2 Turn-On Delay (6) 1 VIN = 3.3V, VDD = 5.0V, VS = 50V RL = 5W, PW = 50ms ton TBD 1 VIN = 0.1V, VDD = 5.0V, VS = 50V RL = 5W, PW = 50ms toff TBD Rise Time (2) (6) 1 VIN = 3.3V, VDD = 5.0V, VS = 50V RL = 5W, P.W. = 50ms tr TBD (2) (6) 1 VIN = 0.1V, VDD = 5.0V, VS = 50V RL = 5W, P.W. = 50ms tf TBD Parameter Turn-Off Delay Fall Time (6) Min. Typ. 10 Max. Units 1 Ohms 15 mA mA ms Notes for Maximum Ratings and Electrical Characteristic Tables 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Specification is guaranteed by design. Rise and fall times are controlled internally. Set and Reset inputs protected for VIN > -10 V to < +48 V. Optically coupled Solid State Relays (in reality a FET with isolated Gate drive) have relatively slow turn on and turn off times. Care must be taken to insure that transient currents during these times do not cause violation of SOA limits for the particular switch used. If transient conditions are present, we recommend that a complete simulation be performed by the end user to insure compliance with SOA requirements as specified in the data sheet of the applicable switching transistor. While the SSR design meets the design requirements specified in MIL-PRF-38534, the end user is responsible for product derating, as required for the application. Reference Figures 3 & 4 for Switching Test Circuits and Waveform; Output Voltage (VO) of Figure 4, Switching Test Waveform, is representative of the Output FET Drain-to-Source Voltage. Input Supply voltage shall not exceed 4 0 V . Total Dose Irradiation takes place with an Input Voltage of 24 V applied and VDS = 80 V. API Technologies’ Marlborough Operations does not currently have a DLA certified Radiation Hardness Assurance Program. “Flag” output is open collector, and is normally “open” when relay is set. Some models have functionality such that this “sense” can be reversed. Radiation Performance API’s Radiation Hardened Solid State Relays are tested to verify their hardness capability. The hardness assurance program uses a Cobalt-60 (60 Co) Source and heavy ion irradiation. Both pre- and post-irradiation performance are tested and specified using the same drive circuitry and test conditions to provide a direct comparison. Rev Date: 6/12/2015 © API Technologies Corp. Proprietary Information Page # 3 | www.apitech.com | micro.apitech.com | +1.888.553.7531 | [email protected] AP10NP01LL8E Table 5 - Ordering Information AP 10 NP Breakdown Voltage 06 = 60 V DC 10 = 100 V DC 25 = 250 V DC A6=60 V AC 1A=100 V AC 2A=200 V AC 01 LL Max Output Current 01 = 1 A 10 = 10 A 12 = 12 A etc Contact Type NC = Normally Closed NP = Normally Open DT = SPDT DN=Dual Normally Open DC=Dual Normally Closed DD=DPDT “T” suffix indicates negative Voltage set/reset style. E 8 Pkg & Lead Bend Options, Flat-Pack style assumed UOS 0 = Plug In style package 1 = No Bend 2 = Surface Mount 3 = Pkg with mounting tabs, no leadbend 4 = Pkg with mounting tabs, SMT leadbend Voltage 5=5V 8 = 28 V Timing AA = First Series NN = No set timing MM = Make/Make MB = Make/Break BM = Break/Make BB = Break/Break LL=Latching (no specific timing) BL=Break-BeforeMake Latching 1 Screening Level K = Class-K Compliant H = Class-H Compliant E = Engineering Model “P” suffix indicates “out of phase” Flag. See note 10. “E” suffix indicates Power-up in the “set” state as opposed to power-up in the more common “reset” state. Table 6 - Screening Options Screening Levels H K Compliant- MIL-PRF-38534 Tests Mil-Std-883Method 100 % Non-Destruct Wire-Pull Sample 100% 2023 Pre-Cap Visual N/A 100% 2017 Temperature Cycle 100% 100% 1010 Constant Acceleration 100% 100% 2001 PIND N/A 100% 2020 Pre-Burn-In Electrical (Ta= 25C) 100% 100% Burn-In 100% (240 Hours) 100% (320 Hours) 1015 Final Electrical 100% 100% (6) Hermeticity (Fine & Gross Leak) 100% 100% 1014 X-Ray (5) N/A 100% 2012 External Visual 100% 100% 2009 Rev Date: 6/12/2015 © API Technologies Corp. Proprietary Information Page # 4 | www.apitech.com | micro.apitech.com | +1.888.553.7531 | [email protected] AP10NP01LL8E Figure 1 – Maximum Drain Current vs. Case Temperature per Channel Figure 2 – Functional Block Diagram + - Rev Date: 6/12/2015 © API Technologies Corp. Proprietary Information Page # 5 | www.apitech.com | micro.apitech.com | +1.888.553.7531 | [email protected] AP10NP01LL8E Figure 3 – Switching Test Circuit Figure 4 – Switching Test Waveform Rev Date: 6/12/2015 © API Technologies Corp. Proprietary Information Page # 6 | www.apitech.com | micro.apitech.com | +1.888.553.7531 | [email protected] AP10NP01LL8E Figure 5 –Plug-in Package, Dimensions, bottom view 1 7 14 8 Figure 6 – Flat-Pak Package Dimensions, top view Rev Date: 6/12/2015 © API Technologies Corp. Proprietary Information Page # 7 | www.apitech.com | micro.apitech.com | +1.888.553.7531 | [email protected] AP10NP01LL8E Table 7 – Pin Designations Pin # Pin Description, Either package style 1 RESET 2 SET 3 FLAG 4 VR 5 VR 6 N.O. Switch (+) 7 N.O. Switch (+) 8 N.O. Switch (-) 9 N.O. Switch (-) 10 Not Connected 11 Not Connected 12 Not Connected 13 Power Return 14 Power Return 1.- Dimensioning and Telebanking per ASME Y14.53M-1994 2.- Controlling Dimension: Inch 3.- Dimensions are shown in inches 4.- Tolerances are +/-0.005 UOS 5.- Lead Dimensions are prior to Hot Solder Dip (if used) 6.- Lead finish per MIL-PRF-38534, Finish A, hot solder dip (Sn 63/Pb37) only on SMT lead bend option. 7.- For no leadbend, leads exit package as above and extend out 0.5” minimum. Rev Date: 6/12/2015 © API Technologies Corp. Proprietary Information Page # 8 | www.apitech.com | micro.apitech.com | +1.888.553.7531 | [email protected]