AOZ1254 4A EZBuck™ Synchronous Buck Regulator Not Recommended For New Designs General Description Features The AOZ1254 is a high efficiency, low quiescent current and simple to use 4A synchronous buck regulator. This device operates from 4.5V to 26V input voltage range and provides up to 4A of continuous output current with an adjustable output voltage down to 0.6V. The AOZ1254 is offered in the Exposed Pad SO-8 package which is rated over a -40°C to +85°C ambient temperature range. ns ig es D ew Applications High performance point-of-load DC/DC converters Notebook/ultra mobile PCs/servers PCIe graphics cards/set top boxes Set top boxes DVD drives and HDD LCD-TV/displays R ec om m en de d Fo r Replacement Part: AOZ3046PI N 4.5V to 26V input voltage operation range High efficiency PFM mode light load performance Synchronous rectification: 110mΩ integrated high-side switch and 30mΩ internal low-side switch Integrated bootstrap diode External soft start control Adjustable output voltage down to 0.6V 4A continuous output current Fixed frequency of PWM 620kHz operation Tailored for small profile inductor and ceramic capacitors Cycle-by-cycle current limit Short-circuit protection Thermal shutdown Standard exposed pad SO-8 package -40°C to 150°C operating junction temperature range N ot Typical Application Rev. 1.0 January 2012 www.aosmd.com Page 1 of 1 AOZ1254 Ordering Information Part Number Temperature Range Package Environmental AOZ1254PI -40°C to +85°C EPAD SO-8 Green AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. VIN 2 7 FB 6 AGND 3 SS 4 5 Fo r EPAD SO-8 (Top View) COMP N BST Exposed Pad LX ig VDD es 8 D 1 ew PGND ns Pin Configuration PGND VIN Pin Function de Pin Name 1 2 Power Ground connection. Input Voltage Supply Pin. When VIN rises above the UVLO threshold the device starts up. en Part Number d Pin Description 4 5 6 7 SS COMP AGND FB om m BST VDD LX N ot 8 Exposed Pad R ec 3 Note: Connect close decoupling capacitor from VIN to PGND to minimize input switching loop. Bootstrap Connection for High-side NFET Gate Drive Input. Connect 10nF capacitor from BST to LX. Soft Start Input. Connect a capacitor between SS to GND for soft start time control. External Loop Compensation Input. Signal Ground Input. The Feedback Voltage Input. It is used to determine the output voltage via a resistor divider between the output and AGND. Internal LDO Voltage Output. Connect a 1µF capacitor close to VDD to AGND. Output Connection to Inductor. Thermal connection for output stage. Rev. 1.0 January 2012 www.aosmd.com Page 2 of 2 AOZ1254 N ot R ec om m en de d Fo r N ew D es ig ns Functional Block Rev. 1.0 January 2012 www.aosmd.com Page 3 of 3 AOZ1254 Absolute Maximum Ratings Recommended Operating Ratings Exceeding the Absolute Maximum Ratings may damage the device. This device is not guaranteed to operate beyond the Recommended Operating Ratings. Parameter Supply Voltage (VIN) LX to GND SS to GND BST to LX FB to GND COMP to GND Junction Temperature (TJ) Storage Temperature (TS) ESD Rating(1) Parameter Supply Voltage (VIN) Output Voltage (VOUT) Ambient Temperature (TA) Package Thermal Resistance EPAD SO-8 (JA) Rating 4.5V to 26V 0.6V to 22V -40°C to +85°C 50°C/W es ig ns Rating 30V -0.7V to VIN+0.3V -0.3V to +6V -0.3V to +6V -0.3V to +6V -0.3V to +6V +150°C -65°C to +150°C 2kV D Note: ew 1. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5kΩ in series with 100pF. N Electrical Characteristics Symbol Parameter Conditions VFB_LOAD VFB_LINE IFB VSS_OFF ISS Modulator ot R Frequency Maximum Duty Cycle Minimum On Time System Loop Transconductance Error Amplifier Transconductance 0.8A < IOUT < 3.2A 6V < VVIN < 26V, Load = 1A VFB = 0.6V Off threshold VSS = 2.0V Min. Typ. 4.5 Max Units 26 4.1 V 3.3 0.9 591 5.2 600 0.5 0.05 -30 2.5 500 620 87 80 5 1 5 5.5 155 115 IOUT/VCOMP N Fs DMAX TON_MIN GMSYS GMEA de Supply Current (Quiescent) Shutdown Supply Current LDO Voltage Feedback Voltage Load Regulation Line Regulation Feedback Input Current Enable Threshold SS Source Current VVIN rising VVIN falling IOUT = 0, VFB = 0.8V VSS = 0V VVIN > 6V en IVIN IOFF VVDD VFB om m VUVLO d Supply Voltage Input Under-Voltage Lockout Threshold ec VVIN Fo r TA = 25°C, VVIN = 12V, VSS = 2.5V, VOUT = 3.3V unless otherwise specified. Specifications in BOLD indicate an ambient temperature range of -40°C to +85°C. 1.5 20 609 100 0.4 30 740 V mA µA V mV % %/V nA V µA kHz % ns A/V mA/V Protection ILIM TOTP_RISE TOTP_FALL Current Limit Over-Temperature Shutdown Limit Temperature rising Temperature falling A °C °C Outputs RDSON_HS RDSON_LS High-Side Switch ON Resistance Low-Side Switch ON Resistance Rev. 1.0 January 2012 110 30 www.aosmd.com 170 55 mΩ mΩ Page 4 of 4 AOZ1254 Typical Performance Characteristics N ot R ec om m en de d Fo r N ew D es ig ns TA = 25°C, VIN = 12V, VOUT = 1.1V unless otherwise specified. Rev. 1.0 January 2012 www.aosmd.com Page 5 of 5 AOZ1254 D es ig ns Light Load and PWM Operation Under low output current settings, AOZ1254 will operate in light load mode to obtain high efficiency. The two modes of operation, PFM and PWM are determined by the peak inductor current level and the output feedback voltage. For very low output current and consequently low peak inductor current, AOZ1254 will operate under critical inductor current mode if FB voltage is lower than threshold of VH_PFM. VH_PFM is 10mV higher than normal voltage reference. If output is higher than that value, IC will turn-off to keep high light load efficiency. As the output current increases, the IC will leave PFM mode and will enter PWM mode operating in fixed frequency continuous conduction mode (CCM). In CCM mode, AOZ1254 operates with the low side MOSFET switching in synchronous rectification to obtain high efficiency performance. de CSS ISS N ot TSS 0.6 R ec om m en Soft Start AOZ1254 starts a soft start that can be adjusted by an external capacitor. The internal 2.5µA current source starts to charge the external capacitor through the softstart pin. When soft-start voltage is higher than internal enable threshold voltage, the IC starts to switch with minimum on-time. With the soft-start voltage further increasing, the IC starts to switch with wider on-time, which drives the output (FB) following the soft-start voltage until output reaches the pre-set value. The output soft-start time can be calculated by: Rev. 1.0 January 2012 N Error Amplifier AOZ1254 uses an error amplifier that has a transconductance of 1000µA/V. Closed loop stability is realized through the frequency compensation network connected between COMP to AGND. (Refer to Loop Compensation) Fo r d The AOZ1254 is a high efficiency current-mode buck regulator with integrated both high-side and low-side NMOS switches. It has a wide operating input voltage range of 4.5V to 26V and can supply up to 4A of output load current. AOZ1254’s key protection features include input under voltage lockout, output over voltage protection, cycle by cycle current limit, fault short protection and thermal shut down. The AOZ1254 is available in the exposed pad SO-8 package. ew Detailed Description Slope Compensation A slope compensation ramp is also added in the control loop design to prevent sub harmonic oscillations. There is sufficient inductor current information to obtain stabile current mode operation. The output voltage is divided by the resistive voltage divider at the FB pin. The internal transconductance error amplifier then amplifies the difference between the voltages at FB with the reference voltage. The error signal voltage is an input to the COMP and is compared against the current signal which consists of both the inductor current and slope comp ramp at the PWM comparator input. If this current signal is less than the error voltage the high side switch will turn on. Switching Frequency The AOZ1254 has a fixed switching frequency under PWM mode of operation through an internal oscillator. Its nominal switching frequency is set to 600kHz. www.aosmd.com Page 6 of 6 AOZ1254 Output Voltage Setting The output voltage is set by a resistor divider network of R1 and R2, by feeding back the output to the FB pin. The output setting is defined by: Thermal Protection An internal temperature sensor monitors the junction temperature of the controller. The internal control circuit shuts down the high-side NMOS once the junction temperature exceeds 150ºC. The regulator has a 50° hysteresis and will automatically restart when the junction temperature decreases to 100ºC. R VO 0.6 1 1 R2 Below Table 1 lists popular regulated outputs and the corresponding values of R1, R2. ns ig es 6.67 15 20 31.7 45 73.3 R2 (kΩ) Open 10 10 10 10 10 10 D R1 (kΩ) The input ripple voltage can be approximated by equation below: Table 1.Output Voltage Setting with Resistor Divider IO V 1 O f CIN VIN N VIN ew VO (V) 0.6 1.0 1.5 1.8 2.5 3.3 5.0 Input capacitor The input bypass capacitor must be connected very closely to the VIN and PGND pins of AOZ1254. This mainly to ensure that proper filtering is maintained to filter out the pulsing input current inherent to buck regulator switching. The voltage rating of input capacitor is selected to be higher than maximum input voltage plus the input ripple voltage. en de ICIN _ RMS IO VO VIN VO 1 VIN m equals the conversion ratio: VO m VIN The relationship between the input capacitor RMS current and voltage conversion ratio is calculated and shown in Figure 1 below. It can be seen that when VO is half of VIN, CIN is under the worst current stress. The worst current stress on CIN is 0.5·IO. ot R ec om m Over Current Protection (OCP) The primary signal used in over current protection is the peak inductor. By employing peak current mode control, the COMP voltage is proportional to the peak inductor current. This voltage falls between the range of 0.4V and 2.5V, increasing with output load current. AOZ1254 utilizes cycle by cycle current limit and limits the peak inductor current. A preset current limit voltage is used as a reference trip point. When the output current exceeds the current limit range, the high side switch will stop switching. Since the input current is discontinuous in a buck converter, the current stress on the input capacitor is one key concern when selecting the capacitor. For a buck regulator, the RMS value of input capacitor current can be calculated by: Fo r d The combination of R1 and R2 should be large enough to avoid drawing excessive current from the output that contributes to power loss. Since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop of the high side NMOS and inductor . VO V IN N Under fault conditions where the output maybe shorted to ground, VOUT will drop rapidly and AOZ1254’s protection circuit will force the inductor current to decay once the OCP level is reached within several switching cycles. This feature helps to prevent catastrophic failure and recovery of the IC once the short is removed. AOZ1254 will initiate a soft start once the over-current condition is removed. Figure 1. ICIN vs. Voltage Conversion Ratio Rev. 1.0 January 2012 www.aosmd.com Page 7 of 7 AOZ1254 To ensure reliable operation, the input capacitors must be selected to have a current rating higher than ICIN-RMS at the worst operating conditions. Ceramic capacitors are preferred for input capacitors because of their low ESR and high current rating. Depending on the application circuits, other low ESR tantalum capacitor may also be used. When selecting ceramic capacitors, X5R or X7R type dielectric ceramic capacitors should be used for their better temperature and voltage characteristics. Note that the ripple current rating from capacitor manufactures is based on certain amount of life time. Further de-rating may be necessary in practical design. ig ns Output Capacitor The output capacitor is selected based on the DC output voltage rating, output ripple voltage specification and ripple current rating. The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. Derating needs to be considered for long term reliability. Output ripple voltage specification is another important factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It can be calculated by the equation below: The peak inductor current is: ESRCO is the Equivalent Series Resistor of output capacitor. d IL 2 de ILpeak IO ew CO is output capacitor value and N VO V 1 O f L VIN where, om m en High inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. Low ripple current reduces inductor core losses. It also reduces RMS current through inductor and switches, which results in less conduction loss. Usually, peak to peak ripple current on inductor is designed to be 20% to 30% of output current. ec When selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. ot R The inductor takes the highest current in a buck circuit. The conduction loss on inductor needs to be checked for thermal and efficiency requirements. Surface mount inductors in different shape and styles are available from Coilcraft, Elytone and Murata. Shielded inductors are small and radiate less EMI noise. But they cost more than unshielded inductors. The choice depends on EMI requirement, price and size. N When low ESR ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simplified to: Fo r IL D es 1 VO IL ESRCO 8 f CO Inductor The inductor is used to supply constant current to output when it is driven by a switching voltage. For given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: VO IL 1 8 f CO If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to: VO IL ESRCO For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum are recommended to be used as output capacitors. In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calculated by: ICO _ RMS I L 12 Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. Rev. 1.0 January 2012 www.aosmd.com Page 8 of 8 AOZ1254 To design the compensation circuit, a target crossover frequency fC for close loop must be selected. The system crossover frequency is where control loop has unity gain. The crossover is the also called the converter bandwidth. Generally a higher bandwidth means faster response to load transient. However, the bandwidth should not be too high because of system stability concern. When designing the compensation loop, converter stability under all line and load condition must be considered. Loop Compensation The AOZ1254 employs peak current mode control for ease-of-use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It greatly simplifies the compensation loop design. ns With peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. The pole is dominant pole can be calculated by: Usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. It is recommended to choose a crossover frequency equal or less than 60kHz. ig 1 fp1 2 CO RL D The strategy for choosing RC and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC, to calculate RC: 1 2 CO ESRCO RC fC where, where, ESRCO is the equivalent series resistance of output capacitor. om m en de d The compensation design is actually to shape the converter control loop transfer function to get desired gain and phase. Several different types of compensation network can be used for the AOZ1254. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. Fo r RL is load resistor value; and VFB is 0.6V; GEA is the error amplifier transconductance, which is 1000·10-6 A/V; and GCS is the current sense circuit transconductance, which is 4 A/V. The compensation capacitor CC and resistor RC together make a zero. This zero is put somewhere close to the dominate pole fp1 but lower than 1/5 of selected crossover frequency. CC can is selected by: 1.5 2 RC Fp1 Equation above can also be simplified to: ot where, fC is desired crossover frequency. For best performance, fC is set to be about 1/10 of switching frequency; CC R GEA 2 CC GVEA ec In the AOZ1254, FB pin and COMP pin are the inverting input and the output of internal error amplifier. A series R and C compensation network connected to COMP provides one pole and one zero. The pole is: fp 2 VO 2 CO VFB GEA GCS N CO is the output filter capacitor; ew fZ 1 es The zero is an ESR zero due to output capacitor and it’s ESR. It is can be calculated by: CC N GEA is the error amplifier transconductance, which is 1000·10-6 A/V; CO RL RC GVEA is the error amplifier voltage gain, which is 500 V/V; and CC is compensation capacitor in the Typical Application schematic on the first page. The zero given by the external compensation network, capacitor CC and resistor RC is located at: fZ 2 1 2 CC RC Rev. 1.0 January 2012 www.aosmd.com Page 9 of 9 AOZ1254 PCB guideline that can be helpful: 1. The exposed (LX) node serves as the interconnect of both high-side and low-side MOSFETs. It is suggested that a large copper plane added underneath the IC to improve thermal dissipation. PCB Layout Consideration As with all high current switching buck regulators, circuit board layout is the key in preventing inductive overshoots and undershoots transient spikes. There are essentially two high pulsing current loops in a synchronous buck converter. The first switching loop is formed when the high-side MOSFET is switched on. The circulating current flows from the input capacitors, to the filter inductor, to the output capacitors (load), then returns to the input capacitor through power ground. It is imperative that a low inductive ceramic capacitor be placed directly across VIN (PIN2) and PGND (PIN1) to reduce the switching loop during the high side turn on transition. ns 3. The input capacitor should be connected in close proximity to the VIN pin and the PGND pins. ig 4. A ground plane is strongly recommended. Separate PGND from AGND and connect them at a single point to avoid noise coupling. D es 5. Form a short wide trace from LX to the output inductor and capacitors. Fo r N ew 6. The LX switching node is the noisiest of all pins; therefore, all sensitive nodes must be far away from this pin. N ot R ec om m en de d The second loop is formed when the low-side MOSFET is switched on during synchronous operation. This loop is formed from the inductor, to the output capacitors (load), then returns through the low-side MOSFET. The PCB layout for the AOZ1254 is shown below. It can be seen that the input bypassing capacitors are placed in close proximity to VIN and PGND. Analog ground and power grounds are separated to filter out noise from the main power switching loops. The sensitive nodes that require connection through analog ground (AGND) are COMP, FB, and VSS. 2. To improve high-side thermal dissipation, maximize the copper area connected to the VIN pin. Rev. 1.0 January 2012 www.aosmd.com Page 10 of 10 AOZ1254 N ot R ec om m en de d Fo r N ew D es ig ns Package Dimensions, Exposed Pad SO-8 Rev. 1.0 January 2012 www.aosmd.com Page 11 of 11 AOZ1254 N ot R ec om m en de d Fo r N ew D es ig ns Tape and Reel Dimensions, Exposed Pad SO-8 Rev. 1.0 January 2012 www.aosmd.com Page 12 of 12 AOZ1254 Part Marking AOZ1254PI (EPAD SO-8) ns Z1254PI Part Number Code D es ig FA YW LT ew Assembly Lot Code Fab & Assembly Location om m en de d Fo r N Year & Week Code ec This datasheet contains preliminary data; supplementary data may be published at a later date. Alpha and Omega Semiconductor reserves the right to make changes at any time without notice. R LIFE SUPPORT POLICY N ot ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.0 January 2012 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 13 of 13