APW7533

APW7533
HV Asynchronous Step-Down Converter with Bypass
General Description
Features
•
•
•
•
•
•
•
•
•
•
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•
Wide Input Voltage from 4.5V to 26V
Output Current up to 4A
The APW7533 is a 4A, asynchronous, step-down converter with integrated 22mΩ P-channel MOSFET. The
Adjustable Output Voltage from 0.8V to 100% VIN
- 0.8V Reference Voltage
device, with current-mode control scheme, can convert
4.5~26V input voltage to the output voltage adjustable
- ±2.5% System Accuracy
22mΩ Integrated P-Channel Power MOSFET
from 0.8 to 100% VIN to provide excellent output voltage
regulation.
High Efficiency up to 91%
- Pulse-Skipping Mode (PSM) / PWM Mode Op-
The APW7533 regulates the output voltage in automatic
PSM/PWM mode operation, depending on the output
eration
Current-Mode Operation
current, for high efficiency operation over light to full load
current. The APW7533 is also equipped with power-on-
- Stable with Ceramic Output Capacitors
- Fast Transient Response
reset, soft-start, and whole protections (under-voltage,
over-temperature, and current-limit) into a single package.
Power-On-Reset Monitoring
Fixed 380kHz Switching Frequency in PWM Mode
In shutdown mode, the supply current drops below 5µA.
This device, available in a TDFN-5x5-16 package, pro-
Built-in Digital Soft-Start
Output Current-Limit Protection with Frequency
vides a very compact system solution with minimal external components and good thermal conductance.
Foldback
70% Under-Voltage Protection
100
Over-Temperature Protection
<5µA Quiescent Current During Shutdown
90
Thermal-Enhanced TDFN-5x5-16 Package
Lead Free and Green Devices Available
70
80
Efficiency (%)
•
•
•
(RoHS Compliant)
Applications
•
•
•
•
•
•
•
VOUT =5V
VOUT =3.3V
60
50
40
30
20
LCD Monitor / TV
10
Set-Top Box
Portable DVD
0.001
0.01
0.1
1
10
Output Current, IOUT (A)
Wireless LAN
ADSL, Switch HUB
Notebook Computer
Step-Down Converters Requiring High Efficiency
and 4A Output Current
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
1
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APW7533
Ordering and Marking Information
Package Code
QB : TDFN-5x5-16
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7533
Assembly Material
Handling Code
Temperature Range
Package Code
APW7533 QB :
APW7533
XXXXX
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
NC
1
16 NC
VIN
2
15 LX
VIN
3
14 LX
VIN
4
17
13 LX
VIN
5
LX
12 GND
EN
6
11 FB
UGNG
7
10 COMP
VCC
8
9
LX
TDFN 5x5 - 16
Top View
Simplified Application Circuit
2.2µH
VIN
VIN
VOUT
LX
LX
22µF
22µF
LX
22pF
GND
100k
EN
UGNG
1µF
1µF
63k
FB
COMP
220µF
VCC
220µF
12k
10k
22pF
APW7533
1.5nF
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
2
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APW7533
Absolute Maximum Ratings
Symbol
VIN
VL X
V CC
(Note 1)
P aramet er
VIN Suppl y Vo ltag e (VIN to GND)
LX to GND V oltage
VCC Supp ly Vo lta ge (VCC to GND)
Rating
Unit
-0.3 ~ 3 0
V
> 100n s
-2 ~ VIN+0.3
< 100n s
-5 ~ VIN+6
VIN > 6 .2V
-0.3 ~ 6.5
VIN ≤ 6 .2V
< V IN +0.3
V
V
VUGND _GND
UGND to GND Voltage
-0.3 ~ VIN+0.3
V
V VIN _UGND
VIN to UGND Voltage
-0.3 ~ 7V
V
-0.3 ~ 2 0
V
EN to G ND Vo ltag e
FB, CO MP to GND Voltage
-0 .3 ~ V CC +0 .3
Maximum Ju nctio n Temp erature
T STG
Stora ge Tempera tu re
T SD R
Maximum Lead Solder ing Te mperature , 10 Se co nds
V
15 0
o
-65 ~ 1 50
o
26 0
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
P arame ter
S ymbol
θ JA
Junction-to-Ambient Re sistance in Free A ir
θ JC
Junction-to-Case Resistan ce in Free Air
Typical Value
Unit
(N ote 2)
TDFN-5x5-16
28.8
o
4.4
o
C/W
(Note 3)
TDFN-5x5-16
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TDFN-5x5-16 is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TDFN-5x5-16 package.
Recommended Operating Conditions (Note 4)
S ymbol
V IN
Range
Unit
VIN S upply Voltage
Parame ter
4.5 ~ 26
V
VCC Supp ly Voltage
4 .0 ~ 5 .5
V
VOUT
Converter Ou tp ut Voltage
IOUT
Converter Ou tp ut Curre nt
0~4
VCC Inp ut Capa citor
0.22 ~ 2.2
µF
VIN-to-UGND Inpu t Capacitor
0.22 ~ 2.2
µF
TA
TJ
0.8 ~ 90% V IN
Ambi ent Temper atu re
Junction Tem perature
(Note5 )
V
A
-4 0 ~ 85
o
-40 ~ 1 25
o
C
C
Note 4: Refer to the typical application circuits.
Note 5: If operated in bypass mode, maximum output current is 2.5A
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
3
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APW7533
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless
otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
S ymbol
Parameter
APW75 33
Test Conditions
Unit
Min.
Typ.
Ma x.
SUP PLY CURRENT
I VIN
I VIN_SD
I VCC
I VCC_SD
VIN S upply Curren t
VFB = 0.85V, VEN=3V, LX=Open
-
1.0
2.0
mA
VIN S hutdown Sup ply Curr ent
VEN = 0V, VIN=26V
-
-
5
µA
VCC Supp ly Curre nt
VEN = 3V, V CC = 5.0V, VFB=0.85V
-
0.7
-
mA
VCC Shutdown Su pply Cu rrent
VEN = 0V, V CC = 5.0V
-
-
1
µA
4.5
V
VCC 4.2V LINEAR REGULATOR
Ou tp ut Voltage
VIN = 5.2 ~ 26V, I O = 0 ~ 8mA
4.0
4.2
Loa d Re gula tio n
I O = 0 ~ 8mA
- 60
-40
0
mV
Curren t- Limit
VC C > POR Thr eshold
8
-
30
mA
VIN-TO -UGND 5 .5 V LINEAR REG ULATOR
Ou tp ut Voltage (VVIN-UGND )
VIN = 6.2 ~ 26V, I O = 0 ~ 10mA
5.3
5.5
5.7
V
Loa d Re gula tio n
I O = 0 ~ 10mA
- 80
-60
0
mV
Curren t- Limit
VIN = 6.2 ~ 26V
10
-
30
mA
3.7
3.9
4.1
V
-
0 .1 5
-
V
2.3
2.5
2.7
V
-
0.2
-
V
-
3.5
-
V
-
0.2
-
V
-
0.8
-
V
-1.0
-
+1.0
-2.5
-
+2.5
POWER-ON-RESET (P OR) AND LOCKOUT VOLTAGE THRESHOLDS
VCC POR Vo lta ge Thr eshold
VCC rising
VCC POR Hysteresis
EN Lockout Vol tag e Thre sh old
VEN rising
EN Lockout Hyste resis
VIN-to-UGND L ocko ut Voltage
Thresho ld
VVIN-UGND rising
VIN-to-UGND L ocko ut Hysteresis
REFERENCE VO LTAG E
V REF
Referen ce Voltage
o
TJ = 25 C, I OU T=0A, V IN =12 V
Ou tp ut Voltage Accur acy
%
o
TJ = -4 0 ~ 125 C, IOUT = 0 ~ 4A,
VIN = 4.5 ~ 26V
Lin e Re gulation
VIN = 4.5V to 26 V, I OUT = 0A
-
0 .3 6
-
%
Loa d Re gula tio n
IOUT = 0 ~ 4A
-
0.4
-
%
3 40
380
420
kHz
-
80
-
kHz
-
-
100
%
OSCILLATOR AND DUTY
F OSC
Free Runn ing Frequ ency
VIN = 4.5 ~ 26V
Foldb ack Frequ ency
VFB = 0V
Maximum Co nverter’s Du ty Cycle
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
4
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APW7533
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless
otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
S ymbol
Parameter
APW75 33
Test Conditions
Unit
Min.
Typ.
Ma x.
CURRE NT- MODE PWM CONVERTER
Gm
Err or Ampl ifie r Transcondu ctance
Err or Ampl ifie r DC Gain
CO MP = Ope n
Curren t- Sense Resistan ce
P-cha nnel P owe r MO SFET
Resistan ce
Between VIN a nd Exposed Pad,
o
TJ=25 C
-
400
-
µA/V
60
80
-
dB
-
0 .1 2
-
Ω
-
22
-
mΩ
PRO TE CTIONS
I LIM
P-cha nnel P owe r MO SFET
Curren t- limit
Peak Curren t
5.0
6.5
8.0
A
V UV
FB Under-Vo ltag e Thre shold
VFB fallin g
66
70
74
%
FB Under-Vo ltag e Hyste resis
-
40
-
mV
FB Under-Vo ltag e De boun ce
-
2
-
µs
-
o
C
o
C
T OTP
Over-Temp erature Trip Point
-
Over-Temp erature Hystere sis
150
-
50
-
Soft-Star t In te rva l
9
1 0.8
12
ms
Pre ce ding Dela y before Soft-Sta rt
9
1 0.8
12
ms
-
-
0.8
V
SOFT-START, ENABLE, AND INPUT CURRENTS
t SS
EN Logi c Low Volta ge
VEN fa lling, VIN = 4 ~ 26V
SOFT-START, ENABLE, AND INPUT CURRENTS (CONT.)
EN Logi c High Voltage
VEN rising, VIN = 4 ~ 26V
2.1
-
-
V
EN Pin Clampe d Vol tag e
IEN=10mA
12
-
17
V
P-cha nnel P owe r MO SFET
Lea kage Curren t
VEN = 0V, VLX = 0V, VIN = 26V
-
-
4
µA
I FB
FB Pin Input Cu rrent
VFB = 0.8V
-100
-
+100
nA
I EN
EN Pin Input Cu rrent
VEN < 3V
-500
-
+500
nA
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
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APW7533
Typical Operating Characteristics
Switching Frequency vs. Junction Temperature
420
0.812
410
Switching Frequency, FOSC (kHz)
Reference Voltage, VREF (V)
Reference Voltage vs. Junction Temperature
0.816
0.808
0.804
0.800
0.796
0.792
0.788
0.784
-50
-25
0
25
50
75
400
390
380
370
360
350
340
-50 -25
100 125 150
Junction Temperature, TJ (oC)
Output Voltage vs. Output Current
3.36
3.35
IOUT=1A
Output Voltage, VOUT (V)
Output Voltage, VOUT (V)
Output Voltage vs. Supply Voltage
3.36
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
3.24
VIN=12V
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
3.24
4
6
0.0
8 10 12 14 16 18 20 22 24 26
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Output Current, IOUT (A)
VIN Input Current vs. Supply Voltage
Current-Limit Level (Peak Current)
vs. Junction Temperature
8.0
VFB=0.85V
Current-Limit Level, ILIM (A)
1.4
0.5
Supply Voltage, VIN (V)
1.6
VIN Input Current, IVIN (mA)
0
25 50 75 100 125 150
Junction Temperature, TJ (oC)
1.2
1.0
0.8
0.6
0.4
0.2
7.5
7.0
6.5
6.0
5.5
5.0
0.0
0
4
8
12
16
20
24
VIN Supply Voltage, VIN (V)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
28
-50
6
-25
0
25 50 75 100 125 150
Junction Temperature, TJ (oC)
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APW7533
Typical Operating Characteristics (Cont.)
Efficiency vs. Output Current
EN Clamp Voltage vs. EN Input Current
100
18
16
90
70
EN Clamp Voltage, VEN (V)
Efficiency (%)
80
VOUT=5V
VOUT=3.3V
60
50
40
30
VIN=12v, L=10µH (DCR=50mΩ)
C1=10µF, C4=22µF
20
10
0.001
14
12
TJ = -30 oC
10
TJ = 25oC
8
TJ = 100oC
6
4
2
0
0.01
0.1
1
Output Current, IOUT (A)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
10
1
7
10
100
1000
EN Input Current, IEN (µA)
10000
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APW7533
Operating Waveforms
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10µH)
Load Transient Response
Load Transient Response
I OUT = 50mA -> 3A -> 50mA
I OUT rise/f all time=10µs
I OUT = 0.5A -> 3A -> 0.5A
I OUT rise/f all time=10µs
VOUT
1
VOUT
1
3A
3A
IL1
IL1
2
2
0A
Ch1: VOUT, 200mV/Div, DC,
Voltage Offset = 3.3V
Ch2: IL1, 1A/Div, DC
Time: 50µs/Div
0.5A
Ch1: VOUT, 100mV/Div, DC,
Voltage Offset = 3.3V
Ch2: IL1, 1A/Div, DC
Time: 50µs/Div
Power On
Power Off
I OUT = 3A
1
I OUT = 3A
VIN
VIN
1
VOUT
VOUT
2
2
3
IL1
3
Ch1: VIN, 5V/Div, DC
Ch2: VOUT, 2V/Div, DC
Ch3: IL1, 2A/Div, DC
Time: 5ms/Div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
IL1
Ch1: VIN, 5V/Div, DC
Ch2: VOUT, 2V/Div, DC
Ch3: IL1, 2A/Div, DC
Time: 5ms/Div
8
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APW7533
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10µH)
Enable Through EN Pin
Shutdown Through EN Pin
I OUT = 3A
I OUT = 3A
1
1
VEN
VOUT
VOUT
2
2
3
VEN
IL1
3
Ch1: VEN, 5V/Div, DC
Ch2: VOUT, 2V/Div, DC
Ch3: IL1, 2A/Div, DC
Time: 5ms/Div
IL1
Ch1: VEN, 5V/Div, DC
Ch2: VOUT, 2V/Div, DC
Ch3: IL1, 2A/Div, DC
Time: 5ms/Div
Over Current
Short Circuit
I OUT = 1 -> 6A
VOUT is shorted to ground by a short wire
VOUT
1
VOUT
1
I L1
IL1
2
2
Ch1: VOUT, 1V/Div, DC
Ch2: IL1, 2A/Div, DC
Time: 50µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
Ch1: VOUT, 1V/Div, DC
Ch2: IL1, 2A/Div, DC
Time: 50ms/Div
9
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APW7533
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10µH)
Switching Waveform
Switching Waveform
I OUT = 0.2A
3A
I OUT = 3A
VLX
VLX
1
1
IL1
IL1
2
2
Ch1: VLX, 5V/Div, DC
Ch2: IL1, 1A/Div, DC
Time: 1.25µs/Div
Ch1: VLX, 5V/Div, DC
Ch2: IL1, 2A/Div, DC
Time: 1.25µs/Div
Line Transient Response
VOUT
VIN = 12V --> 24V --> 24V
VIN rise/f all time=20µ s
1
VIN
24V
12V
2
Ch1: VOUT, 50mV/Div, DC,
Voltage Offset = 3.3V
Ch2: VIN, 5V/Div, DC,
Voltage Offset = 12V
Time: 50µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
10
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APW7533
Pin Description
PIN
FUNCTION
NO.
NAME
1,16
NC
2,3,4,5
VIN
6
EN
7
UGND
8
VCC
9,13,14,15
LX
10
COMP
11
FB
12
GND
17
(Expose d Pad)
LX
No Used.
P ower Inp ut. VIN supp lies the power (4.5V to 26V ) to the control circuitry, gate driver and
step-d own con ve rte r switch. Con necting a ceram ic bypass capacitor and a sui tab ly large
capa citor between VIN a nd GND elimin ate s switching no ise an d voltage rip ple on the inp ut to
the IC.
E nabl e In put. EN is a digital inp ut that turns th e regu lator on or off. Drive EN high to turn on the
re gulator, d rive i t low to turn it o ff. Pul l u p with 100kΩ resistor fo r a uto matic star t-u p.
G ate driver power g roun d of the P -chann el Power MOS FET. A linea r r egula to r regul ate s a 5 .5V
voltage b etwe en VIN and UGND to sup ply p ower to P-chan nel MOSFE T gate dr ive r. Co nnect a
cera mic capacitor ( 1µF typ.) be twee n V IN and UGND for n oise d eco uplin g a nd stability o f the
li near reg ulator.
B ias input and 4 .2 V linea r regul ato r’s output. This pin su pplies the bias to some co ntrol circuits.
The 4.2V lin ear regu lator co nve rts the voltage on VIN to 4.2 V to supply th e b ias when no
e xterna l 5V power sup ply is conn ecte d with VCC. Co nnect a cera mic capa citor (1 µF typ.)
b etwee n VCC an d GND for noise de co uplin g and stab ility of the lin ear regu lator.
P ower Switch ing Outpu t. Co nnect this p in to the und erside Exposed Pad.
O utput of error amplifier. Con nect a se ries RC n etwo rk from COMP to GND to compe nsate th e
re gulatio n control l oop. In some cases, an addition al capacitor from CO MP to GND is req uired
for no ise de coupli ng.
Fee dback Inpu t. Th e IC sen ses fe edba ck vo ltag e via FB and reg ulate th e voltage at 0.8V.
Con necting FB with a resistor-divide r from th e o utp ut set the output voltage in th e ra nge from
0 .8V to 90% V IN .
P ower and Si gnal Gr ound .
P ower Switching Ou tpu t. LX is the Drain of th e P- ch anne l MOSFET to supp ly power to the
o utp ut. The Exp osed Pad pr ovi des curr ent with lower imped ance tha n P in 5. Conn ect th e p ad to
o utp ut L C filte r via a top-la ye r the rm al p ad on PCBs. The PCB will be a heat si nk of the IC.
Block Diagram
VIN
Current Sense
Amplifier
4.2V Regulator
and
Power-On-Reset
VCC
Current
-Limit
VCC
POR
70%VREF
UVP
UG
Soft-Start
and
Fault Logic
Soft-Start
Gate
Driver
Inhibit
UGND
Gate
Control
FB
VREF
0.8V
Error
Amplifier
COMP
Slope
Compensation
ENOK
2.5V
EN
LX
Current
Compartor
Enable
0.8V
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
OverTemperature
Protection
FB
11
Oscillator
380kHz
VIN
Linear
Regulator
GND
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APW7533
Typical Application Circuit
1. +12V Single Power Input Step-down Converter (with Electrolytic Input/Output Capacitors)
APW7533
NC
NC
16
2 VIN
3
LX
15
1
VIN
5V~20V
C3
470µF
C2
22µF
VIN
LX
4 VIN
5
LX
LX
VIN
R3 100k
C7
1µF
C8
1µF
GND
L1
10µH
VOUT
+3.3V/4A
14
D1
13
12
C1
33pF
FB 11
6 EN
7
UGNG
COMP
8 VCC
LX
10
9
R1
47k
R2
15k
R4
56k
C6
4.7nF
C4
470µF
C9
22pF
2. Single Power Input Step-down Converter (with Electrolytic Output Capacitors)
APW7533
1
VIN
5V~20V
C3
22µF
C2
22µF
NC
2 VIN
3 VIN
4 VIN
5
VIN
R3 100k
6
7
C7
1µF
C8
1µF
NC
8
EN
UGNG
VCC
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
L1
2.2µH
16
VOUT
+5V/2.5A
LX 15
LX 14
LX 13
LX
D1
GND 12
FB 11
C1
22pF
COMP 10
LX
9
R4
10k
C6
1.5nF
12
R1
63k
R2
12k
C4
220µF
C5
220µF
C9
22pF
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APW7533
Function Description
Main Control Loop
physically close to the IC to provide good noise
The APW7533 is a constant frequency current mode
switching regulator. During normal operation, the internal
decoupling. The linear regulator is not intended for
powering up any external loads. Do not connect any
P-channel power MOSFET is turned on each cycle when
the oscillator sets an internal RS latch and would be turned
external loads to VCC. The linear regulator is also
equipped with current-limit protection to protect itself dur-
off when an internal current comparator (ICMP) resets
the latch. The peak inductor current at which ICMP resets
ing over-load or short-circuit conditions on VCC pin.
VIN-to-UGND 5.5V Linear Regulator
the RS latch is controlled by the voltage on the COMP pin,
which is the output of the error amplifier (EAMP). An
The built-in 5.5V linear regulator regulates a 5.5V voltage
between VIN and UGND pins to supply bias and gate
charge for the P-channel Power MOSFET gate driver. The
external resistive divider connected between VOUT and
ground allows the EAMP to receive an output feedback
linear regulator is designed to be stable with a low-ESR
ceramic output capacitor of at least 0.22µF. It is also
voltage VFB at FB pin. When the load current increases, it
causes a slight decrease in V FB relative to the 0.8V
equipped with current-limit function to protect itself
during over-load or short-circuit conditions between VIN
reference, which in turn causes the COMP voltage to increase until the average inductor current matches the
and UGND.
new load current.
The APW7533 shuts off the output of the converters when
the output voltage of the linear regulator is below 3.5V
VCC Power-On-Reset(POR) and EN Under-voltage
Lockout
The APW7533 keeps monitoring the voltage on VCC pin
(typical). The IC resumes working by initiating a new softstart process when the linear regulator’s output voltage
to prevent wrong logic operations which may occur when
VCC voltage is not high enough for the internal control
is above the undervoltage lockout voltage threshold.
Digital Soft-Start
circuitry to operate. The VCC POR has a rising threshold
of 3.9V (typical) with 0.15V of hysteresis.
The APW7533 has a built-in digital soft-start to control the
output voltage rise and limit the input current surge
An external under-voltage lockout (UVLO) is sensed and
during start-up. During soft-start, an internal ramp,
connected to the one of the positive inputs of the error
programmed at the EN pin. The EN UVLO has a rising
threshold of 2.5V with 0.2V of hysteresis. The EN UVLO
amplifier, rises up from 0V to 1V to replace the reference
voltage (0.8V) until the ramp voltage reaches the reference
should be programmed by connecting a resistive divider
from VIN to EN to GND.
voltage.
After the VCC, EN, and VIN-to-UGND voltages exceed their
The device is designed with a preceding delay about
10.8ms (typical) before soft-start process.
respective voltage thresholds, the IC starts a start-up
process and then ramps up the output voltage to the
setting of output voltage. Connect a RC network from EN
to GND to set a turn-on delay that can be used to sequence
Output Under-Voltage Protection
the output voltages of multiple devices.
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the
In the process of operation, if a short-circuit occurs, the
VCC 4.2V Linear Regulator
required regulation range. The under-voltage continually
monitors the FB voltage after soft-start is completed. If a
VCC is the output terminal of the internal 4.2V linear
regulator which is powered from VIN and provides power
to the APW7533. The linear regulator is designed to be
load step is strong enough to pull the output voltage lower
than the under-voltage threshold, the IC shuts down
stable with a low-ESR ceramic output capacitor powers
the internal control circuitry. Bypass VCC to GND with a
converter’s output.
The under-voltage threshold is 70% of the nominal out-
ceramic capacitor of at least 0.22µF. Place the capacitor
Copyright  ANPEC Electronics Corp.
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APW7533
Function Description (Cont.)
Output Under-Voltage Protection (Cont.)
put voltage. The under-voltage comparator has a built-in
2µs noise filter to prevent the chips from wrong UVP shutdown caused by noise. The under-voltage protection
works in a hiccup mode without latched shutdown. The
IC will initiate a new soft-start process at the end of the
preceeding delay.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction temperature of the APW7533. When the junction temperature exceeds TJ = +150oC, a thermal sensor turns off the power
MOSFET, allowing the devices to cool. The thermal sensor
allows the converter to start a start-up process and
regulate the output voltage again after the junction
temperature is cooled by 50oC. The OTP is designed
with a 50oC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime
of the IC.
Enable/Shutdown
Driving EN to ground places the APW7533 in shutdown.
When in shutdown, the internal power MOSFET turns off,
all internal circuitry shuts down and the quiescent supply
current of VIN reduces to <1µA (typical).
Current-Limit Protection
The APW7533 monitors the output current, flowing through
the P-channel power MOSFET, and limits the current peak
at current-limit level to prevent loads and the IC from
damages during overload or short-circuit conditions.
Frequency Foldback
When the output is shortened to ground, the frequency of
the oscillator will be reduced to about 80kHz. This lower
frequency allows the inductor current to safely discharge,
thereby preventing current runaway. The oscillator’s
frequency will gradually increase to its designed rate
when the feedback voltage on FB again approaches 0.8V.
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APW7533
Application Information
Power Sequencing
VIN
VIN
IQ1
The APW7533 can operate with sigle or dual power input(s).
In dual-power applications, the voltage (VCC) applied at
CIN
Q1
VCC pin must be lower than the voltage (VIN) on VIN pin.
The reason is the internal parasitic diode from VCC to VIN
IL
LX
IOUT
VOUT
L
will conduct due to the forward-voltage between VCC and
VIN. Therefore, VIN must be provided before VCC.
ICOUT
D1
ESR
COUT
Setting Output Voltage
The regulated output voltage is determined by:
T=1/FOSC
VOUT
R1
= 0.8 ⋅ (1 +
)
R2
(V)
VLX
Suggested R2 is in the range from 1K to 20kΩ. For
portable applications, a 10kΩ resistor is suggested for
DT
I
IOUT
R2. To prevent stray pickup, locate resistors R1 and R2
close to APW7533.
IL
IOUT
Input Capacitor Selection
IQ1
It is necessary to turn on the P-channel power MOSFET
I
(Q1) each time when using small ceramic capacitors for
high frequency decoupling and bulk capacitors to sup-
ICOUT
VOUT
ply the surge current. Place the small ceramic capcaitors
physically close to the VIN and between VIN and the anVOUT
ode of the Schottky diode (D1)
Figure 1. Converter Waveforms
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
Output Capacitor Selection
operation, select the bulk capacitor with voltage and
current ratings above the maximum input voltage and
An output capacitor is required to filter the output and
largest RMS current required by the circuit. The capacitor
voltage rating should be at least 1.25 times greater than
supply the load transient current. The filtering requirements
are the function of the switching frequency and the ripple
the maximum input voltage and a voltage rating of 1.5
times is a conservative guideline. The RMS current (IRMS)
current (∆I). The output ripple is the sum of the voltages,
having phase shift, across the ESR and the ideal output
capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations:
of the bulk input capacitor is calculated as the following
equation:
IRMS = IOUT ⋅ D ⋅ (1- D)
(A)
where D is the duty cycle of the power MOSFET.
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be
D=
VOUT + VD
VIN + VD
........... (1)
∆I =
VOUT · (1 - D)
FOSC · L
........... (2)
VESR = ∆I · ESR
........... (3)
(V)
where VD is the forward voltage drop of the diode.
exercised with regard to the capacitor surge current
rating.
The peak-to-peak voltage of the ideal output capacitor is
calculated as the following equation:
Copyright  ANPEC Electronics Corp.
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APW7533
Application Information (Cont.)
Output Capacitor Selection (Cont.)
∆I
∆VCOUT =
(V)
8 ⋅ FOSC ⋅ COUT
and greater core losses. A reasonable starting point for
setting ripple current is ∆I ≤ 0.4 ⋅ IOUT(MAX) . Remember, the
maximum ripple current occurs at the maximum input
........... (4)
For the applications using bulk capacitors, the ∆V COUT
voltage. The minimum inductance of the inductor is calculated by using the following equation:
is much smaller than the V ESR and can be ignored.
Therefore, the AC peak-to-peak output voltage (∆VOUT ) is
VOUT · (VIN - VOUT)
≤ 1.6
380000 · L · VIN
shown as below:
∆VOUT = ∆ I ⋅ ESR
(V)
........... (5)
L≥
For the applications using ceramic capacitors, the VESR is
much smaller than the ∆V COUT and can be ignored.
VOUT · (VIN - VOUT)
608000 · VIN
(H)
........... (6)
where VIN = VIN(MAX)
Therefore, the AC peak-to-peak output voltage (∆VOUT ) is
close to ∆VCOUT .
Output Diode Selection
The Schottky diode carries load current during the off-
The load transient requirements are the function of the
time. The average diode current is therefore dependent
on the P-channel power MOSFET duty cycle. At high input
slew rate (di/dt) and the magnitude of the transient load
current. These requirements are generally met with a
voltages, the diode conducts most of the time. As VIN approaches VOUT, the diode conducts only a small fraction of
mix of capacitors and careful layout. High frequency
capacitors initially supply the transient and slow the
the time. The most stressful condition for the diode is
when the output is short-circuited. Therefore, it is impor-
current load rate seen by the bulk capacitors. The bulk
filter capacitor values are generally determined by the ESR
tant to adequately specify the diode peak current and average power dissipation so as not to exceed the diode
(Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements.
ratings.
High frequency decoupling capacitors should be placed
Under normal load conditions, the average current conducted by the diode is:
as close to the power pins of the load as physically
possible. Be careful not to add inductance in the circuit
ID =
board wiring that could cancel the usefulness of these
low inductance components. An aluminum electrolytic
VIN - VOUT
⋅ IOUT
VIN + VD
The APW7533 is equipped with whole protections to re-
capacitor’s ESR value is related to the case size with lower
ESR available in larger case sizes. However, the Equiva-
duce the power dissipation during short-circuit condition.
Therefore, the maximum power dissipation of the diode
lent Series Inductance (ESL) of these capacitors increases
with case size and can reduce the usefulness of the ca-
is calculated from the maximum output current as:
pacitor to high slew-rate transient loading.
PDIODE(MAX) = VD · ID(MAX)
Inductor Value Calculation
where
The operating frequency and inductor selection are
interrelated in that higher operating frequencies permit
IOUT = IOUT(MAX)
Remember to keep lead length short and observe proper
grounding to avoid ringing and increased dissipation.
the use of a smaller inductor for the same amount of
inductor ripple current. However, this is at the expense of
efficiency due to an increase in MOSFET gate charge
losses. The equation (2) shows that the inductance value
has a direct effect on ripple current.
Accepting larger values of ripple current allows the use of
low inductances but results in higher output voltage ripple
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
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APW7533
Layout Consideration
In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In
general, interconnecting impedance should be minimized
by using short, wide printed circuit traces. Signal and
power grounds are to be kept separating and finally combined using ground plane construction or single point
grounding. Below is a checklist for your layout:
1. Begin the layout by placing the power components
first. Orient the power circuitry to achieve a clean power
flow path. If possible, make all the connections on
one side of the PCB with wide, copper filled areas.
2. High slew rate current loop interconnecting impedances should be minimized by using wide and short
printed circuit traces.
3. Keep the sensitive small signal nodes (FB, COMP)
away from switching nodes (LX or others) on the PCB.
Therefore, place the feedback divider and the feedback compensation network close to the IC to avoid
switching noise. Connect the ground of feedback divider directly to the GND pin of the IC using a dedicated ground trace.
4. The VCC decoupling capacitor should be right next to
the VCC and GND pins. Capacitor C7 should be connected as close to the VIN and UGND pins as possible.
5. Place the decoupling ceramic capacitor C2 near the
VIN as close as possible. The bulk capacitors C3 are
also placed near VIN. Use a wide power ground plane
to connect the C2, C3, C4, C5 and Schottky diode to
provide a low impedance path between the components for large and high slew rate current.
Copyright  ANPEC Electronics Corp.
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APW7533
Package Information
TDFN5x5-16
D
A
E
b
Pin 1
D2
A1
A3
NX
E2
e
aaa C
Pin 1 Corner
K L
S
Y
M
B
O
L
TDFN5*5-16
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.20
0.30
0.008
0.012
D
4.90
5.10
0.193
0.201
D2
3.60
3.80
0.142
0.150
E
4.90
5.10
0.193
0.201
E2
4.30
4.50
0.169
0.177
e
0.50 BSC
L
0.35
K
0.20
aaa
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
0.020 BSC
0.45
0.014
0.018
0.008
0.08
0.003
18
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APW7533
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TDFN 5x5
A
H
T1
12 .4 +2.00
- 0.00
C
13.0+0.50
-0 .20
330.0±2.00
50 MIN.
P0
P1
P2
8.0 ±0.1 0
2.0±0.10
D0
1 .5 +0.10
-0 .00
4.0±0.10
d
D
W
E1
F
1.5 MIN.
20.2 MIN.
12 .0 ±0 .3 0
1.75±0.10
5 .5±0 .10
D1
T
0.6+0.0 0
-0 .4 0
A0
B0
K0
5.35 ±0 .2 0
5.35±0.20
1.00±0.20
1.5 MIN.
(mm)
Devices Per Unit
Pac kage Type
Unit
Quantity
TDFN5x 5 - 1 6
Tap e & Ree l
2500
Copyright  ANPEC Electronics Corp.
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APW7533
Taping Direction Information
TDFN5x5-16
USER DIRECTION OF FEED
Classification Profile
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APW7533
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (t p) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3
Package
Thickness
<2.5 mm
Volume mm
<350
235 °C
Volume mm
≥350
220 °C
≥2.5 mm
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2016
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Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APW7533
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
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