QUAD NON-PROGRAMMABLE PCM CODEC DESCRIPTION FEATURES • • • • • • • • • • IDT821004J 4 channel CODEC with on-chip digital filters Selectable A-law or µ-law companding Master clock frequency selection: 2.048 MHz, 4.096 MHz or 8.192 MHz − Internal timing automatically adjusted based on MCLK and frame sync signal Separate PCM and master clocks Single PCM port with up to 8.192 MHz data rate (128 time slots) Transhybrid balance impedance hardware adjustable via external components Transmit gains hardware adjustable via external components Low power +5.0 V CMOS technology +5.0 V single power supply Package available: 32 pin PLCC The IDT821004J is a single-chip, four channel PCM CODEC with on-chip filters. The device provides analog-to-digital and digital-to-analog conversions and supports both a-law and µ−law companding. The digital filters in IDT821004J provides the necessary transmit and receive filtering for voice telephone circuit to interface with time-division multiplexed systems. All of the digital filters are performed in digital signal processors operating from an internal clock, which is derived from MCLK. The fixed filters set the transmit and receive gain and frequency response. In the IDT821004J the PCM data is transmitted to and received from the PCM highway in time slots determined by the individual Frame Sync signals (FSRn and FSXn, where n = 1-4) at rates from 256 KHz to 8.192 MHz. Both Long and Short Frame Sync modes are available in the IDT821004J. The IDT821004J can be used in digital telecommunication applications such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/ Data Access Unit. FUNCTIONAL BLOCK DIAGRAM IIN1 VOUT1 IIN2 VOUT2 Anolog Front End CH1 PCM TSA 1 PCM TSA 2 Anolog Front End CH2 PCM TSA 3 DSP VOUT4 MCLK IREF PCM Interface Anolog Front End CH4 Clock & Reference Circuits FSX3 FSR3 FSX4 FSR4 TSC DR PDN 1~ 4 Control IDT and the IDT logo are trademarks of Integrated Device Technology, Inc A/µ DECEMBER 3, 2004 INDUSTRIAL TEMPERATURE RANGE 2004 Integrated Device Technology, Inc. FSR2 PCLK VCCA CNF FSX2 DGND IIN4 FSR1 DX VCCD VOUT3 PCM TSA 4 Anolog Front End CH3 AGND IIN3 FSX1 1 DSC-6807/- IDT821004J QUAD NON-PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE VOUT1 CNF PDN1 PDN2 PDN3 PDN4 MCLK 4 3 2 1 32 31 30 PIN CONFIGURATIONS IIN1 5 29 PCLK IIN2 6 28 TSC VOUT2 7 27 DGND VCCA 8 26 DX IREF 9 25 VCCD AGND 10 24 DR VOUT3 11 23 FSR1 IIN3 12 22 FSX1 IIN4 13 21 FSR2 14 15 16 17 18 19 20 VOUT4 A/µ FSX4 FSR4 FSX3 FSR3 FSX2 32-Pin PLCC 2 IDT821004J QUAD NON-PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION Name I/O Pin Number Description AGND -- 10 Analog Ground. All ground pins should be connected to the ground plane of the circuit board. VCCA -- 8 +5 V Analog Power Supply. All power supply pins should be connected to the power plane of the circuit board. DGND -- 27 Digital Ground. All ground pins should be connected to the ground plane of the circuit board. VCCD -- 25 +5 V Digital Power Supply. All power supply pins should be connected to the power plane of the circuit board. DR I 24 Receive PCM Data Input. The PCM data for Channel 1, 2, 3 and 4 is shifted serially into DR pin by the Receive Frame Sync Signal (FSR) with MSB first. A byte of data for each channel is received every 125 µs at the PCLK rate. DX O 26 Transmit PCM Data Output. The PCM data for Channel 1, 2, 3 and 4 is shifted serially out to the DX pin by the Transmit Frame Sync Signal (FSX) with MSB first. A byte of data for each channel is transmitted every 125 µs at the PCLK rate. DX is high impedance between time slots. FSR1 FSR2 FSR3 FSR4 I 23 21 19 17 Receive Frame Sync Input for Channel 1/2/3/4 This 8kHz signal pulse identifies the receive time slot for Channel N on a system’s receive PCM frame. It must be synchronized to PCLK. I 22 20 18 16 Transmit Frame Sync Input for Channel 1/2/3/4 This 8 kHz signal pulse identifies the transmit time slot for Channel N on a system’s transmit PCM frame. It must be synchronized to PCLK. O 9 Reference Current. The IREF output is biased at the internal reference voltage. A resistor placed from IREF to ground sets the reference current used by the analog-to-digital converter to encode the signal current present on IINn pin (n is channel number, n = 1 to 4) into digital form. O 4 7 11 14 Voice Frequency Receiver Output for Channel 1/2/3/4 This is the output of receiver amplifier for Channel N. The received digital data from DR is processed and converted to an analog signal at this pin. I 5 6 12 13 Voice Frequency Transmitter Input for Channel 1/2/3/4 This is the input to the gain setting amplifier in the transmit path for Channel N. The analog voice band voltage signal is applied to this pin through a resistor. This input is a virtual AC ground input, which is biased at the IREF pin. 30 Master Clock. The Master Clock provides the clock for the DSP. It can be either 2.048 MHz or 4.096 MHz. The IDT821004J determines the MCLK frequency via the FSX inputs and makes the necessary internal adjustments automatically. The MCLK frequency must be an integer multiple of the FSX frequency. FSX1 FSX2 FSX3 FSX4 IREF VOUT1 VOUT2 VOUT3 VOUT4 IIN1 IIN2 IIN3 IIN4 MCLK I PCLK I 29 PCM Clock. The PCM Clock shifts out the PCM data to the DX pin and shifts in PCM data from the DR pin. The PCM clock frequency is an integer multiple of the frame sync frequency. When PCLK is connected to MCLK, the PCM clock can generate the DSP clock as well. TSC O 28 Time Slot Control. This open drain output is low active. When the PCM data is transmitted to the DX pin for any of the four channels, this pin will be pulled low. A/µ I 15 A/µ-Law Selection. When this pin is low, µ-Law is selected; when this pin is high, A-Law is selected. This pin can be connected to VCCD or DGND pin directly. 3 IDT821004J QUAD NON-PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION (cont’d) Name I/O Pin Number Description PDN1 PDN2 PDN3 PDN4 I 2 1 32 31 Channel 1/2/3/4 Power Down. When this pin is high, Channel N is powered down. CNF O 3 Capacitor For Noise Filter. This pin should be connected to AGND through a 0.1µF capacitor. NC -- No connection 4 IDT821004J QUAD NON-PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE FUNCTIONAL DESCRIPTION Transmit PCM Interface The transmit PCM interface clocks out 1 byte (8 bits) PCM data out of DX pin every 125 µs. The transmit logic, synchronized by the Transmit Frame Sync signal (FSXn), controls the data transmission. The FSXn pulse identifies the transmit time slot of the PCM frame for Channel N. The PCM Data is transmitted serially on DX pin with the Most Significant Bit (MSB) first. When the PCM data is being output on DX pin, the TSC signal will be pulled low. The IDT821004J contains four channel PCM CODEC with on chip digital filters. It provides the four-wire solution for the subscriber line circuitry in digital switches. The device converts analog voice signal to digital PCM data, and converts digital PCM data back to analog signal. Digital filters are used to bandlimit the voice signals during the conversion. Either A-law or µ-law is supported by the IDT821004J. The law selection is performed by A/µ pin. The frequency of the master clock (MCLK) can be 2.048 MHz, 4.096 MHz, or 8.192 MHz. Internal circuitry determines the master clock frequency automatically. The serial PCM data for four channels are time multiplexed via two pins, DX and DR. The time slots of the four channels are determined by the individual Frame Sync signals at rates from 256 kHz to 8.192 MHz. For each channel, the IDT821004J provides a transmit Frame Sync signal and a receive Frame Sync signal. Each channel of the IDT821004J can be powered down independently to save power consumption. The Channel Power Down Pins PDN1-4 configure channels to be active (power-on) or standby (power-down) separately. Receive Signal Processing In the receive path, the PCM code is received at the rate of 8,000 samples per second. The PCM code is expanded and sent to the DSP for interpolation. A receive filter is implemented in the DSP as a digital lowpass filter. The filtered signal is then sent to an oversampling DAC. The DAC output is post-filtered and delivered at VOUT pin by an amplifier. The amplifier can drive resistive load higher than 2 KΩ. Receive PCM Interface The receive PCM interface clocks 1 byte (8 bits) PCM data into DR pin every 125 µs. The receive logic, synchronized by the Receive Frame Sync signal (FSRn), controls the data receiving process. The FSRn pulse identifies the receive time slot of the PCM frame for Channel N. The PCM Data is received serially on DR pin with the Most Significant Bit (MSB) first. Signal Processing High performance oversampling Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC) are used in the IDT821004J to provide the required conversion accuracy. The associated decimation and interpolation filtering are realized with both dedicated hardware and Digital Signal Processor (DSP). The DSP also handles all other necessary functions such as PCM bandpass filtering and sample rate conversion. Hardware Gain Setting In Transmit Path The transmit gain of the IDT821004J for each channel can be set by 2 resistors, RREF and RTXn (as shown in Figure 1), according to the following equation: Transmit Signal Processing In the transmit path, the analog input signal is received by the ADC and converted into digital data. The digital output of the oversampling ADC is decimated and sent to the DSP. The transmit filter is implemented in the DSP as a digital bandpass filter. The filtered signal is further decimated and compressed to PCM format. to SLIC VTX Gt = The receive gain of IDT821004J is fixed and equal to 1. IDT821004J CTX1 RTX1 A/D IREF VIN1 VREF to IREF Bal Net to SLIC RSN 3 × R REF R TXn RRX1 IREF1 VREF1 CRX1 VOUT1 RREF1 CFIL VREF D/A Figure 1. IDT821004J Transmit Gain Setting for Channel 1 5 IDT821004J QUAD NON-PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE OPERATING THE IDT821004J The following descriptions about operation applies to all four channels of the IDT821004J. Power-on Sequence and Master Clock Configuration To power on the IDT821004J users should follow this sequence: 1. Apply ground; 2. Apply VCC, finish signal connections; 3. Set PDN1-4 pins high, thus all of the 4 channels are powered down; The master clock (MCLK) frequency of IDT821004J can be configured as 2.048 MHz, 4.096 MHz or 8.192 MHz. Using the Transmit Frame Sync (FSX) inputs, the device determines the MCLK frequency and makes the necessary internal adjustments automatically. The MCLK frequency must be an integer multiple of the Frame Sync frequency. Operating Modes There are two operating modes for each transmit or receive channel: standby mode (when the channel is powered down) and normal mode (when the channel is powered on). The mode selection of each channel is done by its corresponding PDN pin. When PDNn is 1, Channel N is in standby mode; when PDNn is 0, Channel N is in normal mode. In standby mode, all circuits are powered down with the analog outputs placed in high impedance state. In normal mode, each channel of the IDT821004J is able to transmit and receive both PCM and analog information. The normal mode is used when a telephone call is in progress. Companding Law Selection An A/µ pin is provided by IDT821004J for the companding law selection. When this pin is low, µ-law is selected; when the pin is high, A-law is selected. 6 IDT821004J QUAD NON-PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS Rating Power Supply Voltage Voltage on Any Pin with Respect to Ground Package Power Dissipation Storage Temperature Com’I & Ind’I ≤ 6.5 -0.5 to 5.5 Unit V V ≤ 600 -65 to +150 mW °C RECOMMENDED DC OPERATING CONDITIONS Parameter Operating Temperature Power Supply Voltage Min. -40 4.75 Typ. Max. +85 5.25 Unit °C V NOTE: MCLK: 2.048 MHz, 4.096 MHz or 8.192 MHz with tolerance of ± 50 ppm NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS Digital Interface Parameter VIL VIH VOL Description Input Low Voltage Input High Voltage Output Low Voltage Min Typ Max 0.8 VDD-0.6 V V Test Conditions All digital inputs All digital inputs DX, TSC,IL = 14mA All other digital outputs, IL = 4mA. All digital pins, IL = 14mA DX, IH = -7 mA, all other outputs, IH = -4 mA VDD-0.2 V All digital pins, IH = -1mA µA µA pF Any digital inputs GND<VIN<VDD DX 2.0 0.4 0.8 Units V V V V 0.2 VOH II IOZ CI Output High Voltage Input Current Output Current in High-impedance State Input Capacitance -10 -10 10 10 5 Note: Total current must not exceed absolute maximum ratings. Power Dissipation Parameter PD2 PD1 PD0 Description Operating Power Dissipation 1 Operating Power Dissipation 1 Standby Power Dissipation Min Typ 180 60 4 Max 240 90 10 Units mW mW mW Test Conditions All channels are active Only one channel is active All channels are powered down,with only MCLK present Note: Power measurements are made at MCLK = 4.096 MHz, outputs unloaded Analog Interface Parameter VOUT1 VOUT2 RO RL IIR IIOS IOUT IZ CL Description Output Voltage Output Voltage Swing Output Resistance Load Resistance Analog Input Current Range Offset Current Allowed on IIN VOUT Output Current (F< 3400Hz) Output Leakage Current Load Capacitance Min 2.25 3.25 Typ 2.4 Max 2.6 1 4 2000 ±40 -1.6 -5 -10 +1.6 5 10 100 7 Units V V P-P Ω Ω µA µA mA µA pF Test Conditions Alternating±zero µ-law PCM code applied to DR. RL=2000Ω 0dBm0, 1020Hz PCM code applied to DR External loading RREF = 13kΩ Power down External loading IDT821004J QUAD NON-PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE TRANSMISSION CHARACTERISTICS 0dBm0 is defined as 0.6832Vrms for A-law and 0.6778 Vrms for µ-law, both for 600 Ω load. Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave; the input amplifier is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Typical value are tested at VDD = 5V and TA = 25°C. Absolute Gain Parameter GXA GRA Description Transmit Gain, Absolute 0°C to 85°C -40°C Receive Gain, Absolute 0°C to 85°C -40°C Min Typ Max Units -0.30 -0.40 0.30 0.40 dB dB -0.30 -0.40 0.30 0.40 dB dB Test Conditions Signal input of 0 dBm0, µ-law or A-law Measured relative to 0 dBm0, µ-law or A-law, PCM input of 0 dBm0 1020 Hz, RL = 10 kΩ Gain Tracking Parameter GTX GTR Description Transmit Gain Tracking +3 dBm0 to -37 dBm0 (exclude -37 dBm0) -37 dBm0 to -50 dBm0 (exclude -50 dBm0) -50 dBm0 to -55 dBm0 Receive Gain Tracking +3 dBm0 to -40 dBm0 (exclude -40 dBm0) -40 dBm0 to -50 dBm0 (exclude -50 dBm0) -50 dBm0 to -55 dBm0 Min Typ Max Units -0.25 -0.50 -1.40 0.25 0.50 1.40 dB dB dB -0.10 -0.25 -0.50 0.10 0.50 0.50 dB dB dB Test Conditions Tested by sinusoidal method, A-law or µ-law Tested by sinusoidal method, A-law or µ-law Frequency Response Parameter GXR GRR Description Transmit Gain, Relative to GXA f = 50 Hz f = 60 Hz f = 300 Hz to 3000 Hz f = 3000 Hz to 3400 Hz f = 3600 Hz f ≥ 4600 Hz Receive Gain, Relative to GRA f < 300 Hz f = 300 Hz to 3000 Hz f = 3000 Hz to 3400 Hz f = 3600 Hz f ≥ 4600 Hz Min Typ -0.15 -0.4 -0.15 -0.4 Max Units -30 -30 0.15 0.15 -0.1 -35 dB dB dB dB dB dB 0 0.15 0.15 -0.2 -35 dB dB dB dB dB Max 340 Units µs 280 150 80 280 260 µs µs µs µs µs 50 80 120 150 µs µs µs µs Test Conditions Group Delay Parameter D XA D XR D RA D RR Description Transmit Delay, Absolute * Transmit Delay, Relative to 1800 Hz f = 500 Hz – 600 Hz f = 600 Hz –1000 Hz f = 1000 Hz – 2600 Hz f = 2600 Hz – 2800 Hz Min Typ Receive Delay, Absolute * Receive Delay, Relative to 1800 Hz f = 500 Hz – 600 Hz f = 600 Hz –1000 Hz f = 1000 Hz – 2600 Hz f = 2600 Hz – 2800 Hz Note*: Minimum value in transmit and receive path. 8 Test Conditions IDT821004J QUAD NON-PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE Distortion Parameter STDX SFDX Description Transmit Signal to Total Distortion Ratio A-law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 µ-law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 Receive Signal to Total Distortion Ratio A-law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 µ-law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 Single Frequency Distortion, Transmit SFDR Single Frequency Distortion, Receive -42 dBm0 IMD Intermodulation Distortion -42 dBm0 Max 16 -68 12 -78 -53 Units dBrnC0 dBm0p dBrnC0 dBm0p dBm0 STDR Min Typ Max Units 36 36 30 24 dB dB dB dB 36 36 31 27 dB dB dB dB Test Conditions ITU-T O.132 Sine Wave Method,Psophometric Weighted for Alaw, C Message Weighted for µ-law. ITU-T O.132 36 36 30 24 dB dB dB dB 36 36 31 27 -42 dB dB dB dB dBm0 Sine Wave Method,Psophometric Weighted for Alaw;Sine Wave Method,C Message Weighted for µlaw; 200 Hz - 3400 Hz, 0 dBm0 input, output any other single frequency ≤ 3400 Hz 200 Hz - 3400 Hz, 0 dBm0 input, output any other single frequency ≤ 3400 Hz Transmit or receive,two frequencies in the range (300 Hz− 3400 Hz) at −6 dBm0 Noise Parameter NXC NXP NRC NRP NRS PSRX PSRR SOS Description Transmit Noise, C Message Weighted for µ-law Transmit Noise, Psophometric Weighted for A-law Receive Noise, C Message Weighted for µ-law Receive Noise, Psophometric Weighted for A-law Noise, Single Frequency f = 0 kHz – 100 kHz Power Supply Rejection Transmit f = 300 Hz – 3.4 kHz f = 3.4 kHz – 20 kHz Power Supply Rejection Receive f = 300 Hz – 3.4 kHz f = 3.4 kHz – 20 kHz Spurious Out-of-Band Signals at VOUT Relative to Input PCM code applied: 4600 Hz – 20 kHz 20 kHz – 50 kHz Min Typ Test Conditions IIN = 0 A, tested at VOUT VDD = 5.0 VDC + 100 mVrms 40 25 dB dB 40 25 dB dB PCM code is positive one LSB, VDD = 5.0 VDC + 100 mVrms 0 dBm0, 300 Hz – 3400 Hz input -40 -30 9 dB dB IDT821004J QUAD NON-PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE Interchannel Crosstalk Parameter Description Min Typ Max Units XTX-R Transmit to Receive Crosstalk -85 -78 dB XTR-X Receive to Transmit Crosstalk -85 -80 dB XTX-X Transmit to Transmit Crosstalk -85 -78 dB XTR-R Receive to Receive Crosstalk -85 -80 dB Test Conditions 300 Hz – 3400 Hz, 0 dBm0 signal into IIN of interfering channel. Idle PCM code into channel under test. 300 Hz – 3400 Hz, 0 dBm0 PCM code into interfering channel. IIN = 0 A for channel under test. 300 Hz – 3400 Hz, 0 dBm0 signal into IIN of interfering channel. IIN = 0 A for channel under test. 300 Hz – 3400 Hz, 0 dBm0 PCM code into interfering channel. Idle PCM code into channel under test. Intrachannel Crosstalk Parameter XTX-R XTR-X Description Transmit to Receive Crosstalk Receive to Transmit Crosstalk Min Typ -80 -80 Max -70 -70 Units dB dB 10 Test Conditions 300 Hz – 3400 Hz, 0 dBm0 signal into IIN. Idle PCM code into DR. 300 Hz – 3400 Hz, 0 dBm0 PCM code into DR. IIN = 0 A. IDT821004J QUAD NON-PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE TIMING CHARACTERISTICS Clock Parameter t1 t2 t3 Description PCLK Duty Cycle PCLK Rise and Fall Time MCLK Duty Cycle Min 40 t4 MCLK Rise and Fall Time t5 PCLK Clock Period 244 Description Data Output Delay Time (for Short Frame Sync Mode) Data Hold Time Data Delay to High-Z Min 5 Frame sync Hold Time Frame sync High Setup Time 50 55 5 Typ 40 Max 60 25 60 Units % ns % 15 ns ns Test Conditions PCLK=512kHz to 8.192MHz PCLK=512kHz to 8.192MHz MCLK=2.048Hz,4.096MHz or 8.192MHz MCLK=2.048Hz,4.096MHz or 8.192MHz PCLK=512kHz to 8.192MHz Transmit Parameter t11 t12 t13 t14 t15 t16 t17 t18 t19 t21 t22 5 50 TSC Enable Delay Time(for Short Frame Sync Mode) TSC Disable Delay Time 50 Data Output Delay Time(for Long Frame Sync Mode) TSC Enable Delay Time(for Long Frame Sync Mode) Receive Data Setup Time Receive Data Hold Time Typ Max 70 Units ns 70 220 t5+70 ns ns t5-50 80 ns ns ns ns 5 220 t5+70 40 5 40 ns 25 5 ns ns ns Note: Timing parameter t13 is referenced to a high-impedance state. MCLK t4 t4 Figure 2. MCLK Timing 11 Test Conditions IDT821004J QUAD NON-PROGRAMMABLE PCM CODEC INDUSTRIAL TEMPERATURE RANGE Time Slot 1 PCLK t15 2 t14 3 4 5 t2 6 t2 7 8 t5 FSX/ FSR DX BIT 1 BIT 3 BIT 2 BIT 1 BIT 4 BIT 5 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 7 BIT 8 t22 t21 DR t13 t12 t11 BIT 2 BIT 3 BIT 6 t17 t16 TSC Figure 3. PCM Interface Timing for Short Frame Mode Time Slot PCLK 1 2 3 4 5 6 7 1 8 t5 t15 t2 t2 FSX/ FSR DX BIT 1 BIT 2 t21 DR BIT 1 t13 t12 t18 BIT 2 BIT 3 BIT 4 BIT 5 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 7 BIT 8 t22 BIT 3 BIT 6 t17 t19 TSC Figure 4. PCM Interface Timing for Long Frame Mode 12 ORDERING INFORMATION IDT XXXXXXX XX Device Type Package X Process/ Temperature Range Blank Industrial (-40 °C to +85 °C) J Plastic Leaded Chip Carrier (PLCC, PL32) 821004J Quad Non-Programmable PCM CODEC Data Sheet Document History CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 13 for Tech Support: 408-330-1552 email: [email protected]