Pad Layouts/Soldering Process www.vishay.com Vishay General Semiconductor Pad Layouts/Soldering Process VISHAY GENERAL SEMICONDUCTOR RECOMMENDED MINIMUM MOUNTING PAD LAYOUT SIZES FOR THE SURFACE MOUNT RECTIFIER DFS BRIDGE MBS BRIDGE 0.047 (1.20) MIN. MBLS BRIDGE 0.023 (0.58) MIN. DO-214AC (SMA)/ DO-214BA (GF1) 0.028 (0.7) MIN. 0.074 (1.88) MAX. 0.066 (1.68) MIN. 0.404 (10.26) MAX. 0.272 (6.91) MAX. 0.030 (0.76) MIN. 0.252 (6.4) MAX. 0.016 (0.45) MIN. 0.060 (1.52) MIN. 0.208 (5.28) REF. 0.060 (1.52) MIN. 0.165 (4.2) 0.150 (3.8) 0.105 (2.67) 0.095 (2.41) 0.205 (5.2) 0.195 (5.0) TO-263 DO-214AA (SMB) 0.42 (10.66) MIN. 0.085 (2.159) MAX. DO-214AB (SMC) 0.185 (4.69) MAX. 0.086 (2.18) MIN. 0.33 (8.38) MIN. 0.670 (17.02) 0.591 (15.00) 0.060 (1.52) MIN. 0.126 (3.20) MIN. 0.060 (1.52) MIN. 0.320 (8.13) REF. 0.220 (5.59) REF. MicroSMP 0.079 (2.00) 0.15 (3.81) MIN. 0.032 (0.80) 0.032 (0.80) 0.043 (1.10) 0.08 (2.032) MIN. 0.105 (2.67) 0.095 (2.41) 0.020 (0.50) DO-220AA (SMP) TO-277A (SMPC) 0.189 (4.80) MIN. 0.105 (2.67) 0.025 (0.635) DO-213AA (GL34)/ DO-213AB (GL-41) 0.030 (0.762) C 0.186 (4.72) MIN. 0.100 (2.54) 0.268 (6.80) 0.050 (1.27) MIN. 0.050 (1.27) B D A 0.041 (1.04) 0.055 (1.40) MIN. All dimensions in inches (millimeters) Revision: 12-Sep-13 Document Number: 88854 1 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Pad Layouts/Soldering Process www.vishay.com Vishay General Semiconductor TO-263AC (SMPD) DO-221AC (SlimSMA) 0.420 (10.66) MIN. 0.060 (1.52) MIN. 0.123 (3.12) MAX. 0.047 (1.20) MIN. 0.047 (1.20) MIN. 0.217 (5.52) REF. 0.330 REF. (8.38) 0.420 (10.66) MIN. 0.604 (15.33) 0.525 (13.33) DO-221BC (SMPA) MAX. 0.037 (0.92) 0.087 (2.20) MIN. 0.060 (1.52) MIN. MIN. 0.122 (3.10) MIN. 0.059 (1.50) 0.120 (3.05) REF. 0.105 (2.67) 0.095 (2.41) 0.080 (2.03) MIN. 0.217 (5.52) DIMENSIONS in inches (millimeters) DO-213AA (GL34) DO-213AB (GL41) A 0.177 (4.5) ref. 0.236 (6.0) ref. B 0.079 (2.0) min. 0.118 (3.0) min. C 0.079 (2.0) max. 0.138 (3.5) max. D 0.050 (1.25) min. 0.050 (1.25) min. VISHAY GENERAL SEMICONDUCTOR RECOMMENDED SOLDERING PROCESS Through hole device (THD) and surface mount device (SMD) imply different soldering technologies leading to different constraints. In THD, the package body is exposed to relatively low temperatures (< 150 °C) because the lead extremeties are only dipped in the soldering alloy, whereas in SMD the whole package body is exposed to a very high temperature (> 240 °C) during reflow soldering process. In addition, molding compounds used for encapsulation absorb moisture from the ambient medium. During rapid heating in solder reflow process; this absorded moisture can vaporize, generating pressure at lead frame pad/silicon to plastic interfaces in the package, with a risk of package cracking and potential degradation of device reliability. Wave soldering with SMD packages is not recommended because the thermal shock associated with package body solder dipping may induce internal structural damage to the package (interface delamination) that may affect long term reliability. SMD package characterizations performed as a standard by Vishay only induce Solder Reflow Resistance assessment. JEDEC JESD A111 recommends that wave soldering of SMD packages should be evaluated by the USER, because the stress induced inside the package is very dependant of solder process parameters. Due to the higher melting point of lead (Pb)-free alloys, the temperature of the solder pot will also increase to improve solderability and shorten contact times. For AgSnCu with melting point of 217 °C, the solder pot temperature will be between 250 °C to 270 °C or as high as 260 °C to 280 °C for SnCu. Revision: 12-Sep-13 Document Number: 88854 2 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Pad Layouts/Soldering Process www.vishay.com Vishay General Semiconductor RECOMMENDED WAVE SOLDERING PROFILE FOR THROUGH HOLE COMPONENTS Lead (Pb)-free Pb 300 Full line: typical Dotted line: process limits 10 s T3 235 °C ~ 260 °C First wave 200 < 105 °C to 165 °C - 5 °C/s - 2 °C/s + 200 °C/s 150 100 °C ~ 130 °C 100 50 Second wave First wave Second wave Temperature (°C) Temperature (°C) 250 Forced cooling + 2 °C/s Tmelt 217 °C T2 Preheating 180 °C max. 50 6 °C/s max. 4 °C/s max. T1 Preheating 130 °C min. Activation of Flux 0 0 t (w1 + w2) 7 +- 02 S 270 °C +/- 5 °C 100 150 200 t1 2 min to 5 min 250 Time (s) Time Notes • Temperature jump from T2 to T3 (w1): 150 °C max. • Time from 25 °C to T3 (wave temp.): 8 min max. Fig. 1 Fig. 2 REFLOW FOR SURFACE MOUNTED COMPONENTS TABLE 1 - CLASSIFICATION REFLOW PROFILE PROFILE FEATURE Sn-Pb EUTECTIC ASSEMBLY LEAD (Pb)-FREE ASSEMBLY Preheat and soak Temperature min. (TSmin.) 100 °C 150 °C Temperature max. (TSmax.) 150 °C 200 °C Time (TSmin. to TSmax.) (tS) 60 s to 120 s Average ramp-up rate (TSmax. to Tp) Liquidous temperature (TL) Time to liquidous (tL) Peak package temperature (Tp) (1) Time (tp) (2) with 5 °C of the specified classification temperature (TC) 183 °C 217 °C 60 s to 150 s 60 s to 150 s See classification temperature in table 2 See classification temperature in table 3 20 s (2) 30 s (2) Average ramp-down rate (Tp to TSmax.) Time 25 °C to peak temperature 60 s to 120 s 3 °C/s maximum 6 °C/s maximum 6 min maximum 8 min maximum Notes (1) Tolerance for peak profile temperature (T ) is defined as a supplier minimum and user maximum p (2) Tolerance for time at peak profile temperature (T ) is defined as a supplier minimum and user maximum p Revision: 12-Sep-13 Document Number: 88854 3 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Pad Layouts/Soldering Process www.vishay.com Vishay General Semiconductor REFLOW PROFILE Supplier TP ≥ TC User TP ≤ TC TC TC - 5 °C Supplier tP User tP TP tp Max. Ramp Up Rate = 3 °C/s Max. Ramp Down Rate = 6 °C/s TL Temperature TSmax. TC - 5 °C t Preheat Area TSmin. tS 25 Time 25 °C to Peak Time Fig. 3 TABLE 2 - Sn-Pb EUTECTIC PROCESS PACKAGE PEAK REFLOW TEMPERATURES VOLUME mm3 < 350 VOLUME mm3 ≥ 350 < 2.5 mm 235 °C 220 °C ≥ 2.5 mm 220 °C 220 °C PACKAGE THICKNESS TABLE 3 - LEAD (Pb) - FREE PROCESS PACKAGE CLASSIFICATION REFLOW TEMPERATURES PACKAGE THICKNESS VOLUME mm3 < 350 VOLUME mm3 350 TO 2000 VOLUME mm3 > 2000 < 1.6 mm 260 °C 260 °C 260 °C 1.6 mm to 2.5 mm 260 °C 250 °C 245 °C ≥ 2.5 mm 250 °C 245 °C 245 °C Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature at the rated MSL level. Notes • Package volume excludes external terminals (balls, bumps, lands, leads) and/or non-integral heatsinks. • The maximum component temperature reached during reflow depends on package thickness and volume. The use of convection reflow processes reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD packages may still exist. • Recommended soldering process is accordance with J-STD-020D. Revision: 12-Sep-13 Document Number: 88854 4 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000