64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT IDT49C466 IDT49C466A Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 64-bit wide Flow-thruEDC • Separate System and Memory Data Input/Output Buses • — Error Detect Time: 10ns — Error Correct Time: 15ns • Corrects all single bit errors; Detects all double bit errors and some multiple bit errors • Configurable 16-deep bus read/write FIFOs with flags • Simultaneous check bit generation and correction of memory data • Supports partial word writes on byte boundaries • Low noise output • Sophisticated error diagnostics and error logging • Parity generation on system data bus • 208-pin Plastic Quad Flatpack The IDT49C466/A 64-bit Flow-thruEDC is a high-speed error detection and correction unit that ensures data integrity in memory systems. The flow-thru architecture, with separate system and memory data buses, is ideally suited for pipelined memory systems. Implementing a modified Hamming code, the IDT49C466/A corrects all single bit hard and soft errors, and detects all double bit errors. The read/write FIFOs can store up to sixteen words. FIFO full and empty flags indicate whether additional data can be written to or read from the EDC. Check bit generation for partial word writes on byte boundaries is supported on the IDT49C466/A. Diagnostic features include a check bit register, syndrome registers, a four bit error counter which logs up to 15 errors, and an error data register which stores the complete error data word. Parity can be generated and checked on the system bus by the IDT49C466/A. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM CHECK-BIT COMPARATOR & SYNDROME GENERATOR & ERROR DETECTOR ERR MERR M U X SD0-63 READ BUFFER 16 WORDS BY 64 MD LATCH OUT M U X DIAGNOSTIC & STATUS REGISTERS MD CHECK-BIT GENERATOR MD CHK-BIT LATCH CBI0-7 MD LATCH IN ERROR CORRECT WRITE BACK PATH MD0-63 SD LATCH IN WRITE BUFFER 16 WORDS BY 72 PARITY P0-7 M U X B Y T E M U X SD LATCH OUT SD CHECK-BIT GENERATOR SD CHK-BIT LATCH CBSYN0-7 PARITY GENERATE & PARITY CHECK 2617 drw 01 The IDT logo is a registered trademark and Flow-thruEDC is a trademark of Integrated Device Technology Inc. COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. AUGUST 1996 11.7 DSC-2617/9 1 11.7 PERR P 0-7 WBEN WBREN SCLK MEN SDILE SD 0-63 BE 0-7 SOE RBFF RBHF RBEF RBSEL RBREN RS 0-1 RBEN MCLK MDOLE 8 8 8 MODE REGISTER SD0-15 0 Mode Bit 5 PARITY CHECK PARITY GEN 1 SCLK control 72 wide Write Fifo SD Latch In MUX DEMUX MCLK RS 0-1 RWBD (Bit 4, Mode Reg) Write Back Path MD Latch Out RWBD (Bit 4, Mode Reg) 64 wide Read Fifo Control 8 MUX BE 0-7 MUX 30-37 28-29 24-27 16-23 8 1 0 Diagnostic path SD to MD Path 8 Error data 0 1 8 BYTE MUX ChkBit Latch SD SD Latch Out MD Latch In ChkBit Latch MD 0 POWER SUPPLY 1 17 4 Mode Bit 2 8 MUX 8 CBI 0-7 GND V CC WBSEL CBSYN 0-7 CBSEL SDOLE MOE MD 0-63 SYNCLK MDILE 49C466/A 64-Bit Flow-ThruEDC 8 SD Check-bit Generator CLEAR from mode register MERR ERR MD Check Bit Generator Diagnostic Registers Chkbit Syndrome (on 1st error) Err Count Err Type Syndrome (on every error) MD to SD Path ERROR CORRECT 0-7 8-15 GENERATOR SYNDROME Check Bit Injection Mode MERR MUX ERROR DETECT MUX MUX ERR IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES WBFF WBEF 2617 drw 02 2 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES GND MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 CBSYN7 CBSYN6 CBSYN5 CBSYN4 GND CBSYN3 CBSYN2 CBSYN1 CBSYN0 VCC GND WBSEL CBSEL WBREN GND WBEN SYNCLK WBFF WBEF SD63 SD62 SD61 SD60 P7 BE7 GND SD59 SD58 SD57 SD56 SD55 SD54 SD53 SD52 P6 BE6 SD51 SD50 SD49 SD48 SD47 VCC PIN CONFIGURATION 1 157 156 208 PQ208-2 105 104 52 53 GND SD46 SD45 SD44 BE5 P5 SD43 SD42 SD41 SD40 SD39 SD38 SD37 SD36 BE4 GND P4 SD35 SD34 SD33 SD32 PERR MCLK MDOLE RS1 MEN GND RS_0 SDILE SCLK SOE SD31 SD30 SD29 SD28 BE3 P3 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 BE2 P2 SD19 SD18 SD17 SD16 GND GND MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 ERR MERR CBI7 CBI6 CBI5 CBI4 CBI3 GND CBI2 CBI1 CBI0 RBEN RBREN RBSEL GND VCC RBHF RBEF RBFF SD0 SD1 SD2 SD3 GND P0 BE0 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 BE1 P1 SD12 SD13 SD14 SD15 GND GND MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 SDOLE MOE MDILE MD31 GND MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 GND MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 VCC PQFP Top View 2617 drw 04 11.7 3 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION Pin Name I/O Description Data Buses SD0-63 I/O System Data Bus: is a bidirectional 64-bit bus interfacing to the system or CPU. When System Output Enable, SOE, is HIGH or Byte Enable, BE0-7, is LOW, data can be input. When System Output Enable, SOE, is LOW and Byte Enable, BE0-7, is HIGH, the SD bus output drivers are enabled. MD0-63 I/O Memory Data Bus: is a bidirectional 64-bit bus interfacing to the memory. During a read cycle, (MOE HIGH) memory data is input for error detection and correction. Data is output on the Memory Data Bus, when MOE is LOW. CBI0-7 I Check Bit Inputs: interface to the check bit memory. CBSYN0-7 O Check Bit/Syndrome Output: When MOE is LOW the generated check bits are output. When CBSEL is HIGH and MOE is HIGH, the syndrome bits are output. The bus is tristated when MOE = 1 and CBSEL = 0. P0-7 I/O Parity for bytes 0 to 7: These pins are parity inputs when the corresponding Byte Enable (BE) is LOW or SOE is HIGH, and are used to generate the parity error signal (PERR). These pins are outputs when the corresponding Byte Enable (BE) is HIGH and SOE is LOW. SOE I System Output Enable: enables system data bus output drivers if the corresponding Byte Enable (BE0-7) is HIGH. BE0-7 I Byte Enable: is used along with SOE, to enable the System Data outputs for a particular byte. For example, if BE1 is HIGH, the System data outputs for byte 1 (SD8-15) are enabled. The BE0-7 pins also control the byte mux. If a particular BE is HIGH during a memory read cycle, that byte is fed back to the memory data bus. This is used during partial word write operations and writing corrected data back to memory. MOE I Memory Output Enable: when LOW, enables the output buffers of the memory data bus (MD) and CBSYN bus. It also controls the CBSYN mux. When LOW, checkbits are selected, when HIGH, syndrome is selected. MDILE I Memory Data Input Latch Enable: on the HIGH-to-LOW transition, latches MD and CBI in MD input latch and MD check bit latch respectively. The latches are transparent when MDILE is HIGH. MDOLE I Memory Data Output Latch Enable: latches data in the MD output latch on the LOW-to-HIGH transition of MDOLE. When MDOLE is LOW, the MD output latch is transparent. SDOLE I System Data Output Latch Enable: latches data in the SD output latch and the SD checkbit latch on the LOW-to-HIGH transition of SDOLE. The latch is transparent when SDOLE is LOW. SDILE I System Data Input Latch Enable: latches SD in the SD input latch on the HIGH-to-LOW transition. When SDILE is HIGH, the SD input latch is transparent. WBSEL I Write FIFO Select: when HIGH, the write FIFO is selected. When WBSEL is LOW, the SD input latch is selected. WBEN I Write FIFO Enable: when LOW, allows SD data to be written to the write FIFO on the SCLK rising edge. WBREN I Write FIFO Read Enable: when LOW, allows data to be read from the the write FIFO on MCLK rising edge. RS0-1 I Reset and Select pins (read and write FIFO FIFOs) RS1 RS0 Function 0 0 Reset 16-deep FIFO or first 8-deep FIFO 0 1 Reset second 8-deep FIFO 1 0 Select 16-deep FIFO or first 8-deep FIFO 1 1 Select second 8-deep FIFO Control Inputs 2617 tbl 01 11.7 4 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION (Continued) Pin Name I/O Description RBSEL I Read FIFO Select: when HIGH, read FIFO is selected (data goes through read FIFO, not MD output latch). When LOW, the MD output latch is selected. RBEN I Read FIFO Enable: when LOW, allows data to be written into the read FIFO on the LOW-to-HIGH transition of the memory clock. RBREN I Read FIFO Enable: when LOW, allows data to be read from the read FIFO on the LOW-to-HIGH transition of SCLK CBSEL I Checkbit Syndrome Output Enable: Controls the CBSYN output buffer.When HIGH, the buffer is enabled. When CBSEL is LOW, MOE controls the buffer. MEN I Mode Enable Input: when LOW, SD0-15 is loaded into the EDC mode register on the LOW-to-HIGH transition of the SCLK. This pin must be held LOW for the entire SCLK HIGH period, as shown in Figure 4. MCLK I Memory Clock: on the LOW-to-HIGH transition of MCLK, memory data is written to the read FIFO when RBEN is LOW. Data is read from the write FIFO when WBREN is LOW, on the LOW-to-HIGH transition of MCLK. SCLK I System Clock: on the LOW-to-HIGH transition of the SCLK, data is read from the read FIFO when RBREN is LOW. Data on the system data bus is written into the write FIFO when WBEN is LOW on the LOW-to-HIGH transition of SCLK. Clocks data into mode register when MEN is LOW. SYNCLK I Syndrome Clock: Used to load diagnostic registers. When an error occurs, Error Counter is incremented on the rising SYNCLK edge (up to 15 errors). On the first error after a diagnostic reset, SYNCLK rising edge clocks data into Check Bit, Syndrome, Error Type and Error Data registers. One of the syndrome registers has new data clocked in on every SYNCLK rising edge. WBEF O Write FIFO Empty Flag: when LOW, indicates that the write FIFO is empty. After a reset, the WBEF goes LOW. WBFF O Write FIFO Full Flag: when LOW, indicates that the write FIFO is full. After a reset, WBFF goes HIGH. RBEF O Read FIFO Empty Flag: when LOW, indicates that the read FIFO is empty. After a reset, the RBEF goes LOW. RBHF O Read FIFO Half-full Flag: when LOW, indicates that there are eight or more data words (in the 16deep configuration) or four or more data words (in the dual 8-deep configuration) in the read FIFO. The flag will return HIGH when less than eight (or four) data words are in the FIFO. RBFF O Read FIFO Full Flag: when LOW, indicates that the read FIFO is full. After a reset, RBFF goes HIGH. ERR O Error Flag: when ERR is LOW, a data error is indicated. The ERR is not latched internally. MERR O Multiple Error Flag: when MERR is LOW, a multiple data error is indicated. The MERR is not latched internally. PERR O Parity Error Flag: when LOW, indicates a parity error on the system data bus input. P P Power Supply Voltage. Ground. Clock Inputs Status Outputs Power Supply VCC GND 2617 tbl 02 11.7 5 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES DETAILED DESCRIPTION — (1, 2) 64-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART Generated Participating Data Bits Checkbits Parity CB0 Even (XOR) 0 1 2 3 X X X X X 4 CB1 Even (XOR) X CB2 Odd (XNOR) X CB3 Odd (XNOR) X CB4 Even (XOR) CB5 Even (XOR) CB6 Even (XOR) X X X X X X X X CB7 Even (XOR) X X X X X X X X X X X 6 7 X X X X 5 X X 8 9 X X X X X X X X X X 11 X 12 13 X X X X 10 15 X X X X 14 X X X X X X X X X X X X 2617 tbl 03 Generated Participating Data Bits Checkbits Parity CB0 Even (XOR) 16 17 18 19 X X X X X 20 CB1 Even (XOR) X CB2 Odd (XNOR) X CB3 Odd (XNOR) X CB4 Even (XOR) CB5 Even (XOR) X X X X X CB6 Even (XOR) X X X X X CB7 Even (XOR) X X X X X X X X 22 23 X X X X X 21 X 24 25 X X X X X X X X X X 26 27 X X 28 29 X 30 31 X X X X X X X X X X X X X X X X X X X 2617 tbl 04 Generated Participating Data Bits Checkbits Parity 32 CB0 Even (XOR) X CB1 Even (XOR) X CB2 Odd (XNOR) X CB3 Odd (XNOR) X CB4 Even (XOR) CB5 Even (XOR) CB6 Even (XOR) CB7 Even (XOR) 33 X 34 X X 36 38 39 X X X X X X X 37 X X X X X X 35 X X 40 X X X X X X X X X X 41 X 42 44 45 X 43 X X X X X X X X X X X 46 47 X X X X X X X X X X X X X X X X X X X 2617 tbl 05 Generated Participating Data Bits Checkbits Parity 48 CB0 Even (XOR) X 49 CB1 Even (XOR) X CB2 Odd (XNOR) X CB3 Odd (XNOR) X CB4 Even (XOR) CB5 Even (XOR) X X X X X CB6 Even (XOR) X X X X X CB7 Even (XOR) X 50 X X 52 54 55 X X X X X X X X X 53 X X X X 51 X X 56 X X X X X X X X X X 57 X 58 60 61 X 59 X X X X X X X X X X 62 63 X X X X X X X X X X NOTES: 2617 tbl 06 1. The table indicates the data bits participating in the checkbit generation. For example, checkbit CB0 is the Exclusive-OR function of the 64 data input bits marked with an X. 2. The checkbit is generated as either an XOR or an XNOR of the 64 data bits noted by an “X” in the table. 11.7 6 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES DETAILED DESCRIPTION — (1) 64-BIT SYNDROME DECODE TO BIT-IN-ERROR HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F S7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Syndrome S5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bits S4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 T T 62 C7 T T 46 T M M T HEX S3 S2 S1 S0 0 0 0 0 0 * C4 C5 T C6 1 0 0 0 1 C0 T T 14 T M M T T M M T M T T 30 2 0 0 1 0 C1 T T M T 34 56 T T 50 40 T M T T M 3 0 0 1 1 T 18 8 T M T T M M T T M T 2 24 T 4 0 1 0 0 C2 T T 15 T 35 57 T T 51 41 T M T T 31 5 0 1 0 1 T 19 9 T M T T 63 M T T 47 T 3 25 T 6 0 1 1 0 T 20 10 T M T T M M T T M T 4 26 T 7 0 1 1 1 M T T M T 36 58 T T 52 42 T M T T M 8 1 0 0 0 C3 T T M T 37 59 T T 53 43 T M T T M T 9 1 0 0 1 T 21 11 T M T T M M T T M T 5 27 A 1 0 1 0 T 22 12 T 33 T T M 49 T T M T 6 28 T B 1 0 1 1 17 T T M T 38 60 T T 54 44 T 1 T T M C 1 1 0 0 T 23 13 T M T T M M T T M T 7 29 T D 1 1 0 1 M T T M T 39 61 T T 55 45 T M T T M E 1 1 1 0 16 T T M T M M T T M M T 0 T T M F 1 1 1 1 T M M T 32 T T M 48 T T M T M M T NOTES: 2617 tbl 07 1. The table indicates the decoding of the eight syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was detected. The all-zero case indicates no error detected. * = No errors detected # = The number of the single data bit-in-error T = Two errors detected M = Three or more detected C# = The number of the single checkbits in error IDT49C466 OPERATION The EDC is involved in two types of operation — memory reads and memory writes. With the IDT49C466, both these can be accomplished by utilizing either of two possible data paths — one incorporating the FIFO and the other without the FIFO. These operations are treated separately below. Memory Write The involvement of the EDC in this type of operation is relatively minimal since it does not call for any error checking. It only generates the check bits associated with each 64-bit wide data word. The EDC can be in generate-detect or normal mode for this operation. When a write operation is performed, it must be ensured that the SD output buffer (enabled by SOE and BE0-7) is disabled so that no attempt is made to simultaneously transfer read data onto the System Data (SD) Bus. When the write FIFO (WFIFO) is bypassed (WBSEL LOW), data passes through the SD Latch In. To latch data, the SDILE signal should be pulled LOW. The special case of a partial word write or byte merge is discussed later. Here it is assumed that all 64 bits are being written. Consequently, BE0-7 must all be LOW. The data is fed to the SD Checkbit generator where appropriate checkbits are generated. Both system data and the generated checkbits can be latched by pulling the SDOLE signal HIGH. Asserting MOE enables the MD output buffer and data is output to the Memory Data (MD) bus. CBSEL (=1) or MOE(=0) need to be asserted to enable the CBSYN output buffer and output checkbits on CBSYN0-7. When the write FIFO is selected (WBSEL = 1), instead of asserting SDILE, WBEN is asserted and data is clocked into the write FIFO on the rising edge of SCLK. WBFF is asserted when the WFIFO is full and this inhibits further write attempts (see section on "Clock Skew" and "R/W FIFO Operation at Boundaries") to the WFIFO. When WBREN is asserted, data can be clocked out of the write FIFO on the rising edge of MCLK. WBEF is asserted when the WFIFO is empty and this inhibits further read attempts (see section on "Clock Skew") from the WFIFO. 11.7 7 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES BEn = 0 BEn = 1 MD LATCH OUT => Path A => Path B MD BUS 64 PATH B 64 PATH A 64 SD LATCH IN 64 BE0-7 BYTE MUX SD LATCH OUT 64 M U X 64 64 WBSEL WRITE BUFFER M U X 8 2617 drw 05 Figure 1. Byte Merge Memory Read During a memory read, data and the corresponding input checkbits are read from the MD bus and CBI0-7, respectively. The memory and checkbit data may both be latched as they come in (MD Latch In and MD Checkbit latch) by the MDILE signal. Memory data is sent to the MD checkbit generator (where checkbits corresponding to the input data are generated) and to the error correct circuitry. The generated checkbits are X-ORed with the input checkbits to produce the syndrome word. This is sent to the error correction circuitry which generates the corrected data (normal mode). The corrected data is output to the SD bus via either of two data paths. When RBSEL is LOW, data flows through MD Latch Out. Pulling MDOLE HIGH latches this data. The output buffer is enabled by asserting SOE (=0) and BE0-7 (=1). Corrected data can be written back to memory by enabling the MD output buffer. In order to ensure selection of the write back path (Path B in figure 1) at the byte mux, BEO-7 should be all 1's while WBSEL = 0. If WBSEL = 1, buffered BEO-7 from the output of the write FIFO controls the byte mux. If the read FIFO (RFIFO) is selected (RBSEL HIGH), data is clocked into the FIFO (Read_FIFO Write) when RBEN is LOW, on the rising edge of MCLK. RBFF is asserted when the RFIFO is full and this inhibits further write attempts to the RFIFO (see section on "Clock Skew" and "R/W FIFO operation at Boundaries"). Data is clocked out of the FIFO (Read_FIFO Read) when RBREN is LOW on the rising edge of SCLK. RBEF is asserted when the RFIFO is empty and this inhibits further read attempts (see section on "Clock Skew") from the RFIFO. Note: In case of multiple error SD should be ignored in correct mode Clock Skew A skew between the read and write clocks, as specified by tskew, is recommended. This specification is not a stringent one, in the manner of setup and hold times, but is important in preempting latencies at FIFO boundaries. For example – When a word is written to an empty FIFO, there is a finite delay before the FIFO is recognized as no longer being empty and hence allowing a read from the same FIFO. Similarly when a word is read from a full FIFO, there is a delay before a write can successfully be attempted. The tskew specification accounts for these cases. During cycles other than on full/empty FIFO boundaries, the clock skew is not required and the device functions correctly even when the reads and writes occur simultaneously. If the tskew specification is ignored and SCLK and MCLK were permanently tied together, there is an extra cycle latency in the cases mentioned above. Clock skew violation is illustrated in Figure 13. FIFO Write Latency The first data written to either of the (read or write) FIFOs, after the FIFO is reset, suffers a single clock latency. Data that is set-up with respect to the first clock is ignored and the data that is set-up with respect to the second clock edge after the reset, is stored as the first data in the FIFO (Refer to Figures 9 and 10). The empty-flag is deasserted after this second clock edge and 15 more data words (in a 16 deep configuration) can be written to the FIFO after this. The latency can be reduced or eliminated by providing a "dummy" or "set-up" clock edge before the actual write to the FIFO. The dummy write clock can be provided any time after reset and before the next buffer write operation takes place. The latency described here (shown in Figures 10 and 13) occurs only after a FIFO reset. In other cases where the FIFO becomes empty there is no latency. 11.7 8 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES R/W FIFO Operation At Boundaries In the 49C466 the write pointer is incremented on every FIFO write. Similarly the read pointer is incremented on every FIFO read. In most cases on a FIFO read, the last data read remains at the output of the FIFO, until the read pointer is further incremented. On the last (the write that fills the FIFO) FIFO write after the FIFO read, however, this last read data is overwritten by the 16th write following the empty condition and consequently the data at the FIFO output is liable to change. The situation is depicted in the diagram below. overwritten and the FIFO output changes from AA to the data just written, namely QQ. This operation needs to be taken into account in the design of the system. In case of a burst operation where FIFO data is output at a much slower rate than the rate at which data is input and the full flag is expected to inhibit further writes, the user cannot expect the FIFO output to remain static through the 16th write of the burst. If this is a requisite to the design, the FIFO output should be latched. In the case of the write FIFO this can be accomplished on-chip by latching the FIFO WP FIFO (empty) reset RP WP WRITE1 (data = AA) FIFO RP WP FIFO (empty) READ1 (data = AA) RP WP WRITE1 (data = BB) FIFO RP WRITE2 (data =CC) No READs (data = AA) WP FIFO No READs (data = AA) FIFO No READs (data = AA) RP WP WRITE15 (data = PP) RP WP WRITE16 (data = QQ) FIFO (full) No READs (data = QQ) Figure 2. R/W FIFO Operation The diagram in figure 2 progresses from the FIFO initialization(reset) through a sequence of write operations. After the first write, a read is executed which establishes the data at the FIFO output(AA). On the last write to the FIFO(the write that fills the FIFO), the location of the last read data is output in the SD output latch. For the read FIFO, the FIFO output must be latched externally to accomplish the same thing, since there is no latch on-chip following the FIFO. If this cannot be done and the situation described above is expected to occur in normal operation, the write must be inhibited one cycle before the FIFO becomes full. 11.7 9 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES Partial Word Write/Byte Merge MODE REGISTER CONFIGURATION Writing a word shorter than 64 bits to memory is treated 15 7 6 5 4 3 2 0 as a special case. The checkbits generated for a data word RWBD CLEAR EDCM0-2 UNUSED RMODE PSEL shorter than 64 bits and written to a particular memory location differ from the checkbits that would be generated by the entire EDCM2 EDCM1 EDCM0 OPERATION 64-bit data word at the same location. Hence, the byte merge ERROR-DATA OUTPUT MODE 0 0 0 operation requires reading of the contents of the memory 0 0 1 DIAGNOSTIC-OUTPUT MODE 0 1 0 GENERATE-DETECT MODE location to be written to, merging the byte/bytes being written 0 1 1 NORMAL MODE 1 0 0 (from SD side) with the other component bytes previously at CHECKBIT-INJECTION MODE that memory location (from MD side), generating a checkbit word for this composite word and writing both the composite RMODE OPERATION 0 NOP data word and the generated checkbits to memory. The BEn 1 READ MODE REGISTER ON SD BUS bits supplied by the user determine the bytes that come from SD and those that come from MD, as illustrated in Figure 1. RWBD OPERATION EDC Modes 0 DUAL FIFOS (8) 1 SINGLE FIFO (16) The IDT49C466 has 5 modes of operation. Refer to table below for a description of the modes. The Error Data Output mode is useful for memory initialCLEAR OPERATION CLEAR NOP 0 ization as described below. In Checkbit Injection mode, the CLEAR ALL DIAGNOSTIC REGISTERS 1 MD Checkbit Latch is loaded with data from the System Bus. This serves to verify the functioning of the EDC. Any discrepancy between the injected checkbits and generated checkbits PSEL OPERATION 0 EVEN PARITY should result in assertion of the ERR, MERR signals. 1 ODD PARITY These modes and certain other features such as clear, 2617drw 06 buffer configuration, etc., can be selected by appropriately loading the Mode Register. The Mode Register can be written to by asserting MEN. Then SD0-15 is clocked into the mode register on the rising edge of SCLK. OPERATING MODE DESCRIPTION Mode Description MODE 0 Error-Data Output Mode: This mode allows the uncorrected data captured from an error event by the Error-Data Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by setting the mode register "'clear"-bit. MODE 1 Diagnostic-Output Mode: In this mode, contents of latch and five internal registers are read by the system for diagnostic and error logging purposes. Internal data paths allow output from the CBI LATCH to be read directly by the system bus for diagnostic purposes. The contents of the internal diagnostic checkbit register, syndrome registers, error count register and error-type register are also output on the SD bus. MODE 2 Generate-Detect Mode: (Detect-Only) The EDC performs checkbit generation during a memory write, and performs error detection only during a memory read. MODE 3 Normal Mode: The EDC performs checkbit generation during memory writes and error detection and correction during memory reads. MODE 4 Checkbit-Injection Mode: In this mode, the checkbit latch is loaded with desired 8-bit data from the SD bus.This eight bit data passes through SD Latch in or write FIFO to the MD check bit latch. By inserting various checkbit values, correct functioning of the EDC can be verified “on-board”. The rest of the operation is similar to regular memory reads. The EDC compares the injected checkbits against the internally generated checkbits. Any discrepancy in the injected checkbits and the internally generated checkbits will cause the ERR / MERR to go LOW. 2617 tbl 08 Memory Initialization Memory initialization involves clearing all memory data locations and writing the corresponding checkbits (checkbits corresponding to all zero data = $0C) to checkbit memory. This can be done using the 49C466 to first create an "all-zero-data" source. This is done by setting the CLEAR bit in the mode register. This clears all diagnostic registers. Then this data can be written back to memory in the Error-Data output (Mode 0) mode. In order to wrap the all-zero data back to the MD bus, BE07 should be high and WBSEL =0. 11.7 10 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES CLEAR MODE BIT 0 MUX Diag. Regs. Error Data Regs. MUX SYNCLK BE0-7 BE0-7 MUX WFIFO 64 WBSEL Fig 3. Memory Initialization using Diagnostic Output/Error Data Output Mode DIAGNOSTIC OUTPUT DATA FORMAT TO SD BUS 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Error Checkbit Error Syndrome Checkbit Syndrome Type (from checkbit latch) Count (on 1st error) (on 1st error only) (on every error) (on 1st error only) * Bit #28 = 1 If "Error" condition Bit #29 = 1 If "Multiple bit Error" condition FROM DIAGNOSTIC REGISTERS 2617 drw 07 Diagnostics The diagnostic ability of the IDT49C466 rests on a set of 6 registers that provide error logging information. These include the checkbit register, error count register, error type register, 2 syndrome registers and the error data register. Data is clocked into each of these registers by SYNCLK. The error data register, checkbit register, error type register and one of the syndrome registers are reloaded only in the case of the first error after a clear. The other syndrome register and the error count register are reloaded on every error condition SYNCLK edge. The contents of the Error Data register can be read only in Error Data Output mode. The contents of the other diagnostic registers as well as the checkbit latch can be read in Diagnostic Output mode. Parity The IDT49C466 provides a parity check and generation facility. On a memory read the EDC generates parity bits for each data byte and outputs the parity byte on the parity bus, P0-7. During a memory write, parity is checked by comparing the parity bits input on P0-7 and the parity bits generated from the input data word. A discrepancy between these two causes the PERR flag to be asserted. In the case of partial word writes, the PERR flag is based on the parity bits Px and data bytes input on SD bus. 11.7 DIAG. REGISTER LOADED BY CONDITION OUTPUT CHECKBIT SYNCLK ↑ ONLY ON 1st ERROR SD8-15 SYNDROME (On 1st ERR) SYNCLK ↑ ONLY ON 1st ERROR SD16-23 ERR CNT SYNCLK ↑ ON EVERY ERROR (Up to 15 ERRORS) SD24-27 ERR TYPE SYNCLK ↑ ONLY ON 1st ERROR SD28-29 SYNDROME (On every ERROR) SYNCLK ↑ ON EVERY ERROR SD30-37 11 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating CAPACITANCE (TA = +25°C, f = 1.0 MHz) Com’l. Symbol Unit VCC Power Supply Voltage –0.5 to +7.0 V VTERM Terminal Voltage with Respect to Ground –0.5 to VCC + 0.5 V TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –55 to +125 °C IOUT DC Output Current 30 mA CIN Parameter(1) Input Typ. Unit VIN = 0V Conditions PQFP 5 pF VOUT = 0V PQFP 7 pF Capacitance COUT Output Capacitance NOTE: 1. This parameter is sampled and not 100% tested. 2617 tbl 10 NOTE: 2617 tbl 09 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Ratings for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE The following conditions apply unless otherwise specified: Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5% Symbol Test Conditions(1) Parameter Guaranteed Logic HIGH Level Min. Typ.(2) Max. Unit 2.0 — — V VIH Input HIGH Level VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V IIH Input HIGH Current VCC = Max., VIN = 2.7V — 0.1 5.0 µA IIL Input LOW Current VCC = Max., VIN = 0.5V IOZ Off State (Hi-Z) VCC = Max. Output Current — -0.1 –5.0 µA VO = 0V — -0.1 –10 µA VO = 3V — 0.1 10 (3) IOS Short Circuit Current VCC = Max. , VOUT= 0V VOH Output HIGH Voltage VCC = Min., –20 — –150 mA IOH = –2mA 2.4 3.6 — V IOL = 8mA — 0.3 0.5 V — 200 — mV VIN = VIH or VIL VOL Output LOW Voltage VCC = Min. VIN = VIH or VIL VH Input Hysteresis on input control lines NOTES: 1. For conditions shown as min. or max., use appropriate Vcc value. 2. Typical values are at VCC = 5.0V, +25°C ambient temperature. 3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. 2617 tbl 11 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Con't) The following conditions apply unless otherwise specified: Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5% Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit ICCQC Quiescent Power Supply Current VIN = VCC, or VIN = GND VCC = Max. — 3.0 15 mA ICCQT Quiescent Power Supply Current TTL Input Levels VIN = 3.4V VCC = Max. — 0.3 1 mA/ Input ICCD Dynamic Power Supply Current VIN = VCC, or VIN = GND — — 100 mA VCC = Max. f = 10MHz Correct Mode NOTES: 1. For conditions shown as Min. or Max., use appropriate Vcc value. 2. Typical values are at VCC = 5.0V, +25°C ambient temperature. 2617 tbl 12 11.7 12 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES AC PARAMETERS PROPAGATION DELAY TIMES Number Parameter From Input(1) GENERATE (WRITE) PARAMETERS Description To Output 49C466 Max. Com'l. 49C466A (50MHz) Max. Com'l. Unit Without Write FIFO: 1 tBC BEn CBSYN (chkbit) 20 15 ns 2 tBM BEn MDOUT 16 13 ns 3 tPPE Pxin PERR 10 8 ns 4 tSC SDin CBSYN (chkbit) 22 15 ns 5 tSM SDin MDout 22 15 ns 6 tSPE SDin PERR 16 12 ns With Write FIFO: 7 tMC MCLK (Lo-Hi) CBSYN (chkbit) 25 18 ns 8 tMMD MCLK (Lo-Hi) MDout 25 18 ns 9 tWBSEL WBSEL MDout 18 13 ns DETECT (READ) PARAMETERS Without Read FIFO: 10 tWYC SYNCLK (Lo-Hi) CBSYN (syndr) 16 12 ns 11 tME MDin ERR 20 12 ns 12 tMME MDin MERR 22 14 ns 13 tCE CBI ERR 13 9 ns 14 tCME CBI MERR 13 9 ns With Read FIFO: 15 tSSD SCLK (Lo-Hi) SDout 22 13 ns 16 tRBSEL RBSEL SDout 18 13 ns CORRECT (READ) PARAMETERS Without Read FIFO: 17 tCS CBI SDout 20 16 ns 18 tMP MDin Pxout 22 18 ns 19 tMS MDin SDout 22 16 ns SCLK (Lo-Hi) Pxout 22 15 ns With Read FIFO: 20 tSP 2617 tbl 13 NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa. 11.7 13 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES PROPAGATION DELAY TIMES FROM LATCH ENABLES Description 49C466 Max. 49C466A (50MHz) Max. Com'l. Com'l. Unit Parameter From Input(1) To Output 21 tMLE MDILE (Lo-Hi) ERR 16 13 ns 22 tMLME MDILE (Lo-Hi) MERR 18 15 ns 23 tMLP MDILE (Lo-Hi) Px 24 18 ns 24 tMLS MDILE (Lo-Hi) SDout 22 17 ns 25 tMOLS MDOLE (Hi-Lo) SDout 18 9 ns 26 tMOLP MDOLE (Hi-Lo) Px 18 11 ns 27 tSLC SDILE (Lo-Hi) CBSYN (chkbit) 20 15 ns 28 tSLM SDILE (Lo-Hi) MDout 20 12 ns Number 29 tSOLC SDOLE (Hi-Lo) CBSYN (chkbit) 12 8 ns 30 tSOLM SDOLE (Hi-Lo) MDout 15 8 ns 2617 tbl 14 NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa. R/W FIFO TIMES Number Parameter From Input(1) Description To Output RS1 (Hi-Lo) EF Min. 49C466A (50MHz) Com'l. Min. Max. Unit — 16 — 16 ns WCLK (Lo-Hi) (SCLK or MCLK) 10 — 9 — ns WCLK (Lo-Hi) (SCLK or MCLK) RCLK (Lo-Hi) (SCLK or MCLK) 10 — 9 — ns tEF R/WCLK (Lo-Hi) (SCLK or MCLK) EF — 15 — 12 ns 35 tFF R/WCLK (Lo-Hi) (SCLK or MCLK) FF — 15 — 12 ns 39 tHFF R/WCLK (Lo-Hi) HF — 15 — 12 ns 31 tRSF 32 tSKEW1 RCLK (Lo-Hi) (SCLK or MCLK) 33 tSKEW2 34 (Hi-Lo)/FF (Lo-Hi) 49C466 Com'l. Max. during SCLK LOW (SCLK or MCLK) NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa. 2617 tbl 15 11.7 14 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES BYTE MERGE TIMES Number Parameter 36 tSCM 37 tMDM 38 tRBM 49C466 Max. Com'l. 49C466A (50MHz) Max. Com'l. Unit MDout 25 18 ns MDout 18 14 ns MDout 23 15 ns Description (1) From Input To Output SCLK (Lo-Hi) MDOLE (Hi-Lo) RBSEL 2617 tbl 16 NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa. ENABLE AND DISABLE TIMES 49C466 Com'l. Description Number Parameter 40 tBESZx 41 tBESxZ 42 tBEPZx 43 tBEPxZ 44 tSEPZx 45 tSEPxZ 46 tCECZx 47 tCECxZ 48 tMEMZx 49 tMEMxZ 50 tSESZx 51 tSESxZ From Input(1) To Output BEN = SDout High Low BEN = High = Low Pout Low SOE Pout High MOE = Low CBSYN = Low = Low High Max. Min. Max. Unit * — 22 — 12 ns Hi-Z — 22 — 12 * — 15 — 10 Hi-Z — 15 — 8 * — 14 — 10 Hi-Z — 14 — 8 * — 12 — 10 — 10 — 8 MDout * — 22 — 10 Hi-Z — 18 — 9 SDout * — 16 — 10 Hi-Z — 20 — 9 High SOE Min. Hi-Z High MOE 49C466A (50MHz) Com'l. ns ns ns ns ns 2617 tbl 17 NOTES: 1. (High-Z) indicates high impedence. 2. * indicates delay to both edges. 11.7 15 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES SET-UP AND HOLD TIMES 49C466 Min. Description Parameter From Input(1) To Output 52 tCMLS CBI Set-up before MDILE = 53 tCMLH CBI Hold 54 tMMLS MDIN Set-up 55 tMMLH 56 57 Number 49C466A (50MHz) Min. Com'l. Com'l. Unit Hi-Lo 2 1.5 ns after MDILE = Hi-Lo 6 1.5 ns before MDILE = Hi-Lo 2 1.5 ns MDIN Hold after MDILE = Hi-Lo 6 1.5 ns tCMOLS CBI Set-up (Correct) before MDOLE = Lo-Hi 12 8 ns tCMOLH CBI Hold (Correct) after MDOLE = Lo-Hi 2 0 ns 58a tMMOLS MDIN Set-up (Detect) before MDOLE = Lo-Hi 10 5 ns 58b tMMOLS MDIN Set-up (Correct) before MDOLE = Lo-Hi 12 12 ns 59a tMMOLH MDIN Hold (Detect) after MDOLE = Lo-Hi 4 0 ns 59b tMMOLH MDIN Hold (Correct) after MDOLE = Lo-Hi 4 0 ns 60 tMMCS MDIN Set-up before MCLK = Lo-Hi 10 10 ns 61 tMMCH MDIN Hold after MCLK = Lo-Hi 4 0 ns 62 tSSLS SDIN Set-up before SDILE = Hi-Lo 5 1.5 ns 63 tSSLH SDIN Hold after SDILE = Hi-Lo 3 1.5 ns 64 tSSCS SDIN Set-up before SCLK Lo-Hi 2 1 ns 65 tSSCH SDIN Hold after SCLK Lo-Hi 6 2 ns 66 tSSOLS SDIN Set-up before SDOLE = Lo-Hi 8 6 ns 67 tSSOLH SDIN Hold after SDOLE = Lo-Hi 0 0 ns 68 tSCSD SCLK (Lo-Hi) before SDOLE = Lo-Hi 14 12 ns 69 tMCSD MCLK (Lo-Hi) before SDOLE = Lo-Hi 14 10 ns 70 tENS R/W FIFO Enable Set-up before S/M CLK = Lo-Hi 4 2 ns 71 tENH R/W FIFO Enable Hold after S/M CLK = Lo-Hi 4 2 ns 72 tRSS RS1 (Lo-Hi) R/WCLK = Lo-Hi 6 2 ns 73 tMODS Mode Data Set-up before SCLK = Lo-Hi 4 2 ns 74 tMODH Mode Data Hold after SCLK = Lo-Hi 4 2 ns 75 tMENS Mode Enable Set-up before SCLK = Lo-Hi 4 2 ns 76 tMENH Mode Enable Hold after SCLK = Lo-Hi 4 2 ns 77 tMSDS MDIN Set-up before SDOLE = Lo-Hi 22 20 ns 78 tMSDH MDIN Hold after SDOLE = Lo-Hi 0 0 ns 93 tBSCS BE Set-up before SCLK = Lo-Hi 1 1 ns 94 tBSCH BE Hold after SCLK = Lo-Hi 6 2 ns 4 2 ns before SYNCLK = Lo-Hi 10 8 ns DIAGNOSTIC SET-UP AND HOLD TIMES 79 tCSCS CBI Set-up 80 tMSCS MDIN Set-up 81 tMLSCS(2) MDILE = Lo-Hi Set-up 10 8 ns 82 tCSCH(2) CBI Hold 6 2 ns 83 (2) tMSCH MDIN Hold 6 2 ns 84 tMLSCH(2) MDILE = Lo-Hi Hold 6 2 ns After SYNCLK= Lo-Hi NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa. 2617 tbl 18 11.7 16 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES MINIMUM PULSE WIDTH 49C466 Min. Description Number Parameter From Input(1) 49C466A (50MHz) Min. Condition Com'l. Com'l. Unit 86 tRS Min. RS1 LOW time to reset buffers — 6 5.0 ns 87 tMLE Min. MDILE HIGH time to strobe new data MD, CBI = Valid 6 5.0 ns 88 tMDOLE Min. MDOLE LOW time to strobe new data — 6 5.0 ns to strobe new data 89 tSLE Min. SDILE HIGH time SD = Valid 6 5.0 ns 90 tCLK Min. S/MCLK HIGH time to clock in new data EN signal LOW 6 6.0 ns 91 tSYNCLK Min. SYNCLK HIGH time to clock in new data — 6 5.0 ns 92 tSDOLE Min. SDOLE LOW time — 6 5.0 to clock in new data ns 2617 tbl 19 11.7 17 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 1V/ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 15 2617 tbl 21 SD0-15 SDin (Mode) tMODH tMODS SCLK tMENH tMENS MEN 2617 drw 08 Figure 4. Mode Enable Timing WBSEL SOE write SCLK (WCLK) tSSCS tSSCH SD0-63 SDin tENH tENS WBEN tFF tFF WBFF tSKEW1 read MCLK (RCLK) 2617 drw 09 WBREN Figure 5. WFIFO Write Timing (Write Cycle) 11.7 18 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES read MCLK (RCLK) tENS ______ WBREN t EF _____ WBEF WBSEL tENH tEF t MCSD ______ SDOLE t MEMxZ ____ MOE t MMD t MEMZx MDout D1 MD0-63 t CECZx t MC CBSYN0-7 SCLK (WCLK) Valid Checkbits out t SKEW2 write 2617 drw 10 Figure 6. WFIFO Read and Checkbit Generate Timing (Write Cycle) 11.7 19 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES RBSEL ____ MOE t MEMxZ MD0-63 MDin MDout t MMLS CBI0-7 t MMLH Checkbits in t CMLS t CMLH MDILE t MMCS t MMCH write MCLK (WCLK) t ENH _____ RBEN t ENS tFF _____ RBFF t SKEW1 SCLK (RCLK) read 2617 drw 11 Figure 7. RFIFO Write Timing (Read Cycle) 11.7 20 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES read SCLK (RCLK) tENH tENS RBREN tEF RBEF write tEF MCLK (WCLK) tSKEW2 RBSEL tSSD SOE tSESZX BE0-7 tBESZX SDout (corrected data) SD0-63 tSEPZX tBEPZX P0-7 Parity out 2617 drw 12 Figure 8. RFIFO Read Timing (Read Cycle) 11.7 21 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES RS1 t RS t RSS WCLK (SCLK / MCLK) t RSF __ EF dummy write t RSF __ FF Figure 9. FIFO (WFIFO/RFIFO) Reset Timing DATA (SD/MD) dataxx data1 t SSCS dummy write t SSCH write WCLK (SCLK/MCLK) t ENS BUFFER _____ ENABLE _____ (WBEN/ RBEN) t RSF FIFO RESET (RS1) t EF BUFFER EMPTY FLAG _____ ____ (WBEF/ RBEF) 2617 drw 14 Figure 10. FIFO (WFIFO/RFIFO) Write Latency Timing 11.7 22 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES Valid BE0-7 BE0-7 SOE SD0-63 SDin Dy tSSCS tSSCH SDILE SDOLE external tristate MD0-63 MDout Dxy MDin Dx tMEMZX tMEMXZ MOE tMMOEmin1 MDILE tMMOLS tMMOLH MDOLE RBSEL WBSEL 2617 drw 15 Figure 11. Partial Word Write/Byte Merge Timing NOTE: 1. tMMOE is not a propagation delay. For partial word write operations tMMOE MIN= tMDM. 11.7 23 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES tBM Valid BE0-7 BE0-7 tSESXZ SOE SD Data xx dummy write tSSCS tSSCH write data read data SCLK MCLK WBEN tENS tENH tENS tENH WBREN tCSM = tMMD WBSEL tMMCS MD RBEN tMMCH Data yy tENS Merged Data xx+yy tENH tENS tENH RBREN RBSEL MOE tMEMXZ 2617 drw 25 Figure 12. Partial Word Write/Byte Merge Timing using both RFIFO and WFIFO 11.7 24 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES invalid data SD0-63 dummy write SDin 1 t SSCS SDin 2 t SSCH SCLK (WCLK) 1 2 t RSS RS1 tRSF t EF _____ WBEF MCLK (RCLK) 1 ignored (no skew) _____ WBREN 2617 drw 20 Figure 13. Write FIFO Write Timing with Clock Skew Violation MD0-63 MDin t MSCH t MSCS CB0-7 CBin t CSCS t CSCH MDILE t MLSCH t MLSCS SYNCLK t SYNCLK 2617 drw 21 Figure 14. Diagnostic Timing 11.7 25 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS SWITCH POSITION V CC 7.0V VIN Open Drain Disable Low Closed Open All Other Tests 2617 tbl 20 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. D.U.T. 50pF RT Switch Enable Low 500Ω VOUT Pulse Generator Test 500Ω CL 2617 drw 16 SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tH tSU tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH 2617 drw 18 2617 drw 17 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V CONTROL INPUT tPLZ tPZL VOH 1.5V VOL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH 2617 drw 26 SWITCH OPEN 1.5V 0V 3.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V 2617 drw 27 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 11.7 26 IDT49C466/A Flow-thruEDC ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT 49C466 Device Type X Speed XX Package X Process/ Temperature Range BLANK Commercial (0° C to +70° C) PQF Plastic Quad Flatpack Blank A Standard speed 50MHz speed 49C466 64-Bit Flow-thru EDC 2617 drw 19 11.7 27