IDT74ALVCH32373 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH32373 DESCRIPTION: FEATURES: The 32-bit transparent D-type latch is built using advanced dual metal CMOS technology. The high-speed, low-power latch is ideal for temporary storage of data. The device can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as four 8-bit latches, two 16bit latches, or one 32-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The ALVCH32373 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH32373 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor. • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in 96-ball LFBGA package DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for Heavy Loads APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 1OE A3 3OE 1LE A4 3LE D1 A5 D 3D1 J3 J4 J5 A2 H3 2LE H4 2D1 4OE 4LE E5 D 4D1 T3 T4 N5 D E2 C 3Q1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS 2OE J2 C 1Q1 C D 2Q1 N2 C TO SEVEN OTHER CHANNELS 4Q1 TO SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE FEBRUARY 2000 1 ©2000 Integrated Device Technology, Inc. DSC-4908/1 IDT74ALVCH32373 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION 6 1D2 1D4 1D6 1D8 2D2 2D4 2D6 2D7 3D2 3D4 3D6 3D8 4D2 4D4 4D6 4D7 5 1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D8 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D8 4 1LE GND VCC GND GND VCC GND 2LE 3LE GND VCC GND GND VCC GND 4LE 3 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 2 1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q8 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q8 1 1Q2 1Q4 1Q6 1Q8 2Q2 2Q4 2Q6 2Q7 3Q2 3Q4 3Q6 3Q8 4Q2 4Q4 4Q6 4Q7 A B C D E F G J K L N P R T H M LFBGA TOPVIEW 96 BALL LFBGA PACKAGE ATTRIBUTES 1.5mm Max. 1.4mm Nom. 1.3mm Min. 0.8mm 6 5 4 TOP VIEW 3 2 1 A B C D E F G H J K L M N P R T A B C D E F G H J K L M N P R T 1 2 3 5.5mm 4 5 6 13.5mm 2 IDT74ALVCH32373 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA IIK Continuous Clamp Current, VI < 0 or VI > VCC ±50 mA IOK Continuous Clamp Current, VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA INDUSTRIAL TEMPERATURE RANGE CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 5 7 pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF NOTE: 1. As applicable to the device type. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. FUNCTION TABLE (EACH 8-BIT SECTION)(1) PIN DESCRIPTION Pin Names xDx Inputs Description Data Inputs (1) Outputs xOE xAx xDx xQx xLE Latch Enable Inputs L H H H xQx 3-State Outputs L H L L xBx 3-State Output Enable Input (Active LOW) L L X Q(2) H X X Z NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 2. Output level of Q before the indicated steady-state conditions were established. 3 IDT74ALVCH32373 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA Min. Typ.(2) Max. Unit – 75 — — µA VI = 0.8V 75 — — VI = 1.7V – 45 — — 45 — — — ±500 NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V Bus-Hold Input Sustain Current VCC = 2.3V Bus-Hold Input Overdrive Current VCC = 3.6V VI = 2V IBHL IBHH IBHL IBHHO VI = 0.7V VI = 0 to 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 4 — µA µA IDT74ALVCH32373 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Min. Max. Unit VCC – 0.2 — V IOH = – 6mA 2 — IOH = – 12mA 1.7 — 2.2 — VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 38 44 pF 8 10 SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter tPLH Propagation Delay tPHL xDx to xQx tPLH Propagation Delay tPHL xLE to xQx tPZH Output Enable Time VCC = 2.7V VCC = 3.3V ± 0.3V Min. Max. Min. Max. Min. Max. Unit 1 4.5 — 4.3 1.1 3.6 ns 1 4.9 — 4.6 1 3.9 ns 1 6 — 5.7 1 4.7 ns 1.2 5.1 — 4.5 1.4 4.1 ns 1 — 1 — 1.1 — ns tPZL xOE to xQx tPHZ Output Disable Time tPLZ xOE to xQx tSU Setup Time, data before LE↓ tH Hold Time, data after LE↓ 1.5 — 1.7 — 1.4 — ns tW Pulse Duration, LE HIGH or LOW 3.3 — 3.3 — 3.3 — ns Output Skew(2) — — — — — 500 ps tSK(O) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2 Skew between any two outputs of the same package and switching in the same direction. 5 IDT74ALVCH32373 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF (1, 2) Pulse Generator VIN tPHL VIH VT 0V ALVC Link DISABLE ENABLE VIH VT 0V CONTROL INPUT GND tPZL D.U.T. OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω CL ALVC Link Test Circuit for All Outputs tPLH Propagation Delay VOUT RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION tPLZ VLOAD/2 VT VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT SWITCH POSITION Test Switch TIMING INPUT Open Drain Disable Low Enable Low VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open INPUT OUTPUT 1 tSK (x) VIH VT 0V tREM tSU tH Set-up, Hold, and Release Times VOH VT VOL tSK (x) LOW-HIGH-LOW PULSE OUTPUT 2 VT tW VOH VT VOL tPLH2 tH ALVC Link tPHL1 tPLH1 tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V HIGH-LOW-HIGH PULSE VT ALVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 ALVC Link Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 6 IDT74ALVCH32373 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION ALVC X IDT XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 BF Low-Profile Fine Pitch Ball Grid Array 373 32-Bit Transparent D-Type Latch with 3-State Outputs 32 32- Bit Bus Density, ±24mA H Bus-Hold 74 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: [email protected] (408) 654-6459