Webinar 2013: Improved signal integrity through impedance matched circuit boards Würth Elektronik Circuit Board Technology www.we-online.de Seite 1 01/10/2013 Agenda S Impedance and the circuit board I Material aspects and parameters G Impedance calculation N Layer stack-ups A Impedance and HDI (EMC) L High frequency and mid-performance materials www.we-online.de Seite 2 01/10/2013 PCB and impedance Impedance matching needed to keep the variations as small as possible! www.we-online.de Seite 3 01/10/2013 PCB and impedance PCB has an ohmic, capacitive and inductive proportion not an optimal tranfer medium between transmitter and receiver parameters that influence the signal on a PCB Length of conductor Raw material loss factor and permittivity Reflection due to the PTHs Impedance matching Crosstalk between conductors Noise interference from external sources (EMC shielding) www.we-online.de Seite 4 01/10/2013 Important parameters medium low strong strong Track width Copper thickness Layer distance Dielectric constant εr w+h = layouter / developer + PCB supplier t = galvanic process, base copper εr = base material t w h WE offers: advanced partnership! www.we-online.de Seite 5 01/10/2013 Material parameters Epsilon R FR4 Pre-preg 2116 FR4 Pre-preg 106 Thickness 90 – 110 µm εr = 3,6 – 3,8 Resin content ~50% Thickness 50 µm εr = 2,8 – 3,7 Resin content ~70% FR4 Pre-preg 1080 FR4 Pre-preg 7628 Thickness 60 - 70 µm εr = 3,2 – 3,7 Resin content ~60% Thickness 170 – 190 µm εr = 4,1 – 4,6 Resin content ~45% glass r ~6,1 / resin r ~3,2 Cores are laminated pre-pregs www.we-online.de Seite 6 01/10/2013 Epsilon R dielectric losses εr values in relation to the layer distance FR4 (lossy 1080 2x 1080 3x 1080 2116 2x 2116 3x 2116 Tg 135 3.2 3.5 3.6 3.6 3.9 4.7 Tg 150 hf 3.5 3.7 3.9 3.8 4.3 4.6 60 µm 100 µm 150 µm 250 µm 510 µm 710 µm Tg 135 3.2 3.5 3.6 3.6 3.9 4.7 Tg 150 hf 3.5 3.7 3.9 3.8 4.3 4.6 Pre-preg Cores Influence: - layer distance - frequency …. effective εr Influence on characteristic wave impedance www.we-online.de εr) Seite 7 01/10/2013 determination of εr effectiv Calculation of the Er value according to microsection picture with the help of Polar www.we-online.de H1 layer distance W1 lower track width W2 upper track width T1 copper thickness C1 solder resist on substrate (FR4) C2 solder resist on track CEr Er solder resist (supplier) Er dielectric constant Seite 8 01/10/2013 Layer distances Pre-preg 17 µm copper 35 µm copper 1 x 1080 65 µm 60 µm 2 x 1080 134 µm 128 µm Pre-preg 17 µm copper 35 µm copper 2 x 1080 128 µm 120 µm Pre-preg 17 µm copper 35 µm copper 1 x 1080 70 µm 68 µm 2 x 1080 140 µm 136 µm layout against plane or foil layout against layout plane against plane or foil www.we-online.de Seite 9 01/10/2013 Models layer / track configuration layer configuration: Embedded Microstrip Surface Microstrip Stripline line width line width Single Differential space track configuration: Gnd Coplanar Gnd www.we-online.de Seite 10 Which parameters have the biggest influence on the impedance of a track? www.we-online.de Seite 11 Parameters for impedance calculations C2 thickness solder resist over track [15 µm] S1 gap layout W2 upper track width (head) T1 copper thickness r dielectric constant solder resist [typ. 3,5] C1=C3 thickness solder resist over FR4 [42 µm] H1 layer distance Signal > Reference r W1 lower track width (foot) = layout dielectric constant FR4 www.we-online.de Seite 12 01/10/2013 Service “impedance defined stack-ups“ Information required: • type of stack-up: Standard <>HDI / via types • Number of layers • PCB – thickness • Copper thickness (especially inner layers) • layer order: position of signal layer plus corresponding reference layers • Number of signal layers and number of reference layers (Gnd, Power, VCC) • Impedance requirements (Single e.g. 50 Ohm) (Differential e.g. 90 und 100 Ohm) • Which track widths and gaps are preferred or possible? www.we-online.de Seite 13 01/10/2013 Impedance values for different pre-pregs Microstrip Outer Layers Pre-pregs: TG 150°, filled, halogen free Prepreg (each one ply) 1080 2113 2116 Layer spacing above plane layer 68 µm 92 µm 108 µm εr effective 3.5 εr effective 3.6 εr effective 3.8 109 µm 154 µm 179 µm (with εr 4.2: 94 µm) (with εr 4.2: 136 µm) (with εr 4.2: 165 µm) 100 µm 100 µm 100 µm 305 µm 137 µm 122 µm (pressed thickness , 1 oz copper L2) Track Width 50 Ω Single Impedance Track Width Track Separation 100 Ω diff. Impedance www.we-online.de Seite 14 01/10/2013 Example stack-up LAGENAUFBAU 12 - Lagen ML12 WE-Artikel Nr.: Kunde: CBT SH LAGENBEZEICHNUNG KUNDE AUFBAU BASISMaterial PREPREG ANZAHL/TYP CU WE TOP/VS S1 S3 Foil 17,5 µm 100 134 16 3.8 17,5 µm REF Impedanzberechnung: S1 Zdiff 100 Ohm @ 180 / 185 / 180 µm 100 16 3.6 17,5 µm S 87 S1 Zdiff 110 Ohm @ 170 / 270 / 170 µm 16 0,100 mm S 3.7 17,5 µm S2 175 33 1 x 2113 7 4.25 3.8 0,100 mm 6 [µm] 35 µm REF REF [µm] 33 2 x 1080 5 [εr] 35 µm REF 4 KUNDENFORDERUNG 16 0,100 mm 3 ENDDICKE 1) 1 x 1080 1 x 2116 2 Dielektrizitätskonstante 3.8 17,5 µm 100 S2 Zdiff 100 Ohm @ 94 / 186 / 94 µm 16 S2 Zdiff 108 Ohm @ 80 / 200 / 80 µm S3 Zo 75 Ohm @ 385 µm LB-Breite www.we-online.de Seite 15 01/10/2013 Impedance measuremant Polar Technology TDR (Polar Instruments) Transition TC -> PCB www.we-online.de Seite 16 01/10/2013 Impedance measurement test coupons with TC Single 23 mm 150 x 23 mm max. 6 structures TC‘s needed because: Differentiell 28 mm 150 x 28 mm max. 2 structures - 150 mm clear contacting of test adapters defined measuring length PCB‘s per production panel? Must be considered in the panelisation! In worst case maybe less PCBs on production panel! www.we-online.de Seite 17 01/10/2013 Impedance report contents • customer and job information • requirements for measurements • results of measurement • kleinst mögliche Toleranz +/- 10% impedance inseide tolerance: • PCB‘S + testreport will be sended out to customer www.we-online.de Seite 18 01/10/2013 Why did Würth Elektronik qualified the prepreg type 2113? www.we-online.de Seite 19 Signal Integrity HDI Discontinuities in possible wiring schemes Version 2: Microvia / Buried Via Version 1: PTH open ends antenna Blind and Buried Vias result in reduced discontinuities! www.we-online.de Seite 20 01/10/2013 Signal Integrity HDI Via in Pad Technology BGA area completely copper on outer layers (no tracks on the outer layers) signals on outer layers protected from external sources www.we-online.de Seite 21 Design example HDI GND on outer layers suggestion: do not use PTHs if you are already using buried vias Layer 1 GND Layer 2 Signal 1 Layer 3 Signal 2 Layer 4 GND Layer 1 GND Layer 2 Signal 1 Layer 3 Signal 2 Layer 4 GND www.we-online.de Seite 22 Design example HDI GND on outer layers S Wlow Wup layer 1 / 12 GND Prepreg T = 30 µm layer 2 / 11 Sig T = 16 µm layer 3 / 10 Sig H1 = 130 µm H2 = 81 µm H3 = 100 µm Core layer 4 / 9 GND Layer 2 / 11 Layer 3 / 10 Edge Coupled Offset strip line Edge Coupled Offset strip line Distance layer 1 / 12 GND 130 µm 211 µm Distance layer 4 / 9 GND 181 µm 100 µm Cu Thickness T 30 µm 16 µm Upper trace width Wup 82 µm 95 µm Lower trace width Wlow 100 µm 100 µm Separation S 214 µm 152 µm 3.8 / 3.5 / 3.8 3.8 / 3.5 / 3.8 100,0 Ω 100,0 Ω Type Substrate Dielectric εr Impedance www.we-online.de Seite 23 01/10/2013 Signal integrity HDI Example: INTEL Atom Pitch 0.593 mm diagonal Nearly without any restriction for impedances layer distances up to ca. 100 µm track width 90 µm up to pitch 0,6 mm For smaller pitches e.g. 0,4 mm and 0,5 mm µVia layer distances max. 60-70 µm www.we-online.de Seite 24 01/10/2013 summery: Design example HDI GND on outer layers using the outer layer as GND, gives: direct connection from the solder pad to the first and second inner layer by staggered mircovias optimal x – y routing avoids crosstalk between the lines a very good shielding avoiding EMC problems using 100 µm dielectric thickness for µVias, gives: Nearly no restrictions for impedance defined structures www.we-online.de Seite 25 Material costs of high frequency materials Comparative material costs (100 pieces) 1500% 1000% FR4 Standard 100% High Performance www.we-online.de Seite 26 Prepreg 100 µm Mid Performance 2 0% Kern 0.25 Mid Performance 1 500% Kern 0.10 FR4 low CTE 01/10/2013 Signal integrity forecast materials next steps Looking for project partners Qualification of mid-performance materials for production Materials for frequencies from 2,5 GHz - ca. 10 GHz or 15 GHz Lower material costs compared to high performance materials e.g. EMC Elite EM888, Isola FR408 HR, Megtron2, Megtron6 If needed please contact Würth Elektronik www.we-online.de Seite 27 01/10/2013 Dientleistungen Summary Signal Integrity: Higher transmission rates and frequencies increasingly more often require impedance matching. Due to this, we offer our service to you! For higher transmission rates it can often be the case that high frequency materials are necessary. In the future cost effective high frequency materials will also be necessary. We are well prepared! www.we-online.de Seite 28 01/10/2013 Understanding the connections is the secret to success! Many thanks for your interest! Philipp Reeb WÜRTH ELEKTRONIK GmbH & Co. KG Produkt Management Signalintegrität Circuit Board Technology T.: +49 7622 397 277 M.:+ E. [email protected] W. www.we-online.de 01/10/2013 www.we-online.de Page 29