ASIC Datasheet

2016
DLIN IP Core
LIN Bus Controller v. 1.03
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
IP CORE OVERVIEW
The DLIN is a soft core of the Local Interconnect
Network (LIN) bus controller, which provides single
master with multiple slaves communication concept. LIN is a serial communication protocol, primarily designed to be used in automotive application. Compared to CAN, LIN is slower, but is simpler and more cost effective. It’s used in applications where events happen in a “human time”. It is
ideal for communication in intelligent sensors
and actuators, where the bandwidth and versatility
of CAN is not required. The DLIN core provides
an interface
between
a
microprocessor
/microcontroller and a LIN bus. It can work as
a master or a slave LIN mode, depending on a work
mode
determined
by
the
microprocessor/microcontroller. The DLIN controller supports
transmission speed between 1kb/s and 20kb/s
and can transmit and receive LIN messages compatible to LIN 1.3. LIN 2.1 and the newest 2.2. The
status information reported includes the type and
condition of transfer operations being performed
by the DLIN, as well as a wide range of LIN error
conditions (overrun, framing, parity, timeout). The
DLIN includes programmable timer, which allows
detection of timeout and synchronization error.
The core is described at RTL level, allowing target
use in FPGA and ASIC technologies.
KEY FEATURES
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Conforms to LIN 1.3. LIN 2.1 and 2.2 specification
Automatic LIN Header handling
Automatic Re-synchronization
Data rate between 1Kbit/s and 20 Kbit/s
Master and Slave work modes
Time-out detection
Extended error detection
“Break-in-data” support
DELIVERABLES
♦
Source code:
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VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
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Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
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Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
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IP Core implementation support
3 months maintenance
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Delivery of the IP Core and documentation updates, minor
and major versions changes
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use.
There are two formats of the delivered IP Core:
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
SYMBOL
clk
rst
rxdii
DLIN
addr(2:0)
datai(7:0)
rd
wr
cs
txdo
irq
txdo
datao(7:0)
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
sending the response message, if it is addressed by
the master.
APPLICATIONS
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Automotive, industrial
Embedded communication systems
Baud Rate Generator – The DLIN contains a programmable 15 bit baud generator, which divides clock
input, by a divisor in the range between 1 and (2 15-1).
The output frequency of the baud generator is 32 x
the baud rate. The formula for the divisor is:
BLOCK DIAGRAM
The figure below shows the DLIN IP Core block
diagram.
addr(2:0)
datai(7:0)
datao(7:0)
rd
Host
Controller
Interface
Receiver
Control
&
Shift Reg.
BR 
Two registers, called divisor latches DLL and DLH,
store the divisor in the 15-bit binary format.
rxd
Transmitter Control & Shift Register – Performs
transmit management function, sends data by LIN bus
cs
Control
State Unit
Baud Rate
Generator
clk
rst
Receiver Control & Shift Register – is responsible for
receiving frame from LIN bus. Provides necessary
function for data reception, frame timing and error
checking.
Data Buffer – stores the receive or transmit data.
Data
Buffer
wr
f
32  Divisov
Transmitter
Control
&
Shift Reg.
txd
Interrupt
Controller
irq
Interrupt Controller – Interrupt controller works with
transmitter, receiver and control unit, to indicate
DLIN transmission events or errors. User can configure, which events may generates interrupt by enabled or disabled corresponding bits, in Interrupt Enable register. When interrupt is generated, host can
find information about reason by reading LIN Status
Register.
PERFORMANCE
PINS DESCRIPTION
PIN
clk
rst
cs
rd
wr
addr(2:0)
datai(7:0)
rxd
datao(7:0)
irq
txd
TYPE
input
input
input
input
input
input
input
input
output
output
output
DESCRIPTION
Global clock
Global reset
Chip select
Read data strobe
Write data strobe
Address bus
Host output data bus
LIN receive data
Input data bus
Interrupt signal
LIN transmit data
UNITS SUMMARY
Host Controller Interface – accepts inputs from the
system bus and generates control signals for other
DLIN functional blocks. Address bus ADDR(2:0), selects one of register to be read from/written into.
Active level of RD, WR and CS, can be configurable.
RD and WR are ignored, unless the DLIN has been
selected, by activating CS input.
The following table gives a survey about the Core
area and performance in ASIC devices, after Place
& Route (all key features included):
Device
0.18u speed
0.18u area
Area
[gates]
typical
3600
typical
3500
Core performance in ASIC devices
Speed grade
Fmax
[MHz]
350
100
CONTACT
Digital Core Design Headquarters:
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
tel.:
fax:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
Distributors:
Please check:
http://dcd.pl/sales
Control State Unit– is composed of two state machines, the master and the slave, which control master and slave tasks. The master task handles all bus
communication. It must initiate any slave response,
by sending out a synch break, a synch field and protected identifier field. Slave task is responsible for
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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