AN013 EN

Application Note
Wayne Chen
AN013 – May 2014
Component Design Approach and Layout Consideration of G-NAVPTM
In the design procedure, the component design and PCB layout greatly affect the performance of power supply.
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. Choosing appropriate
component make the power supply easy passing the specifications of Intel and AMD. This application note will
introduce the design approach of G-NAVPTM control topology, including on-time setting, switching frequency setting,
load-line setting, and DCR current sensing network setting. After that, the recommend PCB layout rules will be
showed to avoid noise interference to make the controller more robust.
1. Design Approach and Component Selection
The following design approach will use RT8884B as an example, which is designed to meet Intel VR12.5
specification. There are three main design procedures for RT8884B. The first step is initial settings for on-time and
switching frequency. The second step is the DCR current sensing network design. Finally, we have to complete the
load line design.
CPU Operation Condition
Input Voltage
No. of Phases
Load Line
Fast Slew Rate
Max Switching Frequency
Refer to Shark Bay VRTB power delivery guide, the recommended output filter is listed as follows :
Output Inductor : 360nH / 0.72m
Output Bulk Capacitor : 560F / 2.5V / 5m (max) 4 to 5pcs
Output Ceramic Capacitor : 22F / 0805 (18pcs max sites on top side)
© 2014 Richtek Technology Corporation
Application Note
1.1. Initial Setting for On-Time and Switching Frequency
Generally, higher switching frequency can achieve faster transient response, smaller steady-state output ripple, and
reduce power components' size and PCB space. However, the higher switching frequency will cause lower
conversion efficiency, poor noise immunity and thermal issue. Therefore, the maximum switching frequency needs
to be limited in a reasonable range to compromise between the pros and cons. After determining the maximum
switching frequency, the maximum on-time can be obtained with the relation between the duty and switching
ton(MAX) 
Where VDAC is the reference voltage, fsw,max is the maximum switching, and VIN(MAX) is the maximum input voltage.
The following shows the design example of RT8884B.
ton(MAX) 
1  1.85  514 (ns)
300k 12
Since RT8884B is one kind of constant on-time control, the patented CCRCOT (Constant Current Ripple COT)
technology can generate an adaptive on-time with input voltage and VID code to obtain a constant current ripple. So
that the output voltage ripple can be controlled nearly like a constant at different input and output voltage operation
range. Connect a resistor RTON between input voltage terminal and TONSET pin to set the on-time width.
Rton  C  2.2
 VDAC < 2.2V 
R  C  VDAC
ton  ton
 VDAC  2.2V 
ton 
where C = 18.2pF
Where VIN is the maximum input voltage, VDAC is the reference voltage, and ton is the on-time which is determined
in the above equation. The following shows the design example of RT8884B.
514n 
Rton 18.2p  2.2
 Rton  130kΩ
12  1.85
© 2014 Richtek Technology Corporation
Application Note
1.2. DCR Current Sensing Network Design
Figure 1. The whole current loop structure of RT8884B.
Figure 2. The corresponding output waveforms with different τCx and τLx time constant.
Figure 1 shows the whole current loop structure of RT8884B. The design of DCR current sensing network plays an
important role in both ACLL performance and DCLL accuracy. For different time constant design, the ACLL behavior
can be separated into three conditions as follows. Moreover, Figure 2 shows the corresponding output waveforms
with different τCx and τLx time constant.
If τCx matches τLx, an expected load transient waveform can be designed.
If τCx is larger than τLx, output voltage has a sluggish droop as load increasing.
If τCx is smaller than τLx, output voltage will sag to reduce the margin of undershoot specification.
TCX  R X  C X
Where DCRx is the equivalent resistance of the inductor, Lx is the inductance of the inductor, and Rx and Cx is the
DCR current sensing network parameters.
Usually, the τCx time constant will be designed equal or slightly larger than the τLx time constant to prevent the
overshoot and undershoot to have more margin to pass the specification. Notice that, the Cx may attenuate because
of the bias voltage, temperature, or frequency…etc. As design the DCR current sensing network, the attenuate
effect on the Cx is needed to be considered.
© 2014 Richtek Technology Corporation
Application Note
Since the copper wire of inductor has a positive temperature coefficient, DCR value is increased linearly with an
increase of load current. Therefore, for achieving a better DCLL performance, a thermal compensation network with
NTC thermister (REQ) is necessary to compensate the positive temperature coefficient of inductor DCR. The
detailed thermal compensation can refer to design tool for specific product.
1.3. Load-Line Design
In the G-NAVPTM topology, the load line design depends on the ratio of current loop gain and voltage loop gain. The
detailed load line equation will be shown in the corresponding IC datasheet. The following is using RT8884B as an
1  DCR  R
Where DCR (25°C) = 0.72m, RCS = 680 is the current sensing resistor, REQ (25°C) is designed for the thermal
compensation, and the R2 / R1 is the compensator AV gain. Through this equation, the load line can be changed
simply by adjusting the compensator AV gain. Following Intel VR12.5 specification, a 1.5 (m) load line is required;
therefore, the R2 / R1 AV gain can be decided. The design example of RT8884B is shown as below.
1  DCR  R
1  0.72m  16.8k
 2 680
 R2  59.2k
© 2014 Richtek Technology Corporation
Application Note
2. Layout Consideration
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount all of the power components on the top side of the board with
their ground terminals flushed against one another. Follow these guidelines for optimum PC board layout :
2.1. Power Stage Layout Guideline
Keep the high current paths short, especially at the ground terminals.
Keep the power traces and load connections short. This is essential for high efficiency.
When trade-off between the charging path and the discharging path of the inductor, it's preferable to let the
inductor charging path longer than the discharging path.
2.2. IC Sensing Pad and RGND Layout Guideline
Place the current sense component (CX, RCSX, RX) close to the controller to avoid the current sensing signals
be coupled by the noise.
Side Pad
Side Pad
Strong Signal
Figure 3. Placement of current sensing components.
ISENxP and ISENxN connections for current limit and voltage positioning must be made using Kelvin sense
connections to guarantee current sense accuracy. The traces from the inductor are run directly from the
inductor pad and not from the connection plane of the inductor.
Figure 4. The inductor pad for current sensing traces.
The PCB trace from the inductor sense nodes should be paralleled back to the controller. Typically these
traces are run underneath the inductors on the bottom layer of PCB. If these traces run on an inner layer, there
must be a ground plane above the current sense traces as a shielding from the top layer.
Route high speed switching nodes (PWM, UG, LG, phase, etc…) away from sensitive analog areas (COMP,
FB, ISENxP, ISENxN, etc...).
Users need to connect exposed pad to the ground plane through low impedance path. The use of at least 5
vias to connect to ground planes in PCB internal layers is recommended.
© 2014 Richtek Technology Corporation
Application Note
3. Experimental Result and Conclusion
3.1. Experimental Result
Figure 5 shows the RT8884B EVB sample, which is applied in VR12.5 applications and can supports 4/3/2/1 phase.
The measured load line curve and efficiency is showed in Figure 6. From the measured result, the G-NAVPTM
topology can provide an accurate load line and still maintain the higher efficiency. Figure 7 shows a large step and a
small step load transient waveform, which indicates fast and stable transient performance and proper AVP control.
Figure 5. The EVB sample of RT8884B.
Table 1. EVB testing condition
1.8V @PS0
Phase Number
360nH / 0.72m
OSCON : 470F / 4.5m*4
MLCC : 22F*19
© 2014 Richtek Technology Corporation
Application Note
Figure 6. Measured load-line and efficiency from RT8884B.
(CH3: Loading current (900mv/Div) ; CH4: Output voltage (30mV/Div))
(a) Large step (1A-61A) ACLL @300Hz
(b) Small step (50A-60A) ACLL @300Hz
Figure 7. Measured ACLL result from RT8884B.
3.2. Conclusion
The design of the system components usually needs to compromise between lots of restrictions to gain the most
benefit on the efficiency and performance. Besides, the particular layout skills are used to minimize the effect of the
parasitic component and avoid the high speed switching noise coupling. This application note shows the general
design approach of G-NAVPTM control topology and the PCB layout rules. Following the rules mentioned above,
users can use Richtek’s controller IC without any inconvenience.
© 2014 Richtek Technology Corporation
Application Note
4. Reference
[1] Richtek, RT8884B datasheet.
[2] Intel document, “Shark Bay Ultrabook™ Platform Power Delivery”
[3] Intel document, “Shark Bay Mobile Platform Power Delivery”
[4] Intel document, “Shark Bay Desktop and Denlow-WS Platform”
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Hsinchu, Taiwan, R.O.C.
Tel: 886-3-5526789
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© 2014 Richtek Technology Corporation
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