2016 D8255 IP Core Programmable Peripheral Interface v. 1.00 ○ COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. IP CORE OVERVIEW The D8255 is a programmable I/O device, designed to be used with all Intel and most other microprocessors. It provides 24 I/O pins, which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation: ● Mode 0 - Basic Input/Output. This functional configuration provides simple input and output operations, for each of the three ports. No „handshaking'' is required, data is simply written to or read from a specified port. Mode 0 Basic Functional Definitions: ○ ○ ○ ● MODE 1 - Strobed Input/Output. This functional configuration provides the means for transferring I/O data to or from a specified port, in conjunction with strobes or „handshaking'' signals. In mode 1, Port A and Port B use the lines on Port C, to generate or accept these „handshaking'' signals. Mode 1 Basic functional Definitions: ○ ○ ○ ○ ● Two 8-bit ports and two 4-bit ports. Any port can be input or output. 16 different Input/output configurations are possible in this Mode Two Groups (Group A and Group B). Each group contains one 8-bit data port and one 4bit control/data port. The 8-bit data port can be either input or output. Both inputs and outputs are latched. The 4-bit port is used for control and status of the 8-bit data port. MODE 2 - Strobed Bidirectional Bus I/O. This functional configuration provides the means for communicating with a peripheral device or structure on a single 8-bit bus, for both transmitting and receiving data (bidirectional bus I/O). „Handshaking'' signals are provided to maintain proper bus flow discipline, in a similar manner to MODE 1. Interrupt generation and enable/disable functions are also available. MODE 2 Basic Functional Definitions: ○ ○ Used in Group A only. One 8-bit, bi-directional bus port (Port A) and a 5bit control port (Port C). The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port (Port A) Functional configuration of the D8255 is programmed by the system software, so that normally no external logic is necessary to interface peripheral devices or structures. The control word register can be both written and read, as shown in the address decode table in the pin descriptions. KEY FEATURES ● ● Compatible with 8255 industry standard 24 I/O lines individually programmed in 2 groups of 12: ○ ○ ● 3 major modes of operation ○ ○ ○ ● ● ● ● ● Group A - Port A and upper half of Port C Group B – Port B and lower half of Port C Mode 0 – Basic input/output Mode 1 – Strobed Input/output Mode 2 – Bi-directional Bus Control Word Read-Back Capability Direct Bit Set/Reset Capability Interrupt control functions No internal three state busses Fully synthesizable technology independent source code. DESIGN FEATURES ♦ ONE GLOBAL SYSTEM CLOCK ♦ SYNCHRONOUS RESET ♦ ALL ASYNCHRONOUS INPUT SIGNALS ARE SYNCHRONIZED BEFORE INTERNAL USE ♦ ALL LATCHES IMPLEMENTED IN ORIGINAL 8255 DEVICES ARE REPLACED BY EQUIVALENT FLIP-FLOP REGISTERS, WITH THE SAME FUNCTIONALITY APPLICATIONS ● ● ● ● Embedded microprocessor boards Interface to the printer I/O component to interface peripheral equipment to the microcomputer system bus PINS DESCRIPTION PIN clk reset cs rd we a[1:0] portai[7:0] portbi[7:0] portci[7:0] datai[7:0] datao[7:0] portao[7:0] portbo[7:0] portco[7:0] TYPE input input input input input input input input input input output output output output DESCRIPTION Global clock Global reset Chip select Processor read strobe Processor write strobe Processor address lines Port A input Port B input Port C input Data bus (input) Data bus (output) Port A output Port B output Port C output 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. Port A - One 8-bit data output latch/buffer and one 8-bit input latch buffer. Both „pull-up'' and “pulldown” bus hold devices present on Port A. SYMBOL datai(7:0) datao (7:0) portai(7:0) portbi(7:0) portao (7:0) portbo (7:0) portci(7:0) portco (7:0) Port B - One 8-bit data input/output latch/buffer. Only „pull-up'' bus hold devices are present on Port B. Port C - One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under mode control. Each 4-bit port contains a 4-bit latch and can be used for the control signal outputs and status signal inputs, in conjunction with ports A and B. Only „pull-up'' bus hold devices are present on Port C. a(1:0) we rd cs rst clk BLOCK DIAGRAM clk rst datai datao a1 a0 rd wr cs Group A Control Data Bus Buffer & Control Logic Group B Control Group A Port A portai[7:0] Group A Port C Upper portci[7:4] Group B Port C Lower Group B Port B portao[7:0] portco[7:4] Group A and Group B Controls - The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a control word to the D8255. The control word contains information, such as “mode”', “bit set”, “bit reset”, etc., that initializes the functional configuration of the D8255. Each of the Control blocks (Group A and Group B), accepts “commands” from the Read/Write Control Logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports. Group A - Port A and upper half of Port C Group B - Port B and lower half of Port C portci[3:0] portco[3:0] portbi[7:0] portbo[7:0] The control word register can be both written and read. The figure on the right shows the control word format, for both Read and Write operations. When the control word is read, bit D7 will always be logic “1”, as this implies control word mode information. DELIVERABLES UNITS SUMMARY Data Bus Buffer – The Data Bus Buffer is used to interface the D8255, to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions, by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic - The control logic block manages all of the internal and external transfers of both, Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both, A and B Control Groups. Ports A, B, and C - The D8255 contains three 8-bit ports. All can be configured in a wide variety of functional characteristics by the system software, but each has its own special features or “personality”, for further enhancement of the power and flexibility of the D8255. ♦ Source code: ● VHDL Source Code or/and ● VERILOG Source Code or/and ● Encrypted, or plain text EDIF ♦ VHDL & VERILOG test bench environment ● Active-HDL automatic simulation macros ● ModelSim automatic simulation macros ● Tests with reference responses ♦ Technical documentation ● Installation notes ● HDL core specification ● Datasheet ♦ ♦ ♦ Synthesis scripts Example application Technical support ● IP Core implementation support ● 3 months maintenance ● ● Delivery of the IP Core and documentation up dates, minor and major versions changes Phone & email support 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. LICENSING Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code called HDL Source code FPGA EDIF/NGO/NGD/QXP/VQM called Netlist PERFORMANCE The following table gives a survey about the Core area and performance in ASIC devices (all key features included): Technology Optimization 0.25 typical 0.25 typical area speed Gates Fmax Core performance in ASIC devices CONTACT Digital Core Design Headquarters: Wroclawska 94, 41-902 Bytom, POLAND e-mail: tel.: fax: firstname.lastname@example.org 0048 32 282 82 66 0048 32 282 74 37 Distributors: Please check: http://dcd.pl/sales 3 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.