2016 D8254 IP Core Programmable Interval Timer v. 1.08 COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. IP CORE OVERVIEW The D8254 is a programmable interval timer/counter, binary compatible with the 82C54 industry standard. The D8254 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control. The D8254 can be used as: Real time clock Even counter Digital one-shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller KEY FEATURES ♦ ♦ Three independent 16-bit counters Six programmable Counter modes ○ ○ ○ ○ ○ ○ ♦ ♦ ♦ ♦ Interrupt on terminal count Hardware retriggerable One-Shot Rate Generator Square wave mode Software triggered strobe Hardware triggered strobe Binary or BCD counting Status Read Back Command Simple interface allows easy connection to microcontrollers Fully synthesizable, static design with no internal tri-states DELIVERABLES ♦ Source code: ● ● ● ♦ VHDL & VERILOG test bench environment ● ● ● ♦ VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation ● ● Installation notes HDL core specification ● ♦ ♦ ♦ Datasheet Synthesis scripts Example application Technical support ● ● IP Core implementation support 3 months maintenance ● Delivery of the IP Core and documentation updates, minor and major versions changes Phone & email support ● PINS DESCRIPTION PIN rst datai(7:0) ddr(1:0) cs rd wr clk0 gate0 clk1 gate1 clk2 gate2 atao(7:0) out0 out1 out2 TYPE input input input input input input input input input input input input output output output output DESCRIPTION Global reset Processor data bus (input) Processor address lines Chip select Processor read strobe Processor write strobe Clock input for Counter 0 Gate input for Counter 0 Clock input for Counter 1 Gate input for Counter 1 Clock input for Counter 2 Gate input for Counter 2 Processor data bus (output) Output of Counter 0 Output of Counter 1 Output of Counter 2 BLOCK DIAGRAM rst addr(1:0) wr rd cs datai(7:0) datao(7:0) Read/Write Logic Counter 0 clk0 gate0 out0 Data Bus Buffer Counter 1 clk1 gate1 out1 Control Word Register Counter 2 clk1 gate1 out1 SYMBOL rst datai(7:0) datao(7:0) addr(1:0) cs rd wr clk0 gate0 out0 clk1 gate1 out1 clk2 gate2 out2 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. LICENSING COUNTERS BLOCK DIAGRAM Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. All three Counters (0, 1, 2) are functionally identical and fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes: ● ● ● ● ● ● Interrupt on terminal count Hardware retriggerable One-Shot Rate Generator Square wave mode Software triggered strobe Hardware triggered strobe The internal block diagram of a single counter is shown in the figure below. datai(7:0) There are two formats of the delivered IP Core: clkn gaten VHDL or Verilog RTL synthesizable source code FPGA EDIF/NGO/NGD/QXP/VQM (Netlist) Control Unit Ctrl. Word Register UNITS SUMMARY Read Write Logic - The Read/Write Logic accepts inputs from the system bus and generates control signals, for the other functional blocks of the D8254. ADDR(1:0) select one of the three counters or the Control Word Register, to be read from/written into. A “low'' on the RD input tells the D8254, that the CPU is reading one of the counters. A “low'' on the WR input tells the D8254 that the CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by CS; RD and WR are ignored, unless the 82C54 has been selected by holding CS low. The WR and CLK signals should be synchronous. This is accomplished by using a CLK input signal to the D8254 counters, which is a derivative of the system clock source. Another technique is, to externally synchronize the WR and CLK input signals. This is done by gating WR with CLK. Data Bus Buffer 8-bit buffer is used to interface the D8254 to the system bus. Control Word - The Control Word Register is selected by the Read/Write Logic when ADDR(1:0) = 11. If the CPU does a write operation to the D8254, the data is stored in the Control Word Register and is interpreted, as a Control Word used to define the operation of the Counters. Status Register, Status Latch – Status register, which contains actual mode declaration and value of output signal. Latched in Status Latch, after receiving ReadBack Command with STATUS Bit = 0. Control Unit – Controls read/write operation and decrementing of CE CR M, CR L – Input data registers. When a new count is written to counter, the count is written in the CR and later transferred to CE OL L, OL M – Output data registers. Latched when the suitable Counter Latch Command is sent to the D8254 CRM Satus Register Status Latch outn CRL CE OLM OLL datao(7:0) The central element of each Counter is the CE module - Counting Element – 16 bit pre-settable synchronous down BIN/BCD counter. PERFORMANCE The following table gives a survey about the Core area and performance in ALTERA® devices after Place & Route: Device CYCLONE CYCLONE 2 STRATIX STRATIX 2 STRATIXGX MERCURY EXCALIBUR APEX II APEX20KC APEX20KE APEX20K Speed grade Logic Cells -6 -6 -5 -3 -5 -5 -1 -7 -7 -1 -1V Core performance in ALTERA® devices Fmax 150 MHz 166 MHz 181 MHz 238 MHz 185 MHz 135 MHz 108 MHz 140 MHz 129 MHz 105 MHz 88 MHz CONTACT Digital Core Design Headquarters: Wroclawska 94, 41-902 Bytom, POLAND e-mail: tel.: fax: [email protected] 0048 32 282 82 66 0048 32 282 74 37 Distributors: Please check: http://dcd.pl/sales 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.