IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH16721 DESCRIPTION: FEATURES: This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the ALVCH16721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The highimpedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVCH16721 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16721 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor. • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in SSOP and TSSOP packages DRIVE FEATURES: • High Output Drivers: ±24mA • Low switching noise APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM OE CLK CLKEN 1 56 29 CE C1 D1 55 2 Q1 1D TO 19 OTH ER C HAN NELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2004 1 © 2004 Integrated Device Technology, Inc. DSC-4747/2 IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VTERM(2) Max Unit 1 Terminal Voltage with Respect to GND –0.5 to +4.6 V OE 56 CLK VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V Q1 2 55 D1 TSTG Storage Temperature –65 to +150 °C Q2 3 54 D2 IOUT DC Output Current –50 to +50 mA GND 4 53 GND IIK ±50 mA Q3 5 52 D3 Continuous Clamp Current, VI < 0 or VI > VCC Q4 6 51 D4 IOK Continuous Clamp Current, VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA VCC 7 50 VCC Q5 8 49 D5 Q6 9 48 D6 Q7 10 47 D7 GND 11 46 GND Q8 12 45 D8 Q9 13 44 D9 Q10 14 43 D10 Q11 15 42 D11 Q12 16 41 D12 Q13 17 40 D13 GND 18 39 GND Q14 19 38 D14 Q15 20 37 D15 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. CIN Input Capacitance VIN = 0V 5 7 pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF NOTE: 1. As applicable to the device type. Q16 21 36 D16 VCC 22 35 VCC Q17 23 34 D17 Pin Names Q18 24 33 D18 OE 3–State Output Enable Input (Active LOW) Dx Data Inputs(1) PIN DESCRIPTION Description GND 25 32 GND Q19 26 31 D19 Qx 3-State Outputs CLK Clock Input Q20 27 30 D20 NC 28 29 CLKEN Unit CLKEN NC Clock Enable Input (Active LOW) No Internal Connection NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. SSOP/ TSSOP TOP VIEW FUNCTION TABLE (EACH FLIP-FLOP)(1) Inputs Output OE CLKEN CLK Dx Qx L H X X Q0(2) L L ↑ H H L L L L ↑ L or H L X L Q0(2) H X X X Z NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance ↑ = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established. 2 IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA Min. Typ.(2) Max. Unit – 75 — — µA VI = 0.8V 75 — — VI = 1.7V – 45 — — VI = 0.7V 45 — — — ±500 NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Bus-Hold Input Sustain Current Test Conditions VCC = 3V VI = 2V IBHL IBHH Bus-Hold Input Sustain Current VCC = 2.3V IBHL IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 — µA µA IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 55 59 pF 46 49 SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter fMAX VCC = 2.7V VCC = 3.3V ± 0.3V Min. Max. Min. Max. Min. Max. Unit 150 — 150 — 150 — MHz 1 5.6 1 5.1 1 4.3 ns 1 6.1 1 5.8 1 4.8 ns 1 5.5 1 4.7 1 4.4 ns tPLH Propagation Delay tPHL CLK to Qx tPZH Output Enable Time tPZL OE to Qx tPHZ Output Disable Time tPLZ OE to Qx tSU Set-up Time, data before CLK↑ tSU Set-up Time, CLKEN before CLK↑ tH Hold Time, data after CLK↑ 0 — 0 — 0 — ns tH Hold Time, CLKEN after CLK↑ 0 — 0 — 0 — ns tW Pulse Width, CLK HIGH or LOW 3.3 — 3.3 — 3.3 — ns Output Skew(2) — — — — — 500 ps tSK(O) 4 — 3.6 — 3.1 — ns 3.4 — 3.1 — 2.7 — ns NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF VIN tPHL VIH VT 0V ALVC Link DISABLE ENABLE CONTROL INPUT GND tPZL D.U.T. OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω RT tPLH Propagation Delay VOUT Pulse Generator tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC (1, 2) VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION CL ALVC Link Test Circuit for All Outputs tPLZ VLOAD/2 VT VIH VT 0V VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT SWITCH POSITION Test VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open INPUT OUTPUT 1 tPLH1 VIH VT 0V tSU tH Set-up, Hold, and Release Times VOH VT VOL tSK (x) LOW-HIGH-LOW PULSE OUTPUT 2 VT tW VOH VT VOL tPLH2 tREM ALVC Link tPHL1 tSK (x) tH TIMING INPUT Switch Open Drain Disable Low Enable Low tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V HIGH-LOW-HIGH PULSE VT ALVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 ALVC Link Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT ALVC X XX Bus-Hold Temp. Range XXX Family XXX XX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA Shrink Small Outline Package Thin Shrink Small Outline Package 721 20-Bit Flip-Flop with 3-State Outputs 16 Double-Density, ±24mA H Bus-Hold 74 –40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459