IDT72V01 IDT72V02 IDT72V03 IDT72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9 Integrated Device Technology, Inc. FEATURES: • 3.3V family uses 70% less power than the 5 Volt 7201/ 02/03/04 family • 512 x 9 organization (72V01) • 1024 x 9 organization (72V02) • 2048 x 9 organization (72V03) • 4096 X 9 organization (72V04) • Functionally compatible with 720x family • 25 ns access time • Asynchronous and simultaneous read and write • Fully expandable by both word depth and/or bit width • Status Flags: Empty, Half-Full, Full • Auto-retransmit capability • Available in 32-pin PLCC and 28-pin SOIC Package (to be determined) • Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications 7202/7203/7204. These devices load and empty data on a first-in/first-out basis. They use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write ( ) and Read ( ) pins. The devices have a maximum data access time as fast as 25 ns. The devices utilize a 9-bit wide data array to allow for control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. They also feature a Retransmit ( ) capability that allows for reset of the read pointer to its initial position when is pulsed low to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. The IDT72V01/72V02/72V03/72V04 is fabricated using IDT’s high-speed CMOS technology. It has been designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. W R RT RT DESCRIPTION: The IDT72V01/72V02/72V03/72V04 are dual-port FIFO memories that operate at a power supply voltage (Vcc) between 3.0V and 3.6V. Their architecture, functional operation and pin assignments are identical to those of the IDT7201/ FUNCTIONAL BLOCK DIAGRAM DATA INPUTS (D 0 –D 8) W WRITE CONTROL RAM ARRAY 512x 9 1024 x 9 2048 x 9 4096 x 9 WRITE POINTER R READ CONTROL THREESTATE BUFFERS DATA OUTPUTS (Q 0 –Q 8 ) FLAG LOGIC EF FF EXPANSION LOGIC XI READ POINTER RS RESET LOGIC FL/RT XO/HF 2679 drw 01 CEMOS is a trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co. COMMERCIAL TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. DECEMBER 1996 For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.08 DSC-3033/6 1 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 1 2 28 27 VCC D4 D3 D2 3 4 26 25 D5 D6 D1 D0 5 6 24 23 XI FF D7 FL/RT 7 8 22 21 RS EF XO/HF D5 5 29 D6 D1 6 28 D7 D0 7 27 NC XI FF 8 9 10 26 25 FL/RT RS EF XO/HF Q0 Q1 J32-1 24 11 23 Q7 NC 12 22 Q2 13 11 12 18 17 Q6 Q5 Q8 GND 13 14 16 15 Q4 Q7 Q6 21 14 15 16 17 18 19 20 Q3 R 2679 drw 02a Q5 Q2 Q3 Q4 20 19 R 9 10 GND NC Q0 Q1 2679 drw 02b PLCC TOP VIEW SMALL OUTLINE PACKAGE TO BE DETERMINED RECOMMENDED DC OPERATING CONDITIONS (1) ABSOLUTE MAXIMUM RATINGS Symbol Rating VTERM Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature IOUT DC Output Current NC 4 3 2 1 32 31 30 D2 Q8 W D8 D3 D8 INDEX W PIN CONFIGURATIONS VCC D4 COMMERCIAL TEMPERATURE RANGE Com’l. –0.5 to +7.0 Symbol Unit V °C 0 to +70 °C –55 to +125 –55 to +125 °C 50 mA Rating Min. Typ. Max. Unit 3.0 3.3 3.6 V VCC Supply Voltage GND Supply Voltage 0 0 0 V VIH(1) Input High Voltage 2.0 — VCC+0.5 V VIL(2) Input Low Voltage — — 0.8 V NOTE: 1. VIH = 2.6V for XI input (commercial). 2. 1.5V undershoots are allowed for 10ns once per cycle. 2679 tbl 03 NOTE: 2679 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. CAPACITANCE (TA = +25°C, f = 1.0 MHz) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Condition VIN = 0V VOUT = 0V NOTE: 1. This parameter is sampled and not 100% tested. Max. 8 8 Unit pF pF 2679 tbl 02 5.08 2 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3 V ± 0.3V, TA = 0°C to +70°C) IDT72V01/72V02/ 72V03/72V04 Commercial tA = 25 ns Symbol Parameter Min. Typ. IDT72V01/72V02/ 72V03/72V04 Commercial tA = 35 ns Max. Min. Typ. Max. Unit –1 — 1 –1 — 1 µA ILO(2) Output Leakage Current –10 — 10 –10 — 10 µA VOH Output Logic “1” Voltage IOH = –2mA 2.4 — — 2.4 — — V VOL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 V ICC1(3,4) Active Power Supply Current — 35 50 — 35 50 mA ICC2(3) Standby Current (R=W=RS=FL/RT=VIH) — 5 8 — 5 8 mA ICC3(L)(3) Power Down Current (All Input = VCC - 0.2V) — — 0.3 — — 0.3 mA ILI (1) Input Leakage Current (Any Input) NOTES: 1. Measurements with 0.4 ≤ VIN ≤ VCC. 2. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 3. ICC measurements are made with outputs open (only capacitive loading). 4. Tested at f = 20MHz. 5.08 2679 tbl 05 3 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3V±0.3V, TA = 0°C to +70°C) Symbol Parameter Commercial Commercial 72V01L25/72V02L25 72V01L35/72V02L35 72V03L25/72V04L25 72V03L35/72V04L35 Min. Min. Max. Unit Max. fS Shift Frequency — 28.5 — 22.2 MHz tRC Read Cycle Time 35 — 45 — ns tA Access Time — 25 — 35 ns tRR Read Recovery Time 10 — 10 — ns 25 — 35 — ns tRPW (2) Read Pulse Width (3) tRLZ Read Pulse Low to Data Bus at Low Z 5 — 5 — ns tWLZ Write Pulse High to Data Bus at Low Z(3,4) 5 — 10 — ns tDV Data Valid from Read Pulse High 5 — 5 — ns (3) tRHZ Read Pulse High to Data Bus at High Z — 18 — 20 ns tWC Write Cycle Time 35 — 45 — ns 25 — 35 — ns (2) tWPW Write Pulse Width tWR Write Recovery Time 10 — 10 — ns tDS Data Set-up Time 15 — 18 — ns tDH Data Hold Time 0 — 0 — ns tRSC Reset Cycle Time 35 — 45 — ns tRS Reset Pulse Width(2) 25 — 35 — ns tRSS Reset Set-up Time(3) 25 — 35 — ns tRSR Reset Recovery Time 10 — 10 — ns tRTC Retransmit Cycle Time 35 — 45 — ns tRT Retransmit Pulse Width(2) 25 — 35 — ns (3) tRTS Retransmit Set-up Time 25 — 35 — ns tRTR Retransmit Recovery Time 10 — 10 — ns tEFL Reset to Empty Flag Low — 35 — 45 ns tHFH,FFH Reset to Half-Full and Full Flag High — 35 — 45 ns tRTF Retransmit Low to Flags Valid — 35 — 45 ns tREF Read Low to Empty Flag Low — 25 — 30 ns tRFF Read High to Full Flag High — 25 — 30 ns tRPE Read Pulse Width after EF High 25 — 35 — ns tWEF Write High to Empty Flag High — 25 — 30 ns tWFF Write Low to Full Flag Low — 25 — 30 ns tWHF Write Low to Half-Full Flag Low — 35 — 45 ns tRHF Read High to Half-Full Flag High — 35 — 45 ns tWPF Write Pulse Width after FF High 25 — 35 — ns tXOL Read/Write to XO Low — 25 — 35 ns tXOH Read/Write to XO High — 25 — 35 ns tXI XI Pulse Width(2) XI Recovery Time XI Set-up Time 25 — 35 — ns tXIR tXIS NOTES: 1. Timings referenced as in AC Test Conditions. 2. Pulse widths less than minimum value are not allowed. 10 — 10 — ns 10 — 10 — ns 2679 tbl 06 3. Values guaranteed by design, not currently tested. 4. Only applies to read data flow-through mode. 5.08 4 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 5.0V GND to 3.0V 5ns 1.5V 1.5V See Figure 1 1.1K TO OUTPUT PIN 680Ω 2679 tbl 08 30pF* 2679 drw 03 or equivalent circuit Figure 1. Output Load * Includes scope and jig capacitances. SIGNAL DESCRIPTIONS INPUTS: DATA IN (D0 – D8) Data inputs for 9-bit wide data. CONTROLS: RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a low state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the high state during the window shown in Figure 2, (i.e., tRSS before the rising edge of RS) and should not change until tRSR after the rising edge of RS. Half-Full Flag (HF) will be reset to high after Reset (RS). WRITE ENABLE (W) A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go high after tRFF, allowing a valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full. READ ENABLE (R) A read cycle is initiated on the falling edge of the Read Enable (R) provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes high, the Data Outputs (Q0 – Q8) will return to a high impedance condition until the next Read operation. When all data has been read from the FIFO, the Empty Flag (EF) will go low, allowing the “final” read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go high after tWEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes in R will not affect the FIFO when it is empty. FIRST LOAD/RETRANSMIT (FL/RT) This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the restransmit input. The Single Device Mode is initiated by grounding the Expansion In (XI). The IDT72V01/72V02/72V03/72V04 can be made to retransmit data when the Retransmit Enable control (RT) input is pulsed low. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the high state during retransmit. This feature is useful when less than 512/1024/2048/4096 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers. EXPANSION IN (XI) This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode. OUTPUTS: FULL FLAG (FF) The Full Flag (FF) will go low, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go 5.08 5 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 low after 512/1024/2048/4096 writes to the IDT72V01/72V02/ 72V03/72V04. COMMERCIAL TEMPERATURE RANGE indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by using rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. EMPTY FLAG (EF) The Empty Flag (EF) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an t RSC t RS RS t RSR t RSS W t RSS R t EFL EF t HFH , t FFH HF, FF 2679 drw 04 Figure 2. Reset NOTES: 1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC. 2. W and R = VIH around the rising edge of RS. t RC t RPW t RR tA tA R t RLZ t DV Q0 – Q8 t RHZ DATA OUT VALID DATA OUT VALID t WC t WPW t WR W t DS D0 – D8 t DH DATA IN VALID DATA IN VALID 2679 drw 05 Figure 3. Asynchronous Write and Read Operation 5.08 6 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 LAST WRITE IGNORED WRITE COMMERCIAL TEMPERATURE RANGE FIRST READ ADDITIONAL READS FIRST WRITE R W t WFF t RFF FF 2679 drw 06 Figure 4. Full Flag From Last Write to First Read LAST READ IGNORED READ FIRST WRITE ADDITIONAL WRITES FIRST READ W R t REF t WEF EF tA DATA OUT VALID VALID 2679 drw 07 Figure 5. Empty Flag From Last Read to First Write t RTC t RT RT t RTS t RTR W,R RTF FLAG VALID HF, EF, FF 2679 drw 08 Figure 6. Retransmit 5.08 7 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE W t WEF EF t RPE R 2679 drw 09 Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse R t RFF FF t WPF W 2679 drw 10 Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse W t RHF R HALF-FULL OR LESS t WHF MORE THAN HALF-FULL HF HALF-FULL OR LESS 2678 drw 11 Figure 9. Half-Full Flag Timing WRITE TO LAST PHYSICAL LOCATION READ FROM LAST PHYSICAL LOCATION W R t XOL t XOH t XOL t XOH XO 2679 drw 12 Figure 10. Expansion Out 5.08 8 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 t XI COMMERCIAL TEMPERATURE RANGE t XIR XI t XIS W WRITE TO FIRST PHYSICAL LOCATION t XIS R Figure 11. Expansion In OPERATING MODES: Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where R is used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. Single Device Mode A single IDT72V01/72V02/72V03/72V04 may be used when the application requirements are for 512/1024/2048/ 4096 words or less. IDT72V01/72V02/72V03/72V04 is in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 12). Depth Expansion The IDT72V01/72V02/72V03/72V04 can easily be adapted to applications when the requirements are for greater than 512/1,024/2,048/4,096 words. Figure 14 demonstrates Depth Expansion using three IDT72V01/72V02/72V03/72V04s. Any depth can be attained by adding additional IDT72V01/72V02/ 72V03/72V04s. The IDT72V01/72V02/72V03/72V04 operates in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the high state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. See Figure 14. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all must be set to generate the correct composite FF or EF). See Figure 14. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. READ FROM FIRST PHYSICAL LOCATION 2679 drw 13 Figure 13 demonstrates an 18-bit word width by using two IDT72V01/72V02/72V03/72V04s. Any word width can be attained by adding additional IDT72V01/72V02/72V03/72V04s (Figure 13). Bidirectional Operation Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT72V01/72V02/72V03/72V04s as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode. Data Flow-Through Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising edge of W, called the first write edge, and it remains on the bus until the R line is raised from low-to-high, after which the bus would go into a three-state mode after tRHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the W line being low causes it to be asserted again in anticipation of a new data word. On the rising edge of W, the new word is loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer. Compound Expansion The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15). For additional information, refer to Tech Note 9: Cascading FIFOs or FIFO Modules. USAGE MODES: Width Expansion Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from any one device. 5.08 9 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE (HF) (HALF–FULL FLAG) WRITE (W) READ (R) 9 IDT 72V01 72V02 72V03 72V04 DATA IN (D) FULL FLAG (FF) RESET (RS ) 9 DATA OUT (Q) EMPTY FLAG (EF) RETRANSMIT (RT ) EXPANSION IN (XI ) 2679 drw 14 Figure 12. Block Diagram of Single 1024 x 9 FIFO HF HF 18 9 9 DATA IN (D) IDT WRITE (W) IDT 72V01 72V02 72V03 72V04 FULL FLAG (FF) RESET (RS ) READ (R) 72V01 72V02 72V03 72V04 EMPTY FLAG (EF) RETRANSMIT (RT ) 9 9 XI XI 18 DATA OUT (Q) 2679 drw 15 Figure 13. Block Diagram of 1024 x 18 FIFO Memory Used in Width Expansion Mode TABLE I—RESET AND RETRANSMIT Single Device Configuration/Width Expansion Mode RS Inputs RT XI Reset Retransmit 0 1 X 0 0 0 Internal Status Read Pointer Write Pointer Location Zero Location Zero Location Zero Unchanged Read/Write 1 1 0 Increment(1) Mode Increment(1) Outputs EF FF HF 0 X 1 X 1 X X X X NOTE: 1. Pointer will increment if flag is High. 2679 tbl 09 TABLE II—RESET AND FIRST LOAD TRUTH TABLE Depth Expansion/Compound Expansion Mode Inputs Mode Reset First Device Reset All Other Devices Read/Write RS FL XI 0 0 0 1 (1) (1) 1 X (1) NOTE: 1. XI is connected to XO of previous device. See Figure 14. XI = Expansion Input, HF = Half-Full Flag Output Internal Status Read Pointer Write Pointer Location Zero Location Zero Location Zero Location Zero X X Outputs EF FF 0 0 1 1 X X 2679 tbl 10 RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output, 5.08 10 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE XO W D FF 9 9 R EF IDT 72V01 72V02 72V03 72V04 Q 9 FL VCC XI XO FF FULL 9 EF IDT 72V01 72V02 72V03 72V04 EMPTY FL XI XO FF 9 RS EF IDT 72V01 72V02 72V03 72V04 FL XI 2679 drw 16 Figure 14. Block Diagram of 3072 x 9 FIFO Memory (Depth Expansion) ••• Q 0 –Q 8 R, W, RS IDT 72V01/72V02 72V03/72V04 DEPTH EXPANSION BLOCK Q 9 –Q 17 IDT 72V01/72V02 72V03/72V04 DEPTH EXPANSION BLOCK D 0 -D 8 Q (N-8) -Q N ••• D 9 -D 17 IDT 72V01/72V02 72V03/72V04 DEPTH EXPANSION BLOCK D (N-8) -D N ••• D 0 –D N 2679 drw 17 Figure 15. Compound FIFO Expansion NOTES: 1. For depth expansion block see section on Depth Expansion and Figure 14. 2. For Flag detection see section on Width Expansion and Figure 13. 5.08 11 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 WA FFA COMMERCIAL TEMPERATURE RANGE RB EF B HF B IDT 72V01 IDT 72V02 7201A 72V03 72V04 DA 0-8 Q B 0-8 SYSTEM A SYSTEM B Q A 0-8 RA HF A EF A D B 0-8 IDT 72V01 72V02 72V03 72V04 WB FF B 2679 drw 18 Figure 16. Bidirectional FIFO Mode DATA IN W t RPE R EF t REF t WEF t WLZ tA DATA OUT DATA OUT VALID 2679 drw 19 Figure 17. Read Data Flow-Through Mode R t WPF W t RFF FF t WFF DATA IN VALID t DS DATA IN t DH tA DATA OUT DATA OUT VALID 2679 drw 20 Figure 18. Write Data Flow-Through Mode 5.08 12 IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type L Power XXX Speed X Package X Process/ Temperature Range 5.08 Blank Commercial (0°C to + 70°C) J Plastic Leaded Chip Carrier 25 35 Comercial Only Access Time (t A )Speed in Nanoseconds L Low Power 72V01 72V02 72V03 72V04 512 x 9 FIFO 1024 x 9 FIFO 2048 x 9 FIFO 4096 x 9 FIFO 2679 drw 21 13