Integrated Device Technology, Inc. BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For the Pentium Processor FEATURES: • 16K x 15 Configuration – 12 TAG Bits – 3 Separate I/O Status Bits (Valid, Dirty, Write Through) • Match output uses Valid bit to qualify MATCH output • High-Speed Address-to-Match comparison times – 8/9/10/12ns over commercial temperature range • BRDY circuitry included inside the Cache-Tag for highest speed operation • Asynchronous Read/Match operation with Synchronous Write and Reset operation • Separate WE for the TAG bits and the Status bits • Separate OE for the TAG bits, the Status bits, and BRDY • Synchronous RESET pin for invalidation of all Tag entries • Dual Chip selects for easy depth expansion with no performance degredation • I/O pins both 5V TTL and 3.3V LVTTL compatible with VCCQ pins • PWRDN pin to place device in low-power mode • Packaged in a 80-pin Thin Plastic Quad Flat Pack (TQFP) DESCRIPTION: The IDT71215 is a 245,760-bit Cache Tag StaticRAM, organized 16K x 15 and designed to support the Pentium and other Intel processors at bus speeds up to 66MHz. There are twelve common I/O TAG bits, with the remaining three bits used as status bits. A 12-bit comparator is on-chip to allow fast comparison of the twelve stored TAG bits and the current Tag input data. An active HIGH MATCH output is generated when these two groups of data are the same for a given address. IDT71215 This high-speed MATCH signal, with tADM as fast as 8ns, provides the fastest possible enabling of secondary cache accesses. The three separate I/O status bits (VLD, DTY, and WT) can be configured for either dedicated or generic functionality, depending on the SFUNC input pin. With SFUNC LOW, the status bits are defined and used internally by the device, allowing easier determination of the validity and use of the given Tag data. SFUNC HIGH releases the defined internal status bit usage and control, allowing the user to configure the status bit information to fit his system needs. A synchronous RESET pin, when held LOW at a rising clock edge, will reset all status bits in the array for easy invalidation of all Tag addresses. The IDT71215 also provides the option for Burst Ready (BRDY) generation within the cache tag itself, based upon MATCH, VLD bit, WT bit, and external inputs provided by the user. This can significantly simplify cache controller logic and minimize cache decision time. Match and Read operations are both asynchronous in order to provide the fastest access times possible, while Write operations are synchronous for ease of system timing. The IDT71215 uses a 5V power supply on Vcc with separate VCCQ pins provided for the outputs to offer compliance with both 5.0V TTL and 3.3V LVTTL Logic levels. The PWRDN pin offers a low-power standby mode to reduce power consumption by 90%, providing significant system power savings. The IDT71215 is fabricated using IDT's high-performance, high-reliability BiCMOS technology and is offered in a spacesaving 80-pin Thin Plastic Quad Flat Pack (TQFP) package. PIN DESCRIPTIONS A0 – A13 CS1, CS2 WET WES OET OES RESET PWRDN Input CLK System Clock Input Chip Selects Input BRDYH Input Write Enable - Tag Bits Input BRDY Force High BRDY Output Enable Additional BRDY Input Address Inputs Write Enable - Status Bits Input Output Enable - Tag Bits Input BRDYOE BRDYIN BRDY Output Enable - Status Bits Input TAG0 – TAG11 Tag Data Input/Outputs Status Bit Reset Input VLDOUT / S1OUT Valid Bit / S1 Bit Output Output Powerdown Mode Control Pin Input DTYOUT / S2OUT Dirty Bit / S2 Bit Output Output SFUNC Status Bit Function Control Pin Input WTOUT / S3OUT Write Through Bit / S3 Bit Output Output W/R Write/Read Input from Processor Input MATCH VCC Match +5V Power Output Pwr VCCQ VSS Output Buffer Power Ground QPwr Gnd VLDIN / S1IN Valid Bit / S1 Bit Input Input DTYIN / S2IN Dirty Bit / S2 Bit Input Input WTIN / S3IN Write Through Bit / S3 Bit Input Input Input Input Burst Ready Output I/O 3075 tbl 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Pentium is a trademark of Intel Corporation COMMERCIAL TEMPERATURE RANGE AUGUST 1996 1996 Integrated Device Technology, Inc. DSC-3075/3 14.3 1 IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE VSS 1 TAG9 VCCQ TAG10 VSS TAG11 OET BRDYOE OES CLK RESET VSS VCC WET WES CS1 CS2 VSS PWRDN VCC VLDIN / S1IN PIN CONFIGURATION 80 VSS VSS VSS VSS VSS VSS TAG8 DTYIN / S2IN TAG7 WTIN / S3IN TAG6 A0 VLDOUT / S1OUT A1 VCCQ A2 VSS VCC BRDY PN80-1 VSS MATCH A3 VSS A4 VCCQ A5 WTOUT / S3OUT A6 TAG5 A7 TAG4 TAG3 TAG2 VCCQ TAG1 TAG0 VSS DTYOUT / S2 OUT A13 A12 A11 A10 A9 BRDYIN BRDYH W/R VSS VCC VSS VSS VSS VSS VSS VSS SFUNC NC VSS A8 VSS 3075 drw 01 TQFP TOP VIEW 14.3 2 IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM ADDR (0:13) 0 Reg 1 16K x 12 MEMORY 16K x 3 MEMORY TAG BITS STATUS BITS CS1 CS2 Data in Register Reg Data in Register SA SA VLD/S1IN DTY/S2IN WT/S3IN TAG (0:11) OET VLD/S1OUT DTY/S2OUT WRITE (pos) PULSE GENERATOR WT/S3OUT WET Reg WES CLK OES RESET (neg) PULSE GENERATOR COMPARE RESET PWRDN SFUNC MATCH W/R BRDYH BRDY BRDYIN Reg BRDYOE 14.3 3 IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE TRUTH TABLES CHIP SELECT, RESET, AND POWER-DOWN FUNCTIONS(1, 2) CS1 CS2 RESET PWRDN CLK WET WES BRDYOE TAG VLDOUT DTYOUT WTOUT MATCH OPERATION POWER BRDY CHIP SELECT FUNCTION H X X H X X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Deselected Active X L X H X X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Deselected Active L H X H X X X X – – – – – – Selected Active RESET FUNCTION L H L H ↑ H H L Hi-Z L(3) L(3) L(3) L(3) H Reset Status Active L H L H ↑ H H H Hi-Z L(3) L(3) L(3) L(3) Hi-Z Reset Status Active H X L H ↑ H H X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Reset Status Active X L L H ↑ H H X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Reset Status Active X X L H ↑ L X X – – – – – – Not Allowed – X X L H ↑ X L X – – – – – – Not Allowed – H X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Power-down POWER-DOWN FUNCTION X X X L X H NOTES: 1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated. 2. OET, OES, W/R, BRDYH, BRDYIN and SFUNC are "X" for this table. 3. OES is LOW. Standby 3075 tbl 02 READ AND WRITE FUNCTIONS(1, 2) OET OES WET WES CLK W/R TAG VLDIN DTYIN WTIN VLDOUT DTYOUT WTOUT MATCH OPERATION READ FUNCTION L X H X X X DOUT – – – – – – DOUT Read TAG I/O X L X X X X – – – – DOUT DOUT DOUT DOUT Read Status Bits H X X X X X Hi-Z – – – – – – DOUT TAG I/O Disable X H X X X X – – – – Hi-Z Hi-Z Hi-Z DOUT Status Disabled WRITE FUNCTION H X L X ↑ X DIN – – – DOUT DOUT DOUT L Write TAG I/O L X L X ↑ X – – – – – – – – Not Allowed X L X L ↑ X – DIN DIN DIN L Write Status Bits X H X L ↑ X – DIN DIN DIN L Write Status Bits DOUT(3) DOUT(3) DOUT(3) Hi-Z Hi-Z Hi-Z NOTES: 3075 tbl 03 1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated. 2. This table applies when CS1 is LOW and CS2, RESET, and PWRDN are HIGH. BRDYOE, BRDYH, BRDYIN and SFUNC are "X" for this table. 3. DOUT in this case is the same as DIN; that is, the input data is written through to the outputs during the write operation. 14.3 4 IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE TRUTH TABLES (CONT.) MATCH FUNCTION(1, 2, 3) CS1 CS2 SFUNC OET WET WES TAG VLD(4) DTY(4) WT(4) MATCH OPERATION H X X X X X Hi-Z – – – Hi-Z Deselected X L X X X X Hi-Z – – – Hi-Z Deselected L H X X X X – – – – DOUT Selected L H X L H X DOUT – – – L Read Tag I/O L H X H L X DIN – – – L Write Tag I/O L H X X X L – DIN DIN DIN L Write Status Bits L H L H H H TAGIN L – – L Invalid Data - Dedicated Status Bits L H L H H H TAGIN H – – M Match - Dedicated Status Bits L H H H H H TAGIN X – – M Match - Generic Status Bits NOTES: 1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated. 2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address. 3. PWRDN and RESET are HIGH for this table. W/R, BRDYH, BRDYOE, BRDYIN, OES, and CLK are "X". 4. This column represents the stored memory cell data for the given Status bit at the selected address. BRDY 3075 tbl 04 FUNCTION(1, 2, 3, 5) (6) BRDYOE BRDYIN OET WET WES BRDYH W/R SFUNC VLD(4) DTY(4) WT(4) TAG MATCH BRDY OPERATION H X X X X X X X X – X – – Hi-Z L L X X X X X X X – X – X L Ext BRDY Input (7) L H L X X X X X X – X DOUT L H Read TAG L H X L X X X X X – X DIN L H Write TAG L H X X L X X X DIN DIN DIN – L H Write Status L H X X X H X X X – X – X H Force BRDY HIGH L H X X X X X L L – X – L H Invalid TAG L H X X X X H L X – H – X H Write Through L H H H H L X L H – L TAGIN M M Compare L H H H H L L L H – X TAGIN M M Compare L H H H H L X L H – X TAGIN M M Compare L H H H H L X H X – X TAGIN M M Compare BRDY Disabled NOTES: 3075 tbl 05 1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated. 2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address. 3. PWRDN and RESET are HIGH for this table. CLK and OES are "X". 4. This column represents the stored memory cell data for the given Status bit at the selected address. 5. CS1 is LOW, CS2 is HIGH for this table. 6. BRDYIN is a synchronous input; thus the inputs noted in the table must be applied during a rising CLK edge. 7. BRDYIN will be a factor in determining the BRDY output in all cases except when BRDYH is HIGH and there is a valid MATCH. In that case, BRDY will be LOW(Valid). 14.3 5 IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED DC OPERATING CONDITIONS Symbol Symbol Rating Value Unit VTERM Terminal Voltage with Respect to GND –0.5 to +7.0(2) V V TA Operating Temperature –0 to +70 °C 3.6 V TBIAS Temperature Under Bias –65 to +135 °C –65 to +150 °C Parameter Min. Typ. Max. Unit Supply Voltage 4.75 5.0 5.25 V VCCQ 5V Output Buffers 4.75 5.0 5.25 VCCQ 3.3V Output Buffers 3.0 3.3 VCC VSS Supply Ground 0 0 0 V TSTG Storage Temperature VIH Input High Voltage 2.2 3.0 VCC+0.3 V PT Power Dissipation 1.7 W VIHQ VIL I/O High Voltage Input Low Voltage 2.2 –0.5(1) 3.0 — VCCQ+0.3 V V IOUT DC Output Current 20 mA 0.8 NOTE: 3075 tbl 06 1. VIL (min.) = –1.5V for pulse width of less than 10ns, once per cycle. CAPACITANCE (TA = +25°C, f = 1.0 MHz) Parameter(1) Condition Max. Unit CIN Input Capacitance VIN = 0V 5 pF CTAG TAG Input/Output Capacitance VI/O = 0V 7 pF COUT Output Capacitance VOUT = 0V 7 pF Symbol NOTES: 3075 tbl 08 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. VIN should not exceed Vcc+0.5V. All pins should not exceed 7.0V. VCCQ should never exceed VCC, and VCC should never exceed VCCQ + 4.0V. NOTE: 3075 tbl 07 1. This parameter is determined by device characterization but is not production tested. DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% OR 3.3V ± 0.3V) Symbol Min. Max. Unit |ILI| Input Leakage Current Parameter VCC = Max., VIN = 0V to VCC Test Condition — 5 µA |ILO| Output Leakage Current CS1 ≥ V IH, CS2 ≤ VIL, OE ≥ VIH, VCC = Max. VOUT = 0V to VCCQ, VCCQ = Max. — 5 µA VOL Output Low Voltage IOL = 4mA, VCC = Min. — 0.4 V VOH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — V 3075 tbl 09 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1, 2) (VCC = 5.0V ± 5%) Symbol Parameter 71215S8 71215S9 71215S10 71215S12 Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit Test Condition ICC Operating Power Supply Current PWRDN ≥ VIH Outputs Open, VCC = Max., f = fMAX(3) ISB Standby Power Supply Current PWRDN ≤ VIL, VIN ≥ VIH or ≤ V IL VCC = Max., f = fMAX(3) ISB1 Full Standby Power PWRDN ≤ VIL, VIN ≥ VHC or ≤ VLC(4) Supply Current VCC = Max., f = 0(3) 330 — 300 — 290 — 280 — mA 30 — 30 — 30 — 30 — mA 25 — 25 — 25 — 25 — mA NOTES: 1. All values are maximum guaranteed values. 2. CS1 ≤ VIL, CS2 ≥ VIH. 3. fMAX =1/tCYC (all address inputs are cycling at fMAX). f = 0 means no address input lines are changing. 4. VHC = VCC - 0.2V, VLC = 0.2V 14.3 3075 tbl 10 6 IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% 3.3V ± 0.3V, TA = 0 to 70°C) OR Symbol Parameter Read Cycle tAAT Address Access Time Tag Bits tACST Chip Select Access Time Tag Bits IDT71215S8 IDT71215S9 IDT71215S10 IDT71215S12 Min. Max. Min. Max. Min. Max. Min. — — 10 8 — — 11 9 — — 12 10 — — 14 12 ns ns Max. Unit tCLZ(1) Chip Select to Tag and Status Bits in Low-Z 1 — 1 — 1 — 1 — ns tCHZ(1) tOET Chip Select to Tag and Status Bits in High-Z Output Enable to Tag Bits Valid 1 — 5 5 1 — 6 6 1 — 6 6 1 — 7 7 ns ns tOTLZ(1) Output Enable to Tag Bits in Low-Z 0 — 0 — 0 — 0 — ns tOTHZ(1) tTOH tOES Output Enable to Tag Bits in High-Z Tag Bit Hold from Address Change Output Enable to Status Bits Valid 1 2 — 5 — 5 1 2 — 6 — 6 1 2 — 6 — 6 1 2 — 7 — 7 ns ns ns tOSLZ(1) Output Enable to Status Bits in Low-Z 0 — 0 — 0 — 0 — ns tOSHZ(1) tAAS tACSS tSOH Output Enable to Status Bits in High-Z Address Access Time Status Bits Chip Select Access Time Status Bits Status Bit Hold from Address Change 1 — — 2 5 8 6 — 1 — — 2 6 9 7 — 1 — — 2 6 10 8 — 1 — — 2 7 12 10 — ns ns ns ns NOTE: 1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested. 3075 tbl 11 AC ELECTRICAL CHARACTERISTICS (1) (VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% OR 3.3V ± 0.3V, TA = 0 to 70°C) Symbol Parameter Reset and Power Down Cycles Set-up Time IDT71215S8 Min. Max. IDT71215S9 Min. Max. IDT71215S10 Min. Max. IDT71215S12 Min. Max. Unit 4 — 4 — 4 — 4 — ns 1 — 2 — — — 50 — 9 110 1 — 2 — — — 60 — 10 120 1 — 2 — — — 60 — 10 120 1 — 2 — — — 70 — 12 130 ns ns ns ns ns — 9 — 10 — 10 — 12 ns HIGH to TAG Low-Z — 90 — 100 — 100 — 110 ns Set-up to RESET LOW RESET HIGH to PWDRN LOW RESET HIGH to WET and WES LOW 30 1 90 — — — 30 1 95 — — — 30 1 95 — — — 30 1 105 — — — ns CLK ns LOW to Low Power Mode — 50 — 50 — 50 — 50 ns HIGH to Active Power Mode 0 — 0 — 0 — 0 — ns PWRDN LOW to Outputs in High-Z — 9 — 10 — 10 — 12 ns PWRDN HIGH to Outputs in Low-Z HIGH to Outputs Valid 0 — — 50 0 — — 50 0 — — 50 0 — — 50 ns ns and WES HIGH to PWRDN LOW 5 — 5 — 5 — 5 — ns 50 — 50 — 50 — 50 — tSR RESET tHR tSRST tSHRS tRSMI tRSMV RESET tRSHZ(2) RESET LOW to TAG High-Z tRSLZ(2) RESET tPDSR tRHPL tRHWL PWRDN tPD(2) PWRDN tPU(2) PWRDN tPDHZ(2) tPDLZ(2) tPUV PWRDN tWHPL(2) WET tPUWL PWRDN Hold Time Status Bit Reset Time Status Bit Hold from RESET LOW RESET LOW to MATCH and BRDY Invalid RESET HIGH to MATCH and BRDY Valid HIGH to WET and WES Active NOTES: 1. Power-down mode is intended to be used during extended time periods of device inactivity. 2. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested. 14.3 ns 3075 tbl 12 7 IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (1) (VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% Symbol OR 3.3V ± 0.3V, TA = 0 to 70°C) IDT71215S8 IDT71215S9 IDT71215S10 IDT71215S12 Min. Max. Min. Max. Min. Max. Min. Max. Unit Parameter Write Cycle and Clock Parameters tCYC Clock Cycle Time 15 — 15 — 15 — 16.6 — ns tCH(2, 3) Clock Pulse HIGH 4.5 — 4.5 — 4.5 — 5 — ns tCL(2, 3) Clock Pulse LOW 4.5 — 4.5 — 4.5 — 5 — ns tS WET , WES, Chip Select, and Input Data Set-up Time 3 — 3 — 3 — 3 — ns tH WET , WES, Chip Select, and Input Data Hold Time tSA Address Set-up Time tHA tWMI ( 3) 1 — 1 — 1 — 1 — ns 3 — 3 — 3 — 3 — ns Address Hold Time 1 — 1 — 1 — 1 — ns CLK HIGH Write to MATCH and BRDY Invalid — 6 — 7 — 7 — 8 ns tCKLZ CLK HIGH Read to Outputs in Low-Z 1.5 — 1.5 — 1.5 — 1.5 — ns tCTV(4) CLK HIGH Read to Tag Bits Valid — 9 — 10 — 10 — 12 ns tCSV(4) CLK HIGH Write to Status Outputs Valid — 8 — 9 — 9 — 10 ns tCSH(3) Status Output Hold from CLK HIGH Write 0 — 0 — 0 — 0 — ns tWHPL WET 5 — 5 — 5 — 5 — ns tPUWL PWRDN 50 — 50 — 50 — 50 — ns and WES HIGH to PWRDN LOW HIGH to WET and WES Active NOTES: 1. All Write cycles are synchronous and referenced from rising CLK. 2. This parameter is measured as a HIGH time above 2.0V and a LOW time below 0.8V. 3. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested. 4. Addresses are stable prior to CLK transition HIGH. 14.3 3075 tbl 14 8 IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% Symbol OR 3.3V ± 0.3V, TA = 0 to 70°C) Parameter IDT71215S8 Min. Max. IDT71215S9 Min. Max. IDT71215S10 Min. Max. IDT71215S12 Min. Max. Unit MATCH and BRDY Cycles tADM Address to MATCH Valid — 8 — 9 — 10 — 12 ns tDAM Data Input to MATCH Valid — 8 — 9 — 10 — 12 ns tCSM Chip Select to MATCH Valid — 8 — 9 — 10 — 12 ns tCMLZ(1) Chip Select to MATCH in Low-Z 1 — 1 — 1 — 1 — ns tCMHZ(1) Chip Select to MATCH in High-Z 1 5 1 6 1 6 1 7 ns tMHA MATCH Valid Hold from Address 2 — 2 — 2 — 2 — ns tMHD MATCH Valid Hold from Data 2 — 2 — 2 — 2 — ns tBHA BRDY Valid Hold from Address 2 — 2 — 2 — 2 — ns tBHD BRDY Valid Hold from Data 2 — 2 — 2 — 2 — ns tADB Address to BRDY Valid — 9 — 10 — 11 — 13 ns tDAB Data Input to BRDY Valid — 9 — 10 — 11 — 13 ns tCSB Chip Select LOW to BRDY Valid — 9 — 10 — 11 — 13 ns — 6 — 6 — 7 — 8 ns tOEBV BRDYOE LOW to BRDY Valid tOBLZ(1) BRDYOE LOW to BRDY in Low-Z 0 — 0 — 0 — 0 — ns tOBHZ(1) BRDYOE HIGH to BRDY in High-Z 1 5 1 6 1 6 1 7 ns 5 — 5 — 5 — 6 ns tBYFH BRDYH HIGH to Force BRDY HIGH — tBYHV BRDYH LOW to BRDY Valid — 5 — 5 — 5 — 6 ns 4 — 4 — 4 — 4 — ns tSB BRDYIN Set-up Time tHB BRDYIN Hold Time 1.5 — 1.5 — 1.5 — 1.5 — ns tBIBL CLK HIGH BRDYIN LOW to BRDY LOW — 6 — 6 — 7 — 8 ns — 6 — 6 — 7 — 8 ns — 6 — 7 — 7 — 8 ns tBIBV CLK HIGH BRDYIN HIGH to BRDY Valid tOEMI OET LOW to MATCH and BRDY Invalid tOEMV OET HIGH to MATCH and BRDY Valid — 7 — 8 — 8 — 10 ns tWRBH(2) W/R HIGH to BRDY HIGH — 6 — 7 — 7 — 8 ns tWRBV(2) W/R LOW to tWMI tWMV(3) Valid — 6 — 7 — 7 — 8 ns CLK HIGH Write to MATCH and BRDY Invalid — 7 — 7 — 7 — 8 ns CLK HIGH Read to MATCH and BRDY Valid — 8 — 9 — 10 — 12 BRDY NOTES: 1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested. 2. These parameters only apply when SFUNC is LOW and the internal WT bit is HIGH. 3. tADM, tDAM, tCSM and tADB, tDAB, tCSB must also be satisfied. 14.3 ns 3075 tbl 15 9 IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V AC Test Load See Figs. 1, 2, 3, & 4 3075 tbl 16 AC TEST LOADS VCCQ VCCQ 893 Ω 893 Ω Outputs Tag I/O 347 Ω 347 Ω 30pF * 50pF * 3075 drw 03 3075 drw 04 Figure 1. AC Test Load Figure 2. Tag I/O AC Test Load * Including scope and jig capacitance 6 VCCQ 5 Tag I/O and Outputs 347 Ω 893 Ω 4 3 ∆t (Typical, ns) 5pF* 2 1 3075 drw 05 Figure 3. AC Test Load (for tHZ and tLZ parameters ) 20 30 * Including scope and jig capacitance 50 80 100 ∆ Capacitance (pF) 3075 drw 06 Figure 4. Lumped Capacitance Load, Typical Derating 14.3 10 14.3 tCSH tH tH tS Valid tH Valid Input tS tS VALID tCSV NOTE: 1. Transition is measured ±200mV from steady state. VLDOUT DTYOUT WTOUT DTYIN WTIN VLDIN WES TAG (0:11) OET WET CS2 CS1 A (0:13) CLK STATUS WRITE TAG WRITE tS tCTV Valid tSOH tAAS tCKLZ(1) tH tAAT TAG READ VALID Valid tCHZ(1) Valid Output tOTHZ(1) tCHZ(1) tCLZ(1) tACSS tOTLZ(1) tOET tACST tCLZ(1) tSOH tAAS tTOH tAAT VALID Valid Valid Output 3075 drw 07 Valid Valid Output IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORMS OF WRITE AND READ CYCLES 11 14.3 Valid MATCH MATCH Valid Valid BRDY tBYFH tS tBYHV NOTE: 1. Transition is measured ±200mV from steady state. Valid tDAB tDAM tMHD tBHD Valid Match Data tADB tADM tMHA tBHA Valid Address BRDY BRDYOE BRDYH OET WET WES CS2 CS1 TAG (0:11) A (0:13) CLK tWMI Valid tH tS tH tWMV tS tWMI Valid Valid tH tS tWMV Valid Valid tOEMI tOEMV tCMHZ(1) tCSM tCSB tCMLZ(1) Valid Valid tOBHZ(1) Valid 3075 drw 08 tOEBV tOBLZ (1) IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORMS OF MATCH AND BRDY FUNCTIONS 12 IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORMS OF RESET FUNCTION CLK tSR tHR RESET tPDSR PWRDN tSRST tSHRS VLDOUT DTYOUT WTOUT tRHWL tS WES WET tRSMI tRSMV VALID BRDY MATCH VALID tRSLZ(1) tRSHZ(1) TAG (0:11) 3075 drw 09 NOTE: 1. Transition is measured ±200mV from steady state. CLOCK TIMING WAVEFORM tCH tCYC tCL 0.8V CLK 2.0V 0.8V 2.0V 3075 drw 10 TIMING WAVEFORMS OF BRDY AND W/R SIGNAL Applies when SFUNC is LOW, and the internal WT bit is HIGH CLK tSB tHB BRDYIN tBIBL tBIBV W/R tWRBH BRDY BRDY Valid tWRBV BRDY Valid 3075 drw 11 14.3 13 IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORMS OF OES FUNCTION OES tOES tOSHZ(1) tOSLZ(1) VLDOUT DTYOUT Valid Output Valid Output WTOUT 3075 drw 12 NOTE: 1. Transition is measured ±200mV from steady state. TIMING WAVEFORMS OF POWER DOWN FUNCTION PWRDN tWHPL tPUWL CLK tRHPL RESET tS tS , WET WES tPDHZ(1) tPUV TAG (0:11) Valid TAG out tPDLZ(1) VLDOUT DTYOUT WTOUT Valid Status out BRDY BRDY MATCH Valid MATCH Valid tPD tPU ICC ISB 3075 drw 13 NOTE: 1. Transition is measured ±200mV from steady state. ORDERING INFORMATION IDT 71215 Device Type S Power XX Speed PF Package PF 8 9 10 12 14.3 Plastic Thin Quad Flatpack (PN80-1) Speed in nanoseconds 3075 drw 14 14