ALTERA Datasheet

2016
DT8051 IP Core
Tiny Area 8051-compatible Microcontroller v. 4.71
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
IP CORE OVERVIEW
The DT8051 is an area optimized, tiny soft core, of
a single-chip 8-bit embedded microcontroller,
based on World's fastest and most popular DP8051
core, available since over 8 years. The DT8051 soft
core is 100% binary-compatible with the industry
standard 8051 8-bit microcontroller. It has a very
low gate count architecture, giving 6 650 ASIC
gates for a complete system, including the DoCD
on-chip debugger. Dhrystone 2.1 benchmark program runs exactly 8.1 times faster than the original 80C51 at the same frequency. The same C
compiler was used for benchmarking of the core
vs. 80C51, with the same settings. The DT8051
Core has a built-in support for the 2-wire TTAGTM
interface - DCD Hardware Debug System, called
TM
DoCD . This version of the debugger is dedicated
for applications, where a number of external pins is
limited. The DT8051 includes also up to eight external interrupt sources, an advanced Power Management Unit, Timers 0&1, I/O bit addressable
Ports, a full duplex UART and an interface for external SFR. It is delivered with fully automated test
bench and complete set of tests, allowing easy
package validation at each stage of SoC design
flow.
KEY FEATURES
● Software compatible with the 8051 industry standard
● Very low gate count, area optimized architecture – 6
650 ASIC gates for a complete system with DoCD onchip debugger
● 8.1 times faster than a standard 8051
● 7.63 VAX MIPS at 100 MHz
● Up to 256 bytes of internal (on-chip) Data Memory
● Up to 64k bytes of internal (on-chip) Program
Memory
● Up to 64k bytes of external (off-chip) Program
Memory
● Up to 64k bytes of external (off-chip) Data Memory
● De-multiplexed Address/Data Bus to allow easy
connection to memory
● Power Management Unit
○
○
○
Power management mode
Switchback feature
Stop mode
● Interrupt Controller
○
○
○
2 priority levels
8 external interrupt sources
3 interrupt sources from peripherals
● 8-bit I/O Port
○
○
Bit addressable data direction for each line
Read/write of single line and 8-bit group
● Two 16-bit timer/counters
○
○
○
Timers clocked by internal source
Auto reload 8-bit timers
Externally gated event counters
● Full-duplex serial port
○
○
8-bit asynchronous mode, variable baud
9-bit asynchronous mode, variable baud
rate
rate
● Interface for additional Special Function Registers
● 2-wire DoCD™ debug unit
○
Processor execution control
○
○
○
○
Run, Halt
Step into instruction
Skip instruction
Read-write all processor contents
○
○
○
○
○
○
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
Code execution breakpoints
○
○
○
two real-time PC breakpoints
unlimited number of real-time OPCODE breakpoints
Three independent Memory watchpoints
○
○
SFR, DATA, XDATA
2-wire TTAG communication interface
● Fully synthesizable, static synchronous design, with
positive edge clocking and no internal tri-states
● Scan test ready
DELIVERABLES
♦
Source code:
●
●
●
♦
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
●
●
●
♦
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
●
●
●
♦
♦
♦
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
●
●
IP Core implementation support
3 months maintenance
●
●
Delivery of the IP Core and documentation updates, minor
and major versions changes
Phone & email support
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
PINS DESCRIPTION
PIN
clk
rst
port2i[7:0]
prgdatai[7:0]
xdatai[7:0]
ramdatai[7:0]
sfrdatai[7:0]
int0
int1
int2
int3
int4
int5
int6
Int7
t0
t1
gate0
gate1
rxdi
ttdi
port2o[7:0]
prgaddr[15:0]
prgdatao[7:0]
prgramwr
address[15:0]
xdatao[7:0]
xdataz
xdatawr
xdatard
xprgrd
xprgwr
ramaddr[7:0]
ramdatao[7:0]
ramwe
ramoe
sfraddr[6:0]
sfrdatao[7:0]
sfrwe
sfroe
txd
ttck
ttdoen
ttdo
TYPE
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
DESCRIPTION
Global clock
Global reset
Port 2 input
Data bus from internal program memory
Data bus from external data/code
memory
Data bus from internal data memory
Data bus from user SFR’s
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
Timer 0 input
Timer 1 input
Timer 0 gate input
Timer 1 gate input
Serial receiver input
DoCD data input
Port 2 output
Internal program memory address bus
Data bus for Internal program memory
Internal program memory write
External data/code memory address bus
Data bus for external data/code memory
External XDATA bus ‘Z’ state
External data memory write
External data memory read
External program memory read
External program memory write
RAM address bus
Data bus for internal data memory
Internal data memory write enable
Internal data memory output enable
SFR’s address bus
Data bus for user SFR’s
User SFR’s write enable
User SFR’s output enable
Serial transmitter output
DoCD clock output
DoCD data output enable
DoCD data output
APPLICATIONS
♦
♦
♦
♦
Low power battery operated devices
Mixed signal systems
Area optimized FPGA/ASIC design
FSM replacements
BENEFITS
♦
♦
♦
♦
Lowest gate count, 8051 compatible architecture
Very low power consumption
Significant performance improvement with respect
to the 80C51 device, working at the same clock
frequency (8.1 in terms of Dhrystone MIPS)
On demand customization
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use.
There are two formats of the delivered IP Core:
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
UNITS SUMMARY
ALU - Arithmetic Logic Unit - performs the arithmetic
and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status
Word (PSW), (B) registers and related logic, like
arithmetic unit, logic unit, multiplier and divider.
Control Unit - It performs the core synchronization
and data flow control. This module is directly connected to Opcode Decoder and manages execution of
all microcontroller tasks.
Program Memory Interface - It contains Program
Counter (PC) and related logic. It performs
the instructions code fetching. Whole program
memory (FLASH or SRAM type), can be written
by DoCD™ debugger or application can modify some
part of its code - for example, storing some data
which shouldn't volatile.
External Memory Interface - Contains memory access
related registers, like Data Page High (DPH) and Data
Page Low (DPL) registers. It performs the memory
addressing and data transfers.
Internal Data Memory Interface - Interface controls
access into the internal memory of size up to 256
bytes. It contains 8-bit Stack Pointer (SP) register and
related logic.
SFR’s Interface - Special Function Register interface,
manages communication between CPU and user
specified special registers.
Opcode Decoder - Performs an opcode decoding
instruction and control functions for all other blocks.
Interrupt Controller - Interrupt Control module is
responsible for the interrupt manage system for the
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
eight external and internal interrupt sources. It contains interrupt related registers, such as Interrupt
Enable (IE), Interrupt Priority (IP), Extended Interrupt
Enable (EIE), Extended Interrupt priority (EIP) and
(TCON) registers.
SYMBOL
port2i(7:0)
prgdatai(7:0)
Timers - System timers module. Contains two 16bits
configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1,
TL1) and Timers Mode (TMOD) registers. In the timer
mode, timer registers are incremented every 12 (or 4)
CLK periods, when appropriate timer is enabled. In
the counter mode, the timer registers are incremented every falling transition on their corresponding
input pins (T0, T1), if gates are opened (GATE0,
GATE1). T0, T1 input pins are sampled every CLK
period. It can be used as clock source for UARTs.
xdatai(7:0)
ramdatai(7:0)
sfrdatai(7:0)
UART - Universal Asynchronous Receiver & Transmitter module is full duplex, meaning, it can transmit and
receive concurrently. Includes Serial Configuration
register (SCON), serial receiver and transmitter buffer
(SBUF) registers. Its receiver is double-buffered, so it
can commence reception of a second byte before the
previously received byte has been read from the
receive register. Writing to SBUF0 loads the transmit
register, and reading SBUF0, reads a physically separate receive register. It works in 2 asynchronous
modes with variable baud rate, covering all standard
transmission speeds.
DoCD™ Debug Unit – it is a DoCDTM Debug Unit, 2wire, low gate count, real-time hardware debugger,
which provides debugging capability of a whole SoC
system. Unlike other on-chip debuggers, DoCDTM
provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction,
read/write any contents of microcontroller, including
all registers, internal and external program memories
and all SFRs, including user defined peripherals.
Hardware breakpoints control execution of program
memory code; hardware watchpoints can be set and
control internal and external data memories and
SFRs. Hardware watchpoints are executed if any
write/read occurs at particular address, with certain
data pattern or without pattern. Two additional pins
(CODERUN and DEBUGACS) indicate the state of the
debugger and CPU. CODERUN is active, when CPU is
executing an instruction. DEBUGACS pin is active,
when any access is performed by DoCDTM debugger.
The DoCDTM system includes TTAG interface
and complete set of tools, to communicate and work
with core, in real time debugging. It is built as scalable
unit and some features can be turned off by the user,
to save silicon and reduce power consumption. When
debugger is not used, it is automatically switched to
power save mode. Finally, when debug option is no
longer used, whole debugger is turned off.
xdatao(7:0)
xaddress(15:0)
xdataz
xdatard
xdatawr
xprgrd
xprgwr
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatao(7:0)
sfraddr(6:0)
sfroe
sfrwe
int0
int1
int2
int3
int4
int5
int6
int7
t0
gate0
ttdi
ttdo
ttdoen
ttck
t1
gate1
rxd0i
txd0
rst
clk
Ports - Block contains 8051’s general purpose I/O
ports. Each of port’s pin can be read/write
as a single bit or as an 8-bit bus.
port2o(7:0)
prgdatao(7:0)
prgaddr(15:0)
prgramwr
BLOCK DIAGRAM
xaddress(15:0
xdatai(7:0)
xdatao(7:0)
xdataz
xdatard
xdatawr
xprgrd
xprgwr
External
Memory
Interface
prgaddr(15:0)
prgdatai(7:0)
prgdatao(7:0)
prgramwr
Program
Memory
Interface
I/O Port
Registers
Timers
0&1
t0
t1
gate0
gate1
UART
rxd0i
txd0
Opcode
Decoder
ramaddr(7:0)
ramdatai(7:0)
ramdatao(7:0)
ramoe
ramwe
Internal Data
Memory
Interface
Interrupt
Controller
SFR Interface
ALU
clk
rst
Control
Unit
port2(7:0)
DoCD
Debugger
int0
int1
int2
int3
int4
int5
int6
int7
sfraddr(6:0)
sfrdatai(7:0)
sfrdatai(7:0)
sfroe
sfrwe
ttdi
ttdo
ttdoen
ttck
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
PERFORMANCE
CONTACT
The following tables give a survey about the
DT8051 and the DoCD on-chip debugger area and
performance in ALTERA® Programmable Logic
Devices (all features are included). Results given
for a working system with SFR IDATA, CODE and
XDATA memories connected.
Digital Core Design Headquarters:
Device
CYCLONE-II
CYCLONE-III
STRATIX-II
STRATIX-III
Distributors:
Speed grade
Area
-6
1666 LC
-6
1656 LC
-3
1287 ALUT
-2
1289 ALUT
DT8051 without DoCD debugger
Fmax
95 MHz
100 MHz
155 MHz
210 MHz
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
tel.:
fax:
Please check:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
http://dcd.pl/sales
Device
Speed grade
Area
Fmax
CYCLONE-II
-6
1913 LC
90 MHz
CYCLONE-III
-6
1911 LC
95 MHz
STRATIX-II
-3
1507 ALUT
150 MHz
STRATIX-III
-2
1508 ALUT
200 MHz
DT8051 with compact version1 of DoCD debugger
Device
Speed grade
Area
CYCLONE-II
-6
2088 LC
CYCLONE-III
-6
2093 LC
STRATIX-II
-3
1623 ALUT
STRATIX-III
-2
1629 ALUT
DT8051 with full version2 of DoCD debugger
Fmax
80 MHz
95 MHz
135 MHz
185 MHz
1- compact DoCD version includes processor execution control (run,
halt, reset, step); read-write all processor content (PC, SFRs); readwrite all processor memories (IDATA, XDATA, CODE memory); FLASH
code memory programming; one hardware code execution breakpoint; unlimited number of OPCODE execution breakpoints
2- full DoCD version includes processor execution control (run, halt,
reset, step); read-write all processor content (PC, SFRs); read-write
all processor memories (IDATA, XDATA, CODE memory); FLASH
CODE memory programming; two hardware code execution breakpoints; six configurable hardware watch-points (IDATA, XDATA,
SFRs); unlimited number of OPCODE execution breakpoints
Dhrystone Benchmark Version 2.1 was used to
measure the Core performance. The following
table gives a survey about the DT8051 performance in terms of Dhrystone/sec and VAX MIPS
rating per 1 MHz (DMIPS/MHz).
Device
80C51
DT8051
Dhry/sec [12 MHz]
DMIPS/MHz
80C51 ratio
197
0,0094
1,00
1597
0,0763
8,11
DT8051 performance in terms of DMIPS/MHz
DMIPS/MHz
0,1
0,0763
0,08
0,06
0,04
0,02
0,0094
0
80C51
DT8051
4
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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