ASIC Datasheet

2016
DP80C51 IP Core
Pipelined High Performance 8-bit Microcontroller v. 4.01
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
● User programmable External Data Memory Wait
States solution, for a wide range of memories speed
● Dedicated signal for Program Memory writes
● Interface for additional Special Function Registers
● Fully synthesizable, static synchronous design, with
positive edge clocking and no internal tri-states
● Scan test ready
● 2.0 GHz virtual clock frequency in a 0.25u technological process
PERIPHERALS
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○
CPU FEATURES
● 100% pin compatible with the 8051 industry standard
● 100% software compatible with 8051 industry
standard
● Pipelined RISC architecture enables to execute
instructions up to 10 times faster compared to a
standard 8051
● 24 times faster multiplication
● 12 times faster addition
● Up to 256 bytes of internal (on-chip) Data Memory
● Up to 64K bytes of internal (on-chip) or external (offchip) Program Memory
● User programmable Program Memory Wait States
solution, for a wide range of memories speed
Processor execution control
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IP CORE OVERVIEW
The DP80C51 is an ultra-high performance, speed
optimized soft core of a single-chip 8-bit embedded controller, dedicated to operate with fast
(typically on-chip) and slow (off-chip) memories.
The core has been designed with a special concern
about performance to power consumption ratio.
This ratio is extended by an advanced power management unit - the PMU. The DP80C51 is 100%
binary and pin compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of the DP80C51: Harvard, where an
external data and program buses are separated
and von Neumann, with a common program
and an external data bus. The DP80C51 has a Pipelined RISC architecture, up to 10 times faster compared to the standard architecture - it executes
85-200 million instructions per second. This performance can be also exploited to a great advantage in low power applications, where the core
can be clocked over ten times slower than the
original implementation, with no performance
penalty. The DP80C51 is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC
design flow.
DoCD™ debug unit
○
Read-write all processor contents
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2 priority levels
2 external interrupt sources
3 interrupt sources from peripherals
Four 8-bit I/O Ports
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Bit addressable data direction for each line
Read/write of single line and 8-bit group
Two 16-bit timer/counters
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Power management mode
Switchback feature
Stop mode
Interrupt Controller
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Program Memory(PC)
Instructions Smart Trace Buffer – configurable up to
8192 levels (optional)
Automatic adjustment of debug data transfer speed
rate between HAD and Silicon
TTAG or JTAG Communication interface
Power Management Unit
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Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
Unlimited number of software breakpoints
○
●
address by any write into memory
address by any read from memory
address by write into memory required data
address by read from memory required data
Unlimited number of software watch-points
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one at Internal (direct) Data Memory
one at Special Function Registers (SFRs)
one at External Data Memory
Hardware watch-points activated at a certain
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up to eight real-time PC breakpoints
unlimited number of real-time OPCODE breakpoints
Hardware execution watch-point
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Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
Code execution breakpoints
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Run
Halt
Step into instruction
Skip instruction
Timers clocked by internal source
Auto reload 8-bit timers
Externally gated event counters
Full-duplex serial port
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Synchronous mode, fixed baud rate
8-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, variable baud rate
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
CONFIGURATION
The following parameters of the DP80C51 core can
be easily adjusted to requirements of a dedicated
application and technology. The configuration
of the core can be effortlessly done, by changing
appropriate constants in the package file. There is
no need to change any parts of the code.
 Internal Program Memory type
 Internal Program ROM Memory size
 Internal Program RAM Memory size
 Interrupts
-
 Power Management Mode
 Stop mode
 DoCD debug unit
0 - 64kB
0 - 64kB
subroutines location
used
unused
used
unused
used
unused
DELIVERABLES
♦
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
●
●
●
♦
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
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♦
♦
♦
Installation notes
HDL core specification
Datasheet
IP Core implementation support
3 months maintenance
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♦
Delivery of the IP Core and documentation updates, minor
and major versions changes
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
PROGRAM MEMORY:
The DP80C51 soft core is dedicated to operate with
Internal and External Program Memory. Internal Program Memory can be implemented as:
○
○
ROM located in address range between 0x0000 
(ROMsize-1)
RAM located in address range between (RAMsize-1) 
0xFFFF
External Program Memory can be implemented as ROM
or RAM located in address range between ROMsize 
RAMsize.
♦
INTERNAL DATA MEMORY:
The DP8C051 can address Internal Data Memory of up to
256 bytes. The Internal Data Memory can be implemented, as a Single-Port synchronous RAM.
EXTERNAL DATA MEMORY:
The DP80C51 soft core can address up to 64 kB of External Data Memory.
♦
USER SPECIAL FUNCTION REGISTERS:
Up to 104 External (user) Special Function Registers
(ESFRs) may be added to the DP80C51 design. ESFRs are
memory mapped into Direct Memory, between addresses 0x80 and 0xFF, in the same manner, as core SFRs.
They may occupy any address that is not occupied
by a SFR core.
♦
Synthesis scripts
Example application
Technical support
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DESIGN FEATURES
♦
Source code:
●
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●
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
synchronous
asynchronous
Besides parameters mentioned above, all available
peripherals and external interrupts can be excluded from the core, by changing appropriate constants in the package file.
♦
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use. There are two formats of the delivered IP
Core:
WAIT STATES SUPPORT:
The DP80C51 soft core is dedicated for operation with a
wide range of Program and Data memories. Slow Program and External Data memory, may assert a memory
WAIT signal, to hold up CPU activity for required period
of time.
UNITS SUMMARY
Arithmetic Logic Unit - performs the arithmetic
and
logic
operations,
during
execution
of an instruction. It contains accumulator (ACC),
Program Status Word (PSW), (B) registers and
related logic, like arithmetic unit, logic unit, multiplier and divider.
Opcode Decoder - Performs an opcode decoding
instruction and control functions for all other
blocks.
Control Unit – Performs the core synchronization
and data flow control. This module is directly connected to Opcode Decoder and manages execution
of all microcontroller tasks.
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
Program Memory Interface – Program Memory
Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching.
Program Memory can be also written. This feature
allows usage of a small boot loader, to load new
program into ROM, RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or DoCD™
module.
External Memory Interface - Contains memory
access related registers, such as Data Page High
(DPH), Data Page Low (DPL). It performs the external Program and Data Memory addressing
and data transfers. Program fetch cycle length can
be programmed by the user. This feature is called
Program Memory Wait States, and it allows core
to work with different speed program memories.
Internal Data Memory Interface – Interface controls access into the internal memory of size up to
256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Registers
interface controls access to the special registers.
It contains standard and used defined registers and
related logic. User defined external devices can be
quickly accessed (read, written, modified), by using
all direct addressing mode instructions.
Interrupt Controller – Interrupt control module is
responsible for the interrupt manage system,
for the external and internal interrupt sources.
It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers. Please note, that external pins of
this module are connected to appropriate pins of
P3 port.
Timers – System timers module. Contains two 16
bits configurable timers: Timer 0 (TH0, TL0), Timer
1 (TH1, TL1) and Timers Mode (TMOD) registers.
In the timer mode, timer registers are incremented
every 12 CLK periods, when appropriate timer is
enabled. In the counter mode, the timer registers
are incremented every falling transition on their
corresponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins are
sampled every CLK period. It can be used as a clock
source for UARTs. Please note, that external pins of
this module are connected to appropriate pins of
P3 port.
UART0 – Universal Asynchronous Receiver
and Transmitter module is full duplex, which
means that it can transmit and receive concurrently. Includes Serial Configuration register (SCON),
serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it
can commence reception of a second byte, before
the previously received byte has been read from
the receive register. Writing to SBUF0 loads the
transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be
synchronized by Timer 1. Please note, that external
pins of this module are connected to appropriate
pins of P3 port.
Ports - Block contains 8051's general purpose I/O
ports. Each of port's pin can be read/written
as a single bit or as an 8-bit bus P0, P1, P2, P3.
The P0, P2, P3 are multi-functional ports.
When used with External memory P0 works
as a multiplexed Data/LSB address to memory,
and P2 works as a MSB address to external
memory, P3.6 is a write signal and P3.7 is a read
signal. Functionality of port is the same as in legacy
80C51 microcontroller.
Power Management Unit – Power Management
Unit contains advanced power saving mechanisms
with switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or run
core in lower clock frequency (Power Management
Mode), to significantly reduce power consumption.
Switchback feature allows UARTs and interrupts to
be processed in full speed mode, if enabled. It is
highly desirable, when microcontroller is planned
to be used in portable and power critical applications.
DoCD™ Debug Unit – It is a real-time hardware
debugger, which provides debugging capability of a
whole SoC system. Unlike other on-chip debuggers,
TM
DoCD ensures non-intrusive debugging of running application. It can halt, run, step into or skip
an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including
user defined peripherals. Hardware breakpoints
can be set and controlled on program memory,
internal and external data memories, as well as on
SFRs. Hardware watchpoints can be set and controlled on internal and external data memories and
also on SFRs. Hardware watchpoints are executed,
if any write/read occurs at particular address, with
certain data pattern or without pattern. Two additional pins: CODERUN and DEBUGACS, indicate the
state of the debugger and CPU. CODERUN is active,
when CPU is executing an instruction. DEBUGACS
pin is active, when any access is performed by
TM
TM
DoCD debugger. The DoCD system includes
TTAG or JTAG interface and complete set of tools,
to communicate and work with core in real time
debugging. It is built, as a scalable unit and some
features can be turned off by the user, to save
silicon and reduce power consumption. When
debugger is not used, it is automatically switched
to power save mode. Finally, when debug option is
no longer used, whole debugger is turned off.
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
DP8051 FAMILY OVERVIEW
4
4
Floating Point Coprocessor
1
2
Fixed Point Coprocessor
2
3
SPI
I\O Ports
1
1
2
Watchdog
Master I2C Bus Controller
Slave I2C Bus Controller
UART
2
2
2
Compare/Capture
Timer/Counters
2
5
15
Data Pointers
Stack space size
off-chip
on-chip ROM
10 64k 64k 64k 256 256 16M
10 64k 64k 64k 256 256 16M
10 64k 64k 64k 256 256 16M
Interrupt levels
DP8051CPU
DP8051
DP8051XP
on-chip RAM
Design
Architecture speed
grade
Program
Memory space
Internal Data Memory
space
External Data Memory
space
External Data / Program
Memory Wait States
Power Management
Unit
Interface for additional
SFRs
Interrupt sources
Main features of each DP80C51 family member have been summarized in the table below. It gives a brief
member characteristic, helping you to select the most suitable IP Core for your application. You can specify
your own peripheral set (including listed below and others) and requests the core modifications.
-
-
-
-
-
-
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DP8051 family of Pipelined High Performance Microcontroller Cores
DP80390 FAMILY OVERVIEW
2
3
1
2
4
4
-
-
-
-
-
-
Floating Point Coprocessor
I\O Ports
1
1
2
Watchdog
Master I2C Bus Controller 2
Slave I C Bus Controller
SPI
Fixed Point Coprocessor
UART
2
2
2
Compare/Capture
Timer/Counters
2
5
15
Data Pointers
Unit
Interface for additional SFRs
Interrupt sources
Internal Data Memory
space
External Data
Memory space
External Data / Program Memory Wait
States
Power Management
Stack space size
off-chip
on-chip ROM
10 64k 64k 8M 256 256 16M
10 64k 64k 8M 256 256 16M
10 64k 64k 8M 256 256 16M
Interrupt levels
DP80390CPU
DP80390
DP80390XP
Program
Memory space
on-chip RAM
Design
Architecture speed
grade
Main features of each DP80390 family member have been summarized in the table below. It gives a brief
member characteristic, helping you to select the most suitable IP Core for your application. You can specify
your own peripheral set (including listed below and others) and requests the core modifications.
-
DP80390 family of Pipelined High Performance Microcontroller Cores
PROGRAM CODE SPACE
IMPLEMENTATION
The following figure shows an example Program
Memory space implementation in systems with the
DP80C51 Microcontroller core. The On-chip Program Memory located in address space between
0kB and 1kB, is typically used for BOOT code with
system initialization functions. This part of the
code is typically implemented as ROM. The on-chip
Program Memory located in address space between 60kB and 64kB, is typically used for timing
critical part of the code e.g. interrupt subroutines,
arithmetic functions etc. This part of the code is
typically implemented as RAM and can be loaded
by the BOOT code during initialization phase, from
off-chip memory or through a RS232 interface from
an external device. The program code is executed
from the two spaces mentioned above without
wait-states and can achieve top performance, up
to 200 million instructions per second (many instructions executed in one clock cycle). The offchip Program Memory located in address space
between 1kB and 60kB is typically used for main
code and constants. This part of the code is usually
implemented as ROM, SRAM or FLASH device. Due
to relatively long access time, the program code
executed from devices mentioned above must be
fetched with additional Wait-States. The number
of required Wait-States depends on memory access time and the DP80C51 clock frequency.
0xFFFF
0xF000
On chip Memory
(implemented as RAM)
Off chip Memory
(implemented as ROM, SRAM
or FLASH)
0x0400
0x0000
On-chip Memory
(implemented as ROM)
4
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
In most cases, the proper number of Wait-States
cycles is between 2-5. The READY pin can be also
dynamically modulated by e.g. SDRAM controller.
The figure below shows typical Program Memories
connections in a system with the DP80C51 Microcontroller Core.
8
prgramdatai
8
prgdatao
prgramwr
On-chip Memory
(implemented as RAM)
0 Wait-State access
12
prgaddr
10
On-chip Memory
8
prgromdatai
(implemented as ROM)
0 Wait-State access
ASIC or FPGA chip
DP80C51
8
port0
Latch
ale
8
port2
Off-chip Memory
(implemented as FLASH,
or SRAM)
e.g. 2-5 Wait-State access
psen
pswr
The implementation above should be treated as an
example. All Program Memory spaces are fully
configurable. For timing-critical applications, the
whole program code can be implemented as an onchip ROM and (or) RAM and executed without WaitStates, but for some other applications, the whole
program code can be implemented as an off-chip
ROM or FLASH and executed with required number
Wait-State cycles.
port3[5]
bidir
port3[6]
bidir
port3[7]
bidir
ea
rgramdatai[7:0]
rgromdatai[7:0]
ramdatai[7:0]
sfrdatai[7:0]
tdi
tck
tms
rsto
prgaddr[15:0]
prgdatao[7:0]
prgramwr
ale
psen
pswr
ramaddr[7:0]
ramdatao[7:0]
ramoe
ramwe
sfraddr[6:0]
sfrdatao[7:0]
sfroe
sfrwe
tdo
rtck
debugacs
coderun
pmm
stop
input
input
input
input
input
input
input
input
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
I/O Port 3.5, multifunctional
Timer 1 external clock line
I/O Port 3.6 External Data Memory write
I/O Port 3.7
External Data Memory read
Enable all external program memory
Data bus from int. RAM prog. memory
Data bus from int. ROM prog. memory
Data bus from internal data memory
Data bus from user SFR’s
DoCD™ TAP data input
DoCD™ TAP clock input
DoCD™ TAP mode select input
Reset output
Internal program memory address bus
Data bus for internal program memory
Internal program memory write
Address Latch Enable
Program Store (memory) read Enable
Program Store (memory) Write
Internal Data Memory address bus
Data bus for internal data memory
Internal data memory output enable
Internal data memory write enable
Address bus for user SFR’s
Data bus for user SFR’s
User SFR’s read enable
User SFR’s write enable
DoCD™ TAP data output
DoCD™ return clock line
DoCD™ accessing data
CPU is executing an instruction
Power management mode indicator
Stop mode indicator
SYMBOL
ea
prgromdatai(7:0)
prgramdatai(7:0)
PINS DESCRIPTION
PIN
clk
reset
TYPE
input
input
port0[7:0]
bidir
port1[7:0]
bidir
port2[7:0]
bidir
port3[0]
bidir
port3[1]
bidir
port3[2]
bidir
port3[3]
bidir
port3[4]
bidir
DESCRIPTION
Global clock
Global reset input
I/O Port 0, multifunctional
Data/LSB address of external memory
I/O Port 1
I/O Port 2, multifunctional
MSB address of external memory
I/O Port 3.0
Serial receiver input/output port
I/O Port 3.1
Serial transmitter output port
I/O Port 3.2, multifunctional
Interrupt 0 input/timer 0 gate
I/O Port 3.3, multifunctional
Interrupt 1 input/timer 1 gate
I/O Port 3.4, multifunctional
Timer 0 external clock line
ramdatai(7:0)
sfrdatai(7:0)
tdi
tck
tms
reset
clk
port0(7:0)
port1(7:0)
port2(7:0)
ale
port3(7:0)
psen
pswr
prgaddr(15:0)
prgdatao(7:0)
prgramwr
ramaddr(7:0)
ramdatao(7:0)
ramwe
sfraddr(6:0)
sfrdatao(7:0)
sfroe
sfrwe
stop
pmm
tdo
rtck
coderun
debugacs
rsto
5
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
BLOCK DIAGRAM
Opcode
Decoder
I/O Port
Registers
prgramdatai(7:0)
prgromdatai(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
Program
Memory
Interface
Timers
ea
ale
psen
pswr
External
Memory
Interface
Function
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
UART
Interrupt
Controller
Control
Unit
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
clk
reset
rsto
Power
Management
Unit
Internal
Data
Memory
Interface
DoCD™
Debug Unit
User SFR’s
Interface
stop
pmm
tdi
tck
tms
tdo
rtck
coderun
debugacs
ALU
PERFORMANCE
The following tables give a survey about the Core
area and performance in Programmable Logic
Devices after Place & Route (CPU features and
peripherals included):
Device
SC
EC
ECP
XP
Speed grade
Fmax
-7
-5
-5
-5
117 MHz
67 MHz
73 MHz
61 MHz
Core performance in LATTICE® devices
For the user the most important aspect is an application speed improvement. The most commonly
used arithmetic functions and their improvement
are shown in the table below. The improvement
was computed as {80C51 clock periods} divided by
{DP80C51 clock periods} required to execute an
identical function for code executed from an internal (first column) and external (second column)
program memory. More details are available in the
core documentation.
Improvement
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
9,00
9,00
9,00
12,00
9,00
9,00
9,00
12,00
16,00
9,60
12,00
12,00
13,60
12,00
12,00
12,60
11,12
3,00
3,00
3,60
4,00
3,00
3,00
3,60
4,00
6,00
4,80
4,00
4,00
5,47
4,00
4,00
4,89
4,03
Dhrystone Benchmark Version 2.1 was used to
measure the Core performance. The following
table gives a survey about the DP80C51 performance in terms of Dhrystone/sec and VAX MIPS
rating for testing code executed from external (1)
and internal (2) program memory.
Device
80C51
80C310
DP80C511
DP80C512
Target
SC
SC
Clock
frequency
Dhry/sec
(VAX MIPS)
12 MHz
33 MHz
120 MHz
120 MHz
268 (0.153)
1550 (0.882)
9223 (5,250)
20980 (11.939)
Core performance in terms of Dhrystones
20980
22000
20000
18000
16000
14000
9223
12000
10000
8000
6000
1550
4000
268
2000
0
80C51 (12MHz)
80C310 (33MHz)
DP80C51 - external program memory (120MHz)
DP80C51 - internal program memory (120MHz)
An area utilized by the each unit of the DP80C51
core in vendor specific technologies is summarized
in the table below.
Component
Area
[LUT4s]
[FFs]
CPU*
Interrupt Controller
Power Management Unit
I/O ports
Timers
UART0
1740
165
12
118
185
250
310
40
5
35
50
60
Total area
2470
500
Core components area utilization in EC and ECP families
*CPU – consisted of ALU, Opcode Decoder, Control Unit,
Program & Internal & External Memory Interfaces, User SFRs
Interface
6
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
PERFORMANCE
The following tables give a survey about the Core
area and performance in ASIC Devices (CPU features and peripherals included):
Device
Optimization
0.25u typical
area
0.25u typical
speed
Core performance in ASIC devices
Fmax
100 MHz
250 MHz
For the user, the most important aspect is an application speed improvement. The most commonly
used arithmetic functions and their improvement,
are shown in the table below. The improvement
was computed as {80C51 clock periods}, divided by
{DP80C51 clock periods}, required to execute
an identical function for code, executed from internal (first column) and external (second column)
program memory. More details are available
in the core documentation.
Function
Improvement
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
9,00
9,00
9,00
12,00
9,00
9,00
9,00
12,00
16,00
9,60
12,00
12,00
13,60
12,00
12,00
12,60
11,12
3,00
3,00
3,60
4,00
3,00
3,00
3,60
4,00
6,00
4,80
4,00
4,00
5,47
4,00
4,00
4,89
4,03
Dhrystone Benchmark Version 2.1 was used
to measure the Core performance. The following
table gives a survey about the DP80C51 performance in terms of Dhrystone/sec and VAX MIPS
rating for testing code executed from external (1)
and internal (2) program memory.
Device
80C51
80C310
DP80C511
DP80C512
Clock
Dhry/sec
frequency
(VAX MIPS)
12 MHz
268 (0.153)
33 MHz
1550 (0.882)
0.25u
250 MHz
19215 (10,938)
0.25u
250 MHz
43700 (24.872)
Core performance in terms of Dhrystones
43700
48000
44000
40000
36000
32000
28000
19215
24000
20000
16000
12000
8000
268 1550
4000
0
80C51 (12MHz)
80C310 (33MHz)
DP80C51 - external program memory (250MHz)
DP80C51 - internal program memory (250MHz)
An area utilized by each unit of the DP80C51 core
in vendor specific technologies is summarized
in the table below.
Area
[Gates]
[FFs]
CPU*
6100
310
Interrupt Controller
450
40
Power Management Unit
50
5
I/O ports
400
35
Timers
550
50
UART0
650
60
Total area
8200
500
*CPU – consisted of ALU, Opcode Decoder, Control Unit,
Program & Internal & External Memory Interfaces, User SFRs
Interface
Core components area utilization
Component
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