ASIC Datasheet

2016
D6802 IP Core
8-bit Microprocessor v. 1.01
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on over 70 different architectures, starting from serial interfaces to
advanced microcontrollers and SoCs, we are designing solutions tailored to your needs.
IP CORE OVERVIEW
This document contains a brief description of the
D6802 core functionality. The D6802 is an 8-bit
MCU IP Core. It is binary-compatible with the industry standard MC6802 8-bit microprocessor.
Two software-controlled power-saving modes WAIT and HALT are available, to conserve additional power. These modes make the D6802 IP
Core especially attractive for automotive and battery-driven applications. The D6802 is fully customizable - it is delivered in an exact configuration
to meet user’s requirements. It includes fully automated test bench with complete set of tests,
allowing easy package validation at each stage
of SoC design flow.
● De-multiplexed Address/Data Bus, to allow easy
connection to memory
● Two power saving modes: HALT, WAIT
● No internal reset generator or gated clock
● Scan test ready
● Technology independent HDL source code
● Core can be fully customized
TM
● DoCD - Hardware On-Chip Debugger
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use.
There are two formats of the delivered IP Core:
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
DELIVERABLES
♦
Source code:
●
●
●
♦
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
●
●
●
♦
Technical documentation
One global system clock
Synchronous reset
All asynchronous input signals are synchronized
before internal use
IP Core implementation support
3 months maintenance
●
●
PINS DESCRIPTION
PIN
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
●
●
♦
♦
♦
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
●
●
●
♦
♦
♦
DESIGN FEATURES
Delivery of the IP Core and documentation updates, minor
and major versions changes
Phone & email support
CPU FEATURES
● Cycle compatible with an original implementation
● Software compatible with the MC6802 industry
standard
● Up to 256 bytes of Data Memory
TYPE
DESCRIPTION
clk
reset
halt
xdatai
iramdatai
irq
nmi
re
mr
addr
datao
rw
iramoe
iramwe
vma
ba
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output
output
Global system clock
Reset input
Halt clock system
External memory bus input
Internal RAM bus input
Interrupt input
Non-maskable interrupt
Internal RAM enable input
Memory ready input
Common address bus
Data bus output
External RAM read/write
Internal RAM OE
Internal RAM WE
Valid memory address
Bus available output
clkdocd
docddatai
docddatao
docdclk
input
input
output
output
Separate DoCDTM clock
DoCDTM Serial Data input
DoCDTM Serial Data Output
DoCDTM Serial Clock Output
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
PROCESSOR FAMILY OVERVIEW
READY for Prg. And
Data memories
Compare\Capture
Main Timer System
2
2
2
2
-
-
-
-
-
DF6805
4.1
64k
64k
-
7
7
-
-
*
2/2*
1*
D68HC05
1.0
64k
64k
-
7
7
-
-
*
2/2*
1*
DF6808
3.2
64k
64k
-
7
7
-
-
*
2/2*
1*
D68HC08
1.0
64k
64k
-
7
7
-
-
*
2/2*
D68HC11E
1.0
64k
64k
-
20
17
1*
*
D68HC11F
1.0
64K
64K
-
20
17
1*
D68HC11KW1
1.0
1M
1M
25
22
1*
D68HC11K
1.0
1M
1M
20
17
DF6811E
4.4
64k
64k
-
20
17
DF6811F
4.4
64k
64k
-
20
17
DF6811K
4.4
1M
1M
-
-
-
-
-
-
*
4
+
*
4
+
*
4
1*
*
4
5/3*
1*
*
4
12 000
*
5/3*
1*
*
7
13 500
*
13/6*
3*
*
10
21 000
1*
*
5/3*
2*
*
7
16 000
1*
*
5/3*
1*
*
4
*
*
*
12 000
1*
*
5/3*
1*
*
4
*
*
*
13 000
20
17
1*
*
5/3*
2*
7
*
D68HCXX family of High Performance Microcontroller Cores
+ optional
* configurable
DoCD Debugger
Size – ASIC gates
Interface for
additional SFRs
Data Pointers
-
Pulse accumulator
Real Time Interrupt
64k
64k
64k
Watchdog Timer
Interrupt levels
64k
64k
64k
SPI M/S Interface
Interrupt sources
1
1
1
I\O Ports
Physical Linear
memory space
D6802
D6803
D6809
Design
SCI (UART)
Speed acceleration
Paged Data Memory
space
Motorola Memory
Expansion Logic
The main features of each D68HCXX and DF68XX family member have been summarized in the table below.
It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You
can specify your own peripheral set (including listed above and the others) and request the core modifications.
3 900
6 000
9 000
*
-
6 700
*
-
6 700
*
-
8 900
*
-
8 900
16 000
TM
UNITS SUMMARY
Control Unit - Performs the core synchronization
and data flow control. This module manages execution of all instructions. The Control Unit also
manages HALT input pin events.
Opcode Decoder - Performs an instruction opcode
decoding and the control functions for all other
blocks.
ALU - Arithmetic Logic Unit performs the arithmetic and logic operations, during execution of an
instruction. It contains accumulator (A, B), Condition Code Register (CCREG), Index register X and
related logic, like arithmetic unit, logic unit, multiplier and divider.
Bus Controller – Program Memory, Data Memory
interface controls access into the program and
data memories. It contains Program Counter (PC),
Stack Pointer (SP) register, and related logic.
Interrupt Controller - The interrupt requests may
come from external pins (IRQ and NMI) as well as
from particular peripherals.
DoCD - Debug Unit – it’s a real-time hardware
debugger, which provides debugging capability
of a whole SoC system. Unlike other on-chip debuggers, DoCD™ provides non-intrusive debugging
of running application. It can halt, run, step into
or skip an instruction, read/write any contents
of microcontroller, including all registers, internal,
external, program memories, all SFRs, including
user defined peripherals. Hardware breakpoints
can be set and controlled on program memory,
internal and external data memories, as well as on
SFRs. Hardware breakpoint is executed, if any
write/read occurs at particular address, with cerTM
tain data pattern or without pattern. The DoCD
system includes three-wire interface and complete
set of tools, to communicate and work with core in
real time debugging. It is built as scalable unit and
some features can be turned off by the user, to
save silicon and reduce power consumption. When
debugger is not used, it is automatically switched
to power save mode. Finally, when debug option is
no longer used, whole debugger is turned off.
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
BLOCK DIAGRAM
clk
reset
datao
addr
Opcode
Decoder
xdatai
rw
halt
Control
Unit
irq
nmi
Interrupt
Controller
clkdocd
docddatai
docddatao
docdclk
DoCD
Debugger
TM
Bus
Control
iramdatai
iramwe
iramoe
vma
ba
mr
re
ALU
PERFORMANCE
The following table gives a survey about the Core
area and performance in ASIC devices (all key features included):
Technology
0.18 typical
0.18 typical
Optimization
Gates
area
3 600
speed
3 800
Core components area utilization
Fmax
100 MHz
200 MHz
CONTACT
Digital Core Design Headquarters:
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
tel.:
fax:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
Distributors:
Please check:
http://dcd.pl/sales
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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