ASIC Datasheet

2016
D6803 IP Core
8-bit Microprocessor v. 1.01
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on over 70 different architectures, starting from serial interfaces to
advanced microcontrollers and SoCs, we are designing solutions tailored to your needs.
DESIGN FEATURES
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One global system clock
Synchronous reset
All asynchronous input signals are synchronized
before internal use
CPU FEATURES
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Software compatible with 6803 industry standard
Cycle compatible with original implementation
Power saving mode: WAIT
Fully synthesizable, static synchronous design with
no internal tri-states
Scan test ready
TM
DoCD - Hardware On-Chip Debugger
IP CORE OVERVIEW
This document contains brief description of the
D6803 core functionality. The D6803 is
an advanced 8-bit MCU IP Core, with highly sophisticated on-chip peripheral capabilities. In a standard configuration, the core has integrated on-chip
major peripheral functions. An asynchronous serial
communications interface (SCI) is included. The
main 16-bit three programmable timers have three
input capture and five output-compare lines.
A software-controlled power-saving mode - WAIT
is available, to conserve additional power.
This mode makes the D6803 IP Core especially
attractive for automotive and battery-driven applications. The D6803 has a built-in real time hardTM
ware on-chip debugger - DoCD . It allows easy
software debugging and validation. The D6803 is
fully customizable - it is delivered in an exact configuration to meet users’ requirements. It includes
fully automated test bench with complete set of
tests, allowing easy package validation at each
stage of SoC design flow.
PERIPHERALS
The peripherals listed below are implemented in a
standard configuration of the D6803.
TM
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DoCD
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On-Chip Debugger
Processor execution control
Read, write all processor contents
Hardware execution breakpoints
Three 8-bit and one 5-bit I/O Ports
Extended Interrupt Controller
Main16-bit timer/counter system
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16 bit free running counter
Compare/Capture functions
Timer clocked by internal source
Full-duplex UART - SCI
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Standard Non-return to Zero format (NRZ)
Integrated baud rate generator
Enhanced receiver data sampling technique
Overrun and Framing error detection
Wake-up block to recognize UART wake-up from IDLE
Three SCI related interrupts
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use.
There are two formats of the delivered IP Core:
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
PINS DESCRIPTION
PIN
clk
rst
irq
nmi
portxi
rxd
e
rw
as
portxo
txd
clkdocd
ocddatai
cddatao
docdclk
TYPE
input
input
input
input
input
input
output
output
output
output
output
input
input
output
output
DESCRIPTION
Global system clock
Power on reset vector fetch
Interrupt input
Non-maskable interrupt input
Port A,B,C, D inputs
SCI receiver data input
Clock bus synchronization
Memory read/write output
Address strobe
Port A,B,C, D outputs
SCI transmitter data output
DoCDTM clock input
DoCDTM serial Data input
DoCDTM Serial Data Output
DoCDTM Serial Clock Output
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
MICROCONTROLLERS FAMILY OVERVIEW
Real Time Interrupt
Data Pointers
READY for Prg. And
Data memories
Compare\Capture
Main Timer System
2
2
2
2
-
-
-
-
-
DF6805
4.1
64k
64k
-
7
7
-
-
*
2/2*
1*
D68HC05
1.0
64k
64k
-
7
7
-
-
*
2/2*
1*
DF6808
3.2
64k
64k
-
7
7
-
-
*
2/2*
1*
D68HC08
1.0
64k
64k
-
7
7
-
-
*
2/2*
D68HC11E
1.0
64k
64k
-
20
17
1*
*
D68HC11F
1.0
64K
64K
-
20
17
1*
D68HC11KW1
1.0
1M
1M
25
22
1*
D68HC11K
1.0
1M
1M
20
17
DF6811E
4.4
64k
64k
-
20
17
DF6811F
4.4
64k
64k
-
20
DF6811K
4.4
1M
1M
20
-
-
-
-
-
-
*
4
+
*
4
+
*
4
1*
*
4
5/3*
1*
*
4
12 000
*
5/3*
1*
*
7
13 500
*
13/6*
3*
*
10
21 000
1*
*
5/3*
2*
*
7
16 000
1*
*
5/3*
1*
*
4
*
*
*
12 000
17
1*
*
5/3*
1*
*
4
*
*
*
13 000
17
1*
*
5/3*
2*
DoCD Debugger
Size – ASIC gates
Interface for
additional SFRs
Interrupt levels
-
Pulse accumulator
Interrupt sources
64k
64k
64k
Watchdog Timer
Motorola Memory
Expansion Logic
64k
64k
64k
SPI M/S Interface
Paged Data Memory
space
1
1
1
I\O Ports
Physical Linear
memory space
D6802
D6803
D6809
Design
SCI (UART)
Speed acceleration
The main features of each D68HCXX and DF68XX family member have been summarized in the table below.
It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You
can specify your own peripheral set (including listed above and the others) and request the core modifications.
3 900
6 000
9 000
*
-
6 700
*
-
6 700
*
-
8 900
*
-
8 900
7
*
D68HCXX family of High Performance Microcontroller Cores
16 000
+ optional | * configurable
BLOCK DIAGRAM
DELIVERABLES
♦
clk
rst
e
Opcode
Decoder
Control
Unit
irq
nmi
rxd
txd
portai
portci
portdi
portei
I/O
Ports
ALU
♦
rw
Interrupt
Controller
SCI Unit
portao
portbo
portco
portdo
♦
as
♦
♦
♦
Timer with
Compare
Capture
TM
DoCD
Debugger
clkdocd
docddatai
docddatao
docdclk
Source code:
● VHDL Source Code or/and
● VERILOG Source Code or/and
● Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
● Active-HDL automatic simulation macros
● ModelSim automatic simulation macros
● Tests with reference responses
Technical documentation
● Installation notes
● HDL core specification
● Datasheet
Synthesis scripts
Example application
Technical support
● IP Core implementation support
● 3 months maintenance
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Delivery of the IP Core and documentation updates,
minor and major versions changes
Phone & email support
UNITS SUMMARY
Control Unit - Performs the core synchronization and
data flow control. This module manages execution of all
instructions.
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks.
ALU - Arithmetic Logic Unit performs the arithmetic and
logic operations during execution of an instruction. It
contains accumulator (A, B), Condition Code Register
(CCREG), Index register X and related logic like arithmetic
unit, logic unit, multiplier and divider.
Bus Controller – Program Memory, Data Memory interface controls access into the program and data memories. It contains Program Counter (PC), Stack Pointer (SP)
register, and related logic.
Interrupt Controller – Interrupt Control module is responsible for the interrupt manage system for the external & internal interrupts and exceptions processing. It
manages auto-vectored interrupt cycles, priority resolving and correct vector number creation.
Timer with Compare Capture - The programmable timer
is based on free-running 16-bit counter, plus input capture/output compare circuitry. The timer can be used for
many purposes, including measuring pulse length of two
input signals and generating two output signals. The
timer has 16-bit architecture hence each specific functional segment is represented by two 8-bit registers.
These registers contain the high and low byte of that
functional block. Accessing the low byte of a specific
timer function, allows full control of that function, however, an access of the high byte, inhibits that specific
timer function until the byte is also accessed. The inputcapture channel has its own 16-bit time capture latch
(input-capture register) and the output-compare channel
has its own 16-bit compare register. Additional control
bits permit software to control the edge(s), that trigger
each input-capture function and the automatic actions
that result from output-compare functions. Although
hardwired logic is included to automate many timer
activities, this timer architecture is mainly a softwareoriented system. This structure is easily adaptable to a
very wide range of applications, although it is not
as efficient, as a dedicated hardware for some specific
timing applications.
SCI - The SCI is a full-duplex UART type asynchronous
system, using standard non-return to zero (NRZ) format:
1 start bit and a 1 stop bit. The Core resynchronizes the
receiver bit clock on all one to zero transitions in the bit
stream. Therefore, differences in baud rate between the
sending device and the SCI are not as likely to cause
reception errors. Three logic samples are taken near the
middle of data bit time and majority logic decides the
sense for the bit. The receiver also has the ability to
enter a temporary standby mode (called receiver
wakeup), to ignore messages intended for a different
receiver. Logic automatically wakes the receiver up, in
time to see the first character of the next message. This
wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce
queued characters of idle (whole characters of all logic 1)
and break (whole characters of all logic 0). In addition to
the usual transmit data register empty (TDRE) status flag.
I/O Ports - Three ports are 8-bit general-purpose bidirectional I/O system and one (PORTB) is 5-bit. The PORTA,
PORTB, PORTC, PORTD data registers, have their corresponding data direction registers DDRA, DDRB, DDRC,
DDRD to control ports data flow. It assures that all
D6803’s ports have full I/O selectable registers. Writes to
any ports pins cause data to be stored in the data registers. If any port pins are configured as output, then data
registers are driven out of those pins. Reads from port
pins configured as input, causes that input pin is read. If
port pins is configured as output, during read data register is read. Writes to any ports pins not configured as
outputs, do not cause data to be driven out of those
pins, but the data is stored in the output registers. Thus,
if the pins later become outputs, the last data written
to port, will be driven out the port pins.
TM
DoCD - Debug Unit – it’s a real-time hardware debugger, which provides debugging capability of a whole SoC
system. Unlike other on-chip debuggers, DoCD™ provides non-intrusive debugging of running application. It
can halt, run, step into or skip an instruction, read/write
any contents of microcontroller, including all registers,
internal, external, program memories, all SFRs, including
user defined peripherals. Hardware breakpoints can be
set and controlled on program memory, internal and
external data memories, as well as on SFRs. Hardware
breakpoint is executed, if any write/read occurs
at particular address, with certain data pattern
TM
or without pattern. The DoCD system includes threewire interface and complete set of tools,
to communicate and work with core in real time debugging. It is built as scalable unit and some features can be
turned off by the user, to save silicon and reduce power
consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug
option is no longer used, whole debugger is turned off.
The separate CLKDOCD clock line allows the debugger to
operate while the CPU is in STOP mode and the major
clock line CLK is stopped.
OPTIONAL PERIPHERALS
Optional peripherals (not included in the presented
D6803 Core) are also available. The optional peripherals can be implemented upon customer’s
request.
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ADC Support
Ethernet MAC Controller
CAN, LIN Controllers
I2C bus controller - Master
I2C bus controller - Slave
PWM – Pulse Width Modulation Timer
Fixed-Point arithmetic coprocessor
Floating-Point arithmetic coprocessor IEEE-754
standard single precision
CONTACT
Digital Core Design Headquarters:
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
tel.:
fax:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
Distributors:
Please check:
http://dcd.pl/sales
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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