2016
DF6805 IP Core
8-bit Fast Microcontroller v. 1.06
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
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DESIGN FEATURES
IP CORE OVERVIEW
The following document contains a brief description of the DF6805 core functionality. The DF6805
is an advanced 8-bit MCU IP Core, with highly sophisticated, on-chip peripheral capabilities. The
DF6805 soft core is binary-compatible with the
industry standard 68HC05 8-bit microcontroller
and can achieve a performance of 45-100 million
instructions per second. The DF6805 has a FAST
architecture which is 4.1 times faster, compared
to the original implementation. In the standard
configuration, the core has integrated on-chip
major peripheral functions. The DF6805 Microcontroller Core contains full-duplex UART (Asynchronous serial communications interface (SCI) and can
also be equipped with the Synchronous Serial Peripheral Interface SPI. The main 16-bit, freerunning timer system has implemented two input
capture lines and two output-compare lines. Selfmonitoring circuitry is included on-chip, to protect
against system errors. A computer operating
properly (COP) watchdog system protects against
software failures. An illegal opcode detection circuit provides a non-maskable interrupt, if illegal
opcode is detected. Two software-controlled power-saving modes - WAIT and STOP are available, to
conserve additional power. These modes make the
DF6805 IP Core especially attractive for automotive
and battery-driven applications. The DF6805 is
fully customizable - it is delivered in the exact
configuration to meet user’s requirements. It includes fully automated test bench with complete
set of tests, allowing easy package validation at
each stage of SoC design flow.
CPU FEATURES
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FAST architecture, 4.1 times faster than the original implementation
Software compatible with the 68HC05 industry
standard
64 bytes of System Function Registers space (SFRs)
Up to 64k bytes of Program Memory
Up to 64k bytes of Data Memory
De-multiplexed Address/Data Bus to allow easy
connection to memory
Two power saving modes: STOP, WAIT
Ready pin allows Core to operate with slow program and data memories
Fully synthesizable, static synchronous design with
no internal tri-states
No internal reset generator or gated clock
Scan test ready
Technology independent HDL source code
Core can be fully customized
1 GHz virtual clock frequency compared to original
implementation
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One global system clock
Synchronous reset
All asynchronous input signals are synchronized
before internal use
PERIPHERALS
The peripherals listed below are implemented in
standard configuration of DF6805.
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TM
DoCD On-Chip Debugger
○ Processor execution control
○ Read, write all processor contents
○ Hardware execution breakpoints
○ Three wire communication interface
Four 8-bit I/O Ports
Interrupt Controller
○ 7 interrupt sources
○ 7 priority levels
○ Dedicated Interrupt vector for each interrupt source
Main16-bit timer/counter system
○ 16 bit free running counter
○ Timer clocked by internal source
16-bit Compare/Capture Unit
○ Two independent input-capture functions
○ Two output-compare channels
○ Events capturing
○ Pulses generation
○ Digital signals generation
○ Gated timers
○ Sophisticated comparator
○ Pulse width modulation
○ Pulse width measuring
Full-duplex UART - SCI
○ Standard Non-return to Zero format (NRZ)
○ 8 or 9 bit data transfer
○ Integrated baud rate generator
○ Noise, Overrun and Framing error detection
○ IDLE and BREAK characters generation
○ Wake-up block to recognize UART wake-up from IDLE
condition
○ Three SCI related interrupts
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
DELIVERABLES
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Source code:
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VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
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Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
Technical documentation
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In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use. There are two formats of the delivered IP
Core:
Installation notes
HDL core specification
Datasheet
PINS DESCRIPTION
Synthesis scripts
Example application
Technical support
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IP Core implementation support
3 months maintenance
● Delivery of the IP Core and documentation updates, minor
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and major versions changes
Phone & email support
IMPROVEMENT
From the user’s point of view, the most important
is application speed improvement. The most commonly used arithmetic functions and theirs improvement are shown in table on the right. Improvement was computed as {M68HC05 clock
periods}, divided by {DF6805 clock periods} required to execute an identical function. More details are available in the core documentation.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
16-bit addition (immediate data)
16-bit addition (direct addressing)
16-bit addition (indirect addressing
16-bit subtraction (immediate data)
16-bit subtraction (direct addressing)
16-bit subtraction (indirect addressing
Multiplication
Division
Improvement
4
4
3,6
4
4
3,6
4
4
3,6
4
4
3,6
5
5
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
PIN
TYPE
DESCRIPTION
clk
input
Global system clock
rst
input
Global system reset
prgdata[7:0]
input
Program memory bus input
datai[7:0]
input
Memory bus input
ufrdatai[7:0]
input
UFRs data bus input
ready
input
Code and Data memory Ready
irq
input
Interrupt input
portxi[7:0]
input
Port A, B, C, D input
cap1,2
input
Capture inputs
rxd
input
SCI receiver data input
clkdocd
input
DoCDTM clock input
docddatai
input
DoCDTM serial Data input
prgaddr[15:0]
output
Program memory address bus
prgoe
output
Program memory output enable
datao[7:0]
output
Data memory & UFR bus output
addr[15:0]
output
Data memory address bus
ramwe
output
Data memory write enable
ramoe
output
Data memory output enable
ufraddr[5:0]
output
UFR’s address bus
ufrwe
output
UFRs write enable
ufroe
output
UFRs output enable
halt
output
Halt clock system (STOP inst.)
portxo[7:0]
output
Port A, B, C, D output
ddrx[7:0]
output
Port X data direction control
cmp1,2
output
Compare outputs
txd
output
SCI transmitter data output
docddatao
output
DoCDTM Serial Data Output
docdclk
output
DoCDTM Serial Clock Output
* The kind of activity is configurable
OPTIONAL PERIPHERALS
Optional peripherals (not included in the presented
DF6805 Core) are also available. The optional peripherals can be implemented upon customer’s
request.
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ADC - support
I2C bus controller - Master
I2C bus controller - Slave
PWM – Pulse Width Modulation Timer
Fixed-Point arithmetic coprocessor
Floating-Point arithmetic coprocessor IEEE-754
standard single precision
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
MICROCONTROLLERS OVERVIEW
Real Time Interrupt
Data Pointers
READY for Prg. and
Data memories
Compare\Capture
Main Timer System
2
2
2
2
-
-
-
-
-
DF6805
4.1
64k
64k
-
7
7
-
-
*
2/2*
1*
D68HC05
1.0
64k
64k
-
7
7
-
-
*
2/2*
1*
DF6808
3.2
64k
64k
-
7
7
-
-
*
2/2*
1*
D68HC08
1.0
64k
64k
-
7
7
-
-
*
2/2*
D68HC11E
1.0
64k
64k
-
20
17
1*
*
D68HC11F
1.0
64K
64K
-
20
17
1*
D68HC11KW1
1.0
1M
1M
25
22
1*
D68HC11K
1.0
1M
1M
20
17
DF6811E
4.4
64k
64k
-
20
17
DF6811F
4.4
64k
64k
-
20
DF6811K
4.4
1M
1M
20
-
-
-
-
-
-
*
4
+
*
4
+
*
4
1*
*
4
5/3*
1*
*
4
12 000
*
5/3*
1*
*
7
13 500
*
13/6*
3*
*
10
21 000
1*
*
5/3*
2*
*
7
16 000
1*
*
5/3*
1*
*
4
*
*
*
12 000
17
1*
*
5/3*
1*
*
4
*
*
*
13 000
17
1*
*
5/3*
2*
7
*
D68HCXX family of High Performance Microcontroller Cores
DoCD Debugger
Size – ASIC gates
Interface for
additional SFRs
Interrupt levels
-
Pulse accumulator
Interrupt sources
64k
64k
64k
Watchdog Timer
Motorola Memory
Expansion Logic
64k
64k
64k
SPI M/S Interface
Paged Data
Memory space
1
1
1
I\O Ports
Physical Linear
memory space
D6802
D6803
D6809
Design
SCI (UART)
Speed acceleration
The main features of each D68HCXX and DF68XX family member have been summarized in the table below. It
gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You
can specify your own peripheral set (including listed above and the others) and request the core modifications.
3 900
6 000
9 000
*
-
6 700
*
-
6 700
*
-
8 900
*
-
8 900
16 000
+ optional
* configurable
UNITS SUMMARY
Control Unit - Performs the core synchronization
and data flow control. This module manages execution of all instructions. The Control Unit also
manages execution of STOP instruction and wakesup the processor from the STOP mode.
Opcode Decoder - Performs an instruction opcode
decoding and the control functions for all other
blocks.
ALU - Arithmetic Logic Unit performs the arithmetic and logic operations, during execution of an
instruction. It contains accumulator (A), Condition
Code Register (CCREG), Index registers (X) and
related logic like arithmetic unit, logic unit and
multiplier.
Bus Controller – Program Memory, Data Memory
& SFR’s (Special Function Register) interface - controls access into the program and data memories
and special registers. It contains Program Counter
(PC), Stack Pointer (SP) register and related logic.
Interrupt Controller - DF6805 extended IC has
implemented 7-level interrupt priority control. The
interrupt requests may come from external pin
(IRQ), as well as from particular peripherals. The
DF6805 peripheral systems generate maskable
interrupts, which are recognized only if the global
interrupt mask bit (I) in the CCR is cleared. Maskable interrupts are prioritized, according to default
arrangement established during reset. When interrupt condition occurs, an interrupt status flag is
set, to indicate the condition.
I/O Ports - All ports are 8-bit general-purpose bidirectional I/O system. The PORTA, PORTB, PORTC,
PORTD data registers have their corresponding
data direction registers DDRA, DDRB, DDRC, DDRD,
to control ports data flow. It assures that all
DF6805’s ports have full I/O selectable registers.
Writes to any ports pins cause data to be stored in
the data registers. If any port pins are configured
as output, then data registers are driven out of
those pins. Reads from port pins configured as
input, causes that input pin is read. If port pins is
configured as output, during read data register is
read. Writes to any ports pins, not configured as
outputs, do not cause data to be driven out of
those pins, but the data is stored in the output
registers. Thus, if the pins later become outputs,
the last data written to port will be driven out the
port pins.
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
Timer & Compare - The programmable timer is
based on free-running 16-bit counter, with a fixed
divide by four prescaler, plus input capture/output
compare circuitry. The timer can be used for many
purposes, including measuring pulse length of two
input signals and generating two output signals.
The timer has 16-bit architecture hence each specific functional segment is represented by two 8-bit
registers. These registers contain the high and low
byte of that functional block. Accessing the low
byte of a specific timer function, allows full control
of that function, however, an access of the high
byte inhibits that specific timer function, until the
byte is also accessed. Each of the input-capture
channel has its own 16-bit time capture latch (input-capture register) and each of the outputcompare channel, has its own 16-bit compare register. Additional control bits permit software to
control the edge(s) that trigger each input-capture
function and the automatic actions that result from
output-compare functions. Although hardwired
logic is included to automate many timer activities,
this timer architecture is mainly a softwareoriented system. This structure is easily adaptable
to a very wide range of applications, although for
some specific timing applications, it is not as efficient, as a dedicated hardware.
Watchdog Timer - The Watchdog Timer consist of
13
a free running Timer CLK/2 and control logic. The
Watchdog Timer can be enabled by software, by
writing ‘1’ to the WDOG bit in MISC register
($000C). Once enabled, the WDT Timer cannot be
disabled by software. In addition, the WDOG bit
acts as a reset mechanism for the WDT Timer.
Writing logic one ‘1’ to the WDOG bit, clears
Watchdog counter and inhibits Watchdog timeout
SCI - The SCI is a full-duplex UART type, asynchronous system, using standard non return to zero
(NRZ) format: 1 start bit, 8 or 9 data bits and a 1
stop bit. The DF6805 resynchronizes the receiver
bit clock on all one to zero transitions in the bit
stream. Therefore, differences in baud rate, between the sending device and the SCI, are not as
likely to cause reception errors. Three logic samples are taken near the middle of data bit time and
majority logic decides the sense for the bit. For the
start and stop bits, seven logic samples are taken.
Even if noise causes one of these samples to be
incorrect, the bit will still be received correctly. The
receiver also has the ability, to enter a temporary
standby mode (called receiver wakeup), to ignore
messages intended for a different receiver. Logic
automatically wakes the receiver up, in time to see
the first character of the next message. This
wakeup feature greatly reduces CPU overhead
in multi-drop SCI networks. The SCI transmitter can
produce queued characters of idle (whole characters of all logic 1) and break (whole characters of
all logic 0). In addition to the usual transmit data
register empty (TDRE) status flag, this SCI also
provides a transmit complete (TC) indication, that
can be used in applications with a modem.
TM
DoCD - Debug Unit – it’s a real-time hardware
debugger, which provides debugging capability
of a whole SoC system. Unlike other on-chip debuggers, DoCD™ provides non-intrusive debugging
of running application. It can halt, run, step into
or skip an instruction, read/write any contents
of microcontroller, including all registers, internal,
external, program memories, all SFRs, including
user defined peripherals. Hardware breakpoints
can be set and controlled on program memory,
internal and external data memories, as well as on
SFRs. Hardware breakpoint is executed, if any
write/read occurs at particular address, with cerTM
tain data pattern or without pattern. The DoCD
system includes three-wire interface and complete
set of tools, to communicate and work with core in
real time debugging. It is built as scalable unit and
some features can be turned off by the user, to
save silicon and reduce power consumption. When
debugger is not used, it is automatically switched
to power save mode. Finally, when debug option is
no longer used, whole debugger is turned off.
BLOCK DIAGRAM
clk
rst
ready
Opcode
Decoder
halt
Control
Unit
irq
Interrupt
Controller
BUS
Controller
ufraddr
ufrwe
ufroe
ALU
Watchdog
Timer
rxd
txd
clkdocd
docddatai
docddatao
docdclk
I/O
Ports
SCI Unit
TM
DoCD
Debugger
prgdata
prgaddr
prgoe
datai
datao
addr
ramwe
ramoe
Timer
with
Compare /
Capture
Unit
portai
portbi
portci
portdi
portao
portbo
portco
portdo
ddra
ddrb
ddrc
ddrd
cap1
cap2
cmp1
cmp2
4
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
PERFORMANCE
The following table gives a survey about the Core
area and performance in ALTERA® devices after
Place & Route:
Device
CYCLONE
STRATIX
MERCURY
APEX II
APEX20KC
APEX20KE
ACEX1K
FLEX10KE
Speed grade
Logic Cells
-6
1689
-5
1690
-5
1671
-7
1850
-7
1698
-1
1698
-1
1739
-1
1739
Core performance in ALTERA® devices
Fmax
79 MHz
83 MHz
85 MHz
63 MHz
55 MHz
47 MHz
41 MHz
41 MHz
Area utilized by the each unit of DF6805 core in
vendor specific technologies is summarized in the
next table.
Area
Component
[LC]
[FFs]
CPU*
1134
153
Main Timer
110
55
COM/CAP
150
60
Watchdog
29
14
UART - SCI
272
124
I/O Ports
161
64
Total area
1856
470
*CPU – consisted of ALU, Control Unit and Instruction Decoder, Bus Controller with support for 64KB RAM, External IRQ
pin Interrupt Controller
Core components area utilization
CONTACT
Digital Core Design Headquarters:
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
[email protected]
tel.:
0048 32 282 82 66
fax:
0048 32 282 74 37
Distributors:
Please check:
http://dcd.pl/sales
5
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.