ASIC Datasheet

2016
DUSB2 IP Core
USB 2.0 device controller v. 3.02
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
IP CORE OVERVIEW
The DUSB2 is a hardware implementation
of a full/high-speed peripheral controller that interfaces to an UTMI bus transceiver. The DUSB2
contains a USB PID and address recognition logic,
state machines to handle USB packets and transactions, endpoints number recognition logic and
endpoints FIFO control logic. The DUSB2 is designed to support 12 Mb/s "Full Speed" (FS) and
480 Mb/s "High Speed" (HS) serial data transmission rates. The design is technology independent
and thus can be implemented in a variety of process technologies. This core strictly conforms to
the USB Specification v 2.0. It is delivered with fully
automated test bench and complete set of tests,
allowing easy package validation at each stage of
SoC design flow.
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CONFIGURATION
At the synthesis level, the following parameters
of the DUSB2 core can be easily adjusted to requirements of a dedicated application and technology. The CPU interface is configurable as 8, 16
or 32-bit wide. Each data endpoint can be effortlessly enabled and disabled, by simply changing an
appropriate constant in the package file. There is
no need to change any parts of the code, to prepare DUSB2 core with requested number of data
endpoints.
APPLICATIONS
● Human Interface Devices like keyboards, mousses or
game peripherals
● Mass Storage devices like flash disks, mp3 or mp4
players
● GPS navigation systems
● Digital Cameras
● Cellular phones
● Audio devices like microphones and speakers
● Printers
● Scanners
MAIN FEATURES
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Full compliance with the USB 2.0 specification
Full-speed 12 Mbps operation
High-speed 480 Mbps operation
Software configurable EP0 control endpoint size 8-64
bytes
● Software configurable 15 IN/OUT endpoints
○ double buffering
○ configurable number of endpoints
○ configurable type of each endpoint: INTERRUPT,
○ configurable size of each endpoint: 8-1024 bytes
Supports UTMI Transceiver Macrocell Interface
Synchronous RAM interface for FIFOs
Suspend and resume power management functions
Simple interface allows easy connection to 8, 16, 32bit CPU
Allows operation from a wide range of CPU clock
frequencies
Fully synthesizable
Static synchronous design
Positive edge clocking
No internal tri-states
Scan test ready
 EP1_ENABLE
- TRUE (1) / FALSE (0)
 EP2_ENABLE
- TRUE (1) / FALSE (0)
 EP3_ENABLE
- TRUE (1) / FALSE (0)
 EP4_ENABLE
- TRUE (1) / FALSE (0)
 EP5_ENABLE
- TRUE (1) / FALSE (0)
 EP6_ENABLE
- TRUE (1) / FALSE (0)
 EP7_ENABLE
- TRUE (1) / FALSE (0)
 EP8_ENABLE
- TRUE (1) / FALSE (0)
 EP9_ENABLE
- TRUE (1) / FALSE (0)
 EP10_ENABLE - TRUE (1) / FALSE (0)
 EP11_ENABLE - TRUE (1) / FALSE (0)
 EP12_ENABLE - TRUE (1) / FALSE (0)
 EP13_ENABLE - TRUE (1) / FALSE (0)
 EP14_ENABLE - TRUE (1) / FALSE (0)
 EP15_ENABLE - TRUE (1) / FALSE (0)
Besides synthesis level configuration parameters
mentioned above, there is a portion of device
and endpoints parameters, configured at software
level, after the USB bus reset condition. The following parameters can be configured at software level:
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Endpoint 0 FIFO size to 8, 16, 32 or 64 bytes
Endpoints 1-15 FIFO size to 8, 16, 32, 64, 128, 256,
512 or 1024 bytes
Endpoints 1-15 direction to IN or OUT
Endpoints 1-15 mode to INTERRUPT, BULK or ISOCHRONOUS
BULK or ISOCHRONOUS
○ configurable direction of each endpoint
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
LICENSING
DELIVERABLES
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
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Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
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Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
♦
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use.
There are two formats of the delivered IP Core:
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
cpuclk
input
CPU clock
cpuaddress(7:0)
input
CPU address bus
cpudatai(CS-1:0)
input
CPU data input bus
cpuwr
input
CPU write
cpurd
input
CPU read
cpube(3:0)
input
CPU byte enable
utmiclk
input
USB clock
utmilinestate(1:0)
input
USB line state
utmidatai(7:0)
input
USB parallel data input bus
utmirxvalid
input
USB receive valid
utmirxactive
input
USB receive active
utmirxerror
input
USB receive error
utmitxready
input
USB transmit ready
sramdataia(FS-1:0)
input
SRAM port A data input bus
sramdataib(FS-1:0)
input
SRAM port B data input bus
cpudatao(CS-1:0)
output CPU data output bus
irq
output CPU interrupt request
utmiopmode(1:0)
output USB operational mode
utmidatao(7:0)
output USB parallel data output bus
utmitxvalid
output USB transmit valid
utmisuspendm
output USB suspend
utmixcvrselect
output USB transceiver select
utmitermselect
output USB termination select
sramaddra(14:0)
output SRAM port A address bus
sramaddrb(14:0)
output SRAM port B address bus
sramdataoa(FS-1:0)
output SRAM port A data output bus
sramdataob(FS-1:0)
output SRAM port B data output bus
sramwea
output SRAM port A write enable
sramweb
output SRAM port B write enable
FS=8, 16, 32 equal to USB_FIFO_DATA_WIDTH;
CS=8, 16, 32 equal to USB_CPU_DATA_WIDTH;
DS=8, 16, 32 equal to USB_DMA_DATA_WIDTH;
Source code:
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VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
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Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
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Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
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IP Core implementation support
3 months maintenance
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Delivery of the IP Core and documentation updates, minor
and major versions changes
Phone & email support
SYMBOL
utmiclk
utmilinestate(1:0)
utmidatai(7:0)
utmirxvalid
utmirxactive
utmirxerror
utmitxready
utmiopmode(1:0)
utmidatao(7:0)
utmitxvalid
utmisuspendm
utmixcvrselect
utmitermselect
sramaddra(14:0)
sramaddrb(14:0)
sramdataia(FS-1:0) sramdataoa(FS-1:0)
sramdataib(FS-1:0) sramdataob(FS-1:0)
sramwea
sramweb
cpuaddress(8:0)
cpudatai(CS-1:0)
cpube(3:0)
cpurd
cpuwr
dmaaddress(3:0)
dmadatai(DS-1:0)
cpudatao(CS-1:0)
irq
dmadatao(DS-1:0)
dmabe(3:0)
dmard
dmawr
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
BLOCK DIAGRAM
utmiclk
utmilinestate(1:0)
utmidatai(7:0)
utmirxvalid
utmirxactive
utmirxerror
utmitxready
utmiopmode(1:0)
utmidatao(7:0)
utmisuspendm
utmixcvrselect
utmitermselect
utmitxvalid
cpuclk
reset
CPU
Interface
UTMI
Interface
cpurd
cpuwr
cpube(3:0)
cpuaddress(8:0)
cpudatai(CS-1:0)
cpudatao(CS-1:0)
irq
SRAM
Interface
EP0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EP10
EP11
EP12
EP13
EP14
EP15
sramaddra(14:0)
sramaddrb(14:0)
sramdataoa(FS-1:0)
sramdataob(FS-1:0)
sramwea
sramweb
sramdataia(FS-1:0)
sramdataib(FS-1:0)
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
UNITS SUMMARY
CONTACT
UTMI Interface – The UTMI interface is clocked
by UTMICLK clock and manages communication
with USB 2.0 Transceiver Macrocell. It is responsible for reset detection, speed handshake, token,
data and handshake packet reception and transmission.
Digital Core Design Headquarters:
CPU Interface – The CPU interface module is
clocked by CPUCLK clock and manages communication with some CPU. In this module DUSB2 core
configuration and status registers are being located. CPU bus size is configurable as 8, 16 or 32-bit
wide.
Distributors:
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
tel.:
fax:
Please check:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
http://dcd.pl/sales
SRAM Interface – The SRAM interface module
manages communication with Synchronous Random Access Memory. It generates address, read
and write signals for the SRAM memory and buffers data bytes during the FIFO read and write operations.
EP0 endpoint –The EP0 control endpoint is special
bidirectional endpoint, used for device configuration. It allows generic USB control and status access.
EP1-EP15 endpoints – The EP1 to EP15 data endpoints are unidirectional configurable doublebuffered endpoints, used for application specific
data transmission.
PERFORMANCE
The following tables give a survey about the Core
area and performance in ASIC Devices.
Device
0.25u typical
0.25u typical
0.18u typical
0.18u typical
0.13u typical
0.13u typical
Optimization
cpuclk Fmax
area
> 200 MHz
speed
> 200 MHz
area
> 200 MHz
speed
> 200 MHz
area
> 200 MHz
speed
> 200 MHz
Core performance in ASIC devices
utmiclk Fmax
>100 MHz
>100 MHz
>100 MHz
>100 MHz
>100 MHz
>100 MHz
An area utilized by a typical configuration of the
DUSB2 core suitable for HID and Mass Storage
devices in vendor specific technologies, are summarized in the table below.
Component
Area Gates
5400
2100
2100
9600
DUSB2+EP0
EP1 endpoint
EP2 endpoint
Total area
Core components area utilization
4
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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